1 //===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS32/64 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "MipsSERegisterInfo.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSEInstrInfo.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/DebugInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameLowering.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
42 #define DEBUG_TYPE "mips-reg-info"
44 MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &ST)
45 : MipsRegisterInfo(ST) {}
47 bool MipsSERegisterInfo::
48 requiresRegisterScavenging(const MachineFunction &MF) const {
52 bool MipsSERegisterInfo::
53 requiresFrameIndexScavenging(const MachineFunction &MF) const {
57 const TargetRegisterClass *
58 MipsSERegisterInfo::intRegClass(unsigned Size) const {
60 return &Mips::GPR32RegClass;
63 return &Mips::GPR64RegClass;
66 /// Get the size of the offset supported by the given load/store.
67 /// The result includes the effects of any scale factors applied to the
68 /// instruction immediate.
69 static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode) {
76 return 10 + 1 /* scale factor */;
79 return 10 + 2 /* scale factor */;
82 return 10 + 3 /* scale factor */;
88 /// Get the scale factor applied to the immediate in the given load/store.
89 static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
105 void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
106 unsigned OpNo, int FrameIndex,
108 int64_t SPOffset) const {
109 MachineInstr &MI = *II;
110 MachineFunction &MF = *MI.getParent()->getParent();
111 MachineFrameInfo *MFI = MF.getFrameInfo();
112 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
114 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
119 MinCSFI = CSI[0].getFrameIdx();
120 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
123 bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
125 // The following stack frame objects are always referenced relative to $sp:
126 // 1. Outgoing arguments.
127 // 2. Pointer to dynamically allocated stack space.
128 // 3. Locations for callee-saved registers.
129 // 4. Locations for eh data registers.
130 // Everything else is referenced relative to whatever register
131 // getFrameRegister() returns.
134 if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI)
135 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
137 FrameReg = getFrameRegister(MF);
139 // Calculate final offset.
140 // - There is no need to change the offset if the frame object is one of the
141 // following: an outgoing argument, pointer to a dynamically allocated
142 // stack space or a $gp restore location,
143 // - If the frame object is any of the following, its offset must be adjusted
144 // by adding the size of the stack:
145 // incoming argument, callee-saved register location or local variable.
149 Offset = SPOffset + (int64_t)StackSize;
150 Offset += MI.getOperand(OpNo + 1).getImm();
152 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
154 if (!MI.isDebugValue()) {
155 // Make sure Offset fits within the field available.
156 // For MSA instructions, this is a 10-bit signed immediate (scaled by
157 // element size), otherwise it is a 16-bit signed immediate.
158 unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode());
159 unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode());
161 if (OffsetBitSize < 16 && isInt<16>(Offset) &&
162 (!isIntN(OffsetBitSize, Offset) ||
163 OffsetToAlignment(Offset, OffsetAlign) != 0)) {
164 // If we have an offset that needs to fit into a signed n-bit immediate
165 // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
166 MachineBasicBlock &MBB = *MI.getParent();
167 DebugLoc DL = II->getDebugLoc();
168 unsigned ADDiu = Subtarget.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
169 const TargetRegisterClass *RC =
170 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
171 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
172 unsigned Reg = RegInfo.createVirtualRegister(RC);
173 const MipsSEInstrInfo &TII =
174 *static_cast<const MipsSEInstrInfo *>(
175 MBB.getParent()->getSubtarget().getInstrInfo());
176 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset);
181 } else if (!isInt<16>(Offset)) {
182 // Otherwise split the offset into 16-bit pieces and add it in multiple
184 MachineBasicBlock &MBB = *MI.getParent();
185 DebugLoc DL = II->getDebugLoc();
186 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
188 const MipsSEInstrInfo &TII =
189 *static_cast<const MipsSEInstrInfo *>(
190 MBB.getParent()->getSubtarget().getInstrInfo());
191 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
192 OffsetBitSize == 16 ? &NewImm : nullptr);
193 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
194 .addReg(Reg, RegState::Kill);
197 Offset = SignExtend64<16>(NewImm);
202 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
203 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);