1 //===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the MIPS32/64 implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "MipsSERegisterInfo.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSEInstrInfo.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/DebugInfo.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
43 MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &ST)
44 : MipsRegisterInfo(ST) {}
46 bool MipsSERegisterInfo::
47 requiresRegisterScavenging(const MachineFunction &MF) const {
51 bool MipsSERegisterInfo::
52 requiresFrameIndexScavenging(const MachineFunction &MF) const {
56 const TargetRegisterClass *
57 MipsSERegisterInfo::intRegClass(unsigned Size) const {
59 return &Mips::GPR32RegClass;
62 return &Mips::GPR64RegClass;
65 /// Get the size of the offset supported by the given load/store.
66 /// The result includes the effects of any scale factors applied to the
67 /// instruction immediate.
68 static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode) {
75 return 10 + 1 /* scale factor */;
78 return 10 + 2 /* scale factor */;
81 return 10 + 3 /* scale factor */;
87 /// Get the scale factor applied to the immediate in the given load/store.
88 static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
104 void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
105 unsigned OpNo, int FrameIndex,
107 int64_t SPOffset) const {
108 MachineInstr &MI = *II;
109 MachineFunction &MF = *MI.getParent()->getParent();
110 MachineFrameInfo *MFI = MF.getFrameInfo();
111 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
113 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
118 MinCSFI = CSI[0].getFrameIdx();
119 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
122 bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
124 // The following stack frame objects are always referenced relative to $sp:
125 // 1. Outgoing arguments.
126 // 2. Pointer to dynamically allocated stack space.
127 // 3. Locations for callee-saved registers.
128 // 4. Locations for eh data registers.
129 // Everything else is referenced relative to whatever register
130 // getFrameRegister() returns.
133 if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI)
134 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
136 FrameReg = getFrameRegister(MF);
138 // Calculate final offset.
139 // - There is no need to change the offset if the frame object is one of the
140 // following: an outgoing argument, pointer to a dynamically allocated
141 // stack space or a $gp restore location,
142 // - If the frame object is any of the following, its offset must be adjusted
143 // by adding the size of the stack:
144 // incoming argument, callee-saved register location or local variable.
148 Offset = SPOffset + (int64_t)StackSize;
149 Offset += MI.getOperand(OpNo + 1).getImm();
151 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
153 if (!MI.isDebugValue()) {
154 // Make sure Offset fits within the field available.
155 // For MSA instructions, this is a 10-bit signed immediate (scaled by
156 // element size), otherwise it is a 16-bit signed immediate.
157 unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode());
158 unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode());
160 if (OffsetBitSize < 16 && isInt<16>(Offset) &&
161 (!isIntN(OffsetBitSize, Offset) ||
162 OffsetToAlignment(Offset, OffsetAlign) != 0)) {
163 // If we have an offset that needs to fit into a signed n-bit immediate
164 // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
165 MachineBasicBlock &MBB = *MI.getParent();
166 DebugLoc DL = II->getDebugLoc();
167 unsigned ADDiu = Subtarget.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
168 const TargetRegisterClass *RC =
169 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
170 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
171 unsigned Reg = RegInfo.createVirtualRegister(RC);
172 const MipsSEInstrInfo &TII =
173 *static_cast<const MipsSEInstrInfo *>(
174 MBB.getParent()->getTarget().getInstrInfo());
175 BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset);
180 } else if (!isInt<16>(Offset)) {
181 // Otherwise split the offset into 16-bit pieces and add it in multiple
183 MachineBasicBlock &MBB = *MI.getParent();
184 DebugLoc DL = II->getDebugLoc();
185 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
187 const MipsSEInstrInfo &TII =
188 *static_cast<const MipsSEInstrInfo *>(
189 MBB.getParent()->getTarget().getInstrInfo());
190 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
191 OffsetBitSize == 16 ? &NewImm : NULL);
192 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
193 .addReg(Reg, RegState::Kill);
196 Offset = SignExtend64<16>(NewImm);
201 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
202 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);