1 //==- MipsScheduleP5600.td - P5600 Scheduling Definitions --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def MipsP5600Model : SchedMachineModel {
11 int IssueWidth = 2; // 2x dispatched per cycle
12 int MicroOpBufferSize = 48; // min(48, 48, 64)
14 int MispredictPenalty = 8; // TODO: Estimated
16 let CompleteModel = 1;
19 let SchedModel = MipsP5600Model in {
24 def P5600ALQ : ProcResource<1> { let BufferSize = 16; }
25 def P5600IssueALU : ProcResource<1> { let Super = P5600ALQ; }
30 def P5600WriteALU : SchedWriteRes<[P5600IssueALU]>;
32 // and, lui, nor, or, slti, sltiu, sub, subu, xor
33 def : ItinRW<[P5600WriteALU],
34 [II_AND, II_LUI, II_NOR, II_OR, II_SLTI_SLTIU, II_SUBU, II_XOR]>;
39 def P5600AGQ : ProcResource<3> { let BufferSize = 16; }
40 def P5600IssueAL2 : ProcResource<1> { let Super = P5600AGQ; }
41 def P5600IssueCTISTD : ProcResource<1> { let Super = P5600AGQ; }
42 def P5600IssueLDST : ProcResource<1> { let Super = P5600AGQ; }
44 def P5600AL2Div : ProcResource<1>;
45 // Pseudo-resource used to block CTISTD when handling multi-pipeline splits.
46 def P5600CTISTD : ProcResource<1>;
51 def P5600WriteJump : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]>;
52 def P5600WriteJumpAndLink : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]> {
56 // b, beq, beql, bg[et]z, bl[et]z, bne, bnel, j, syscall, jal, bltzal, jalx,
58 def : ItinRW<[P5600WriteJump], [II_B, II_BCC, II_BCCZ, II_BCCZAL, II_J, II_JR]>;
59 def : ItinRW<[P5600WriteJumpAndLink], [II_JAL, II_JALR]>;
64 def P5600WriteLoad : SchedWriteRes<[P5600IssueLDST]> {
68 def P5600WriteLoadShifted : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> {
72 def P5600WritePref : SchedWriteRes<[P5600IssueLDST]>;
74 def P5600WriteStore : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> {
75 // FIXME: This is a bit pessimistic. P5600CTISTD is only used during cycle 2
76 // not during 0, 1, and 2.
77 let ResourceCycles = [ 1, 3 ];
80 def P5600WriteGPRFromBypass : SchedWriteRes<[P5600IssueLDST]> {
84 def P5600WriteStoreFromOtherUnits : SchedWriteRes<[P5600IssueLDST]>;
85 def P5600WriteLoadToOtherUnits : SchedWriteRes<[P5600IssueLDST]> {
90 def : ItinRW<[P5600WriteLoad], [II_LB, II_LBU, II_LH, II_LHU, II_LW, II_LWU]>;
93 def : ItinRW<[P5600WriteLoadShifted], [II_LWL, II_LWR]>;
96 def : ItinRW<[P5600WriteStore], [II_SB, II_SH, II_SW, II_SWL, II_SWR]>;
99 // (this instruction does not exist in the backend yet)
100 def : ItinRW<[P5600WritePref], []>;
103 // (this instruction does not exist in the backend yet)
104 def : ItinRW<[P5600WriteStore], []>;
106 // LDST is also used in moves from general purpose registers to floating point
108 def P5600WriteMoveGPRToOtherUnits : SchedWriteRes<[P5600IssueLDST]> {
115 def P5600WriteAL2 : SchedWriteRes<[P5600IssueAL2]>;
116 def P5600WriteAL2BitExt : SchedWriteRes<[P5600IssueAL2]> { let Latency = 2; }
117 def P5600WriteAL2ShadowMov : SchedWriteRes<[P5600IssueAL2]> { let Latency = 2; }
118 def P5600WriteAL2CondMov : SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> {
121 def P5600WriteAL2Div : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> {
122 // Estimated worst case
124 let ResourceCycles = [1, 34];
126 def P5600WriteAL2DivU : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> {
127 // Estimated worst case
129 let ResourceCycles = [1, 34];
131 def P5600WriteAL2Mul : SchedWriteRes<[P5600IssueAL2]> { let Latency = 3; }
132 def P5600WriteAL2Mult: SchedWriteRes<[P5600IssueAL2]> { let Latency = 5; }
133 def P5600WriteAL2MAdd: SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> {
137 // clo, clz, di, mfhi, mflo
138 def : ItinRW<[P5600WriteAL2], [II_CLO, II_CLZ, II_MFHI_MFLO]>;
140 // ehb, rdhwr, rdpgpr, wrpgpr, wsbh
141 def : ItinRW<[P5600WriteAL2ShadowMov], [II_RDHWR]>;
144 def : ItinRW<[P5600WriteAL2CondMov], [II_MOVN, II_MOVZ]>;
147 def : ItinRW<[P5600WriteAL2Div], [II_DIV]>;
148 def : ItinRW<[P5600WriteAL2DivU], [II_DIVU]>;
151 def : ItinRW<[P5600WriteAL2Mul], [II_MUL]>;
153 def : ItinRW<[P5600WriteAL2Mult], [II_MULT, II_MULTU]>;
154 // maddu?, msubu?, mthi, mtlo
155 def : ItinRW<[P5600WriteAL2MAdd],
156 [II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_MTHI_MTLO]>;
159 def : ItinRW<[P5600WriteAL2BitExt],
162 // Either ALU or AL2 Pipelines
163 // ---------------------------
165 // Some instructions can choose between ALU and AL2, but once dispatched to
166 // ALQ or AGQ respectively they are committed to that path.
167 // The decision is based on the outcome of the most recent selection when the
168 // choice was last available. For now, we assume ALU is always chosen.
170 def P5600WriteEitherALU : SchedWriteVariant<
171 // FIXME: Implement selection predicate
172 [SchedVar<SchedPredicate<[{1}]>, [P5600WriteALU]>,
173 SchedVar<SchedPredicate<[{0}]>, [P5600WriteAL2]>
176 // add, addi, addiu, addu, andi, ori, rotr, se[bh], sllv?, sr[al]v?, slt, sltu,
178 def : ItinRW<[P5600WriteEitherALU],
179 [II_ADDI, II_ADDIU, II_ANDI, II_ORI, II_ROTR, II_SEB, II_SEH,
180 II_SLT_SLTU, II_SLL, II_SRA, II_SRL, II_XORI, II_ADDU, II_SLLV,
186 def P5600FPQ : ProcResource<3> { let BufferSize = 16; }
187 def P5600IssueFPUS : ProcResource<1> { let Super = P5600FPQ; }
188 def P5600IssueFPUL : ProcResource<1> { let Super = P5600FPQ; }
189 def P5600IssueFPULoad : ProcResource<1> { let Super = P5600FPQ; }
191 def P5600FPUDivSqrt : ProcResource<2>;
193 def P5600WriteFPUS : SchedWriteRes<[P5600IssueFPUS]>;
194 def P5600WriteFPUL : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 4; }
195 def P5600WriteFPUL_MADDSUB : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 6; }
196 def P5600WriteFPUDivS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
197 // Best/Common/Worst case = 7 / 23 / 27
198 let Latency = 23; // Using common case
199 let ResourceCycles = [ 1, 23 ];
201 def P5600WriteFPUDivD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
202 // Best/Common/Worst case = 7 / 31 / 35
203 let Latency = 31; // Using common case
204 let ResourceCycles = [ 1, 31 ];
206 def P5600WriteFPURcpS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
207 // Best/Common/Worst case = 7 / 19 / 23
208 let Latency = 19; // Using common case
209 let ResourceCycles = [ 1, 19 ];
211 def P5600WriteFPURcpD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
212 // Best/Common/Worst case = 7 / 27 / 31
213 let Latency = 27; // Using common case
214 let ResourceCycles = [ 1, 27 ];
216 def P5600WriteFPURsqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
217 // Best/Common/Worst case = 7 / 27 / 27
218 let Latency = 27; // Using common case
219 let ResourceCycles = [ 1, 27 ];
221 def P5600WriteFPURsqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
222 // Best/Common/Worst case = 7 / 27 / 31
223 let Latency = 27; // Using common case
224 let ResourceCycles = [ 1, 27 ];
226 def P5600WriteFPUSqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
227 // Best/Common/Worst case = 7 / 27 / 31
228 let Latency = 27; // Using common case
229 let ResourceCycles = [ 1, 27 ];
231 def P5600WriteFPUSqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
232 // Best/Common/Worst case = 7 / 35 / 39
233 let Latency = 35; // Using common case
234 let ResourceCycles = [ 1, 35 ];
236 def P5600WriteMSAShortLogic : SchedWriteRes<[P5600IssueFPUS]>;
237 def P5600WriteMSAShortInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 2; }
238 def P5600WriteMoveOtherUnitsToFPU : SchedWriteRes<[P5600IssueFPUS]>;
240 // FPUS is also used in moves from floating point and MSA registers to general
241 // purpose registers.
242 def P5600WriteMoveFPUSToOtherUnits : SchedWriteRes<[P5600IssueFPUS]> {
246 // FPUL is also used in moves from floating point and MSA registers to general
247 // purpose registers.
248 def P5600WriteMoveFPULToOtherUnits : SchedWriteRes<[P5600IssueFPUL]>;
253 // abs.[ds], abs.ps, bc1[tf]l?, mov[tf].[ds], mov[tf], mov.[ds], [cm][ft]c1,
254 // m[ft]hc1, neg.[ds], neg.ps, nor.v, nori.b, or.v, ori.b, xor.v, xori.b,
255 // sdxc1, sdc1, st.[bhwd], swc1, swxc1
256 def : ItinRW<[P5600WriteFPUS], [II_ABS, II_MOVF_D, II_MOVF_S, II_MOVT_D,
257 II_MOVT_S, II_MOV_D, II_MOV_S, II_NEG]>;
259 // adds_a.[bhwd], adds_[asu].[bhwd], addvi?.[bhwd], asub_[us].[bhwd],
261 def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADD_A_[BHWD]$")>;
262 def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADDS_[ASU]_[BHWD]$")>;
263 // TODO: ADDVI_[BHW] might be 1 cycle latency rather than 2. Need to confirm it.
264 def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADDVI?_[BHWD]$")>;
265 def : InstRW<[P5600WriteMSAShortInt], (instregex "^ASUB_[US].[BHWD]$")>;
266 def : InstRW<[P5600WriteMSAShortInt], (instregex "^AVER?_[US].[BHWD]$")>;
268 // and.v, andi.b, move.v, ldi.[bhwd]
269 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^MOVE_V$")>;
270 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^LDI_[BHWD]$")>;
271 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)_V$")>;
272 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>;
277 // add.[ds], add.ps, cvt.d.[sw], cvt.s.[dw], cvt.w.[sd], cvt.[sw].ps,
278 // cvt.ps.[sw], c.<cc>.[ds], c.<cc>.ps, mul.[ds], mul.ps, sub.[ds], sub.ps,
279 // trunc.w.[ds], trunc.w.ps
280 def : ItinRW<[P5600WriteFPUL],
281 [II_ADD_D, II_ADD_S, II_CVT, II_C_CC_D, II_C_CC_S, II_MUL_D,
282 II_MUL_S, II_SUB_D, II_SUB_S, II_TRUNC]>;
285 def : ItinRW<[P5600WriteFPUDivS], [II_DIV_S]>;
286 def : ItinRW<[P5600WriteFPUDivD], [II_DIV_D]>;
288 // sqrt.[ds], sqrt.ps
289 def : ItinRW<[P5600WriteFPUSqrtS], [II_SQRT_S]>;
290 def : ItinRW<[P5600WriteFPUSqrtD], [II_SQRT_D]>;
292 // madd.[ds], msub.[ds], nmadd.[ds], nmsub.[ds],
293 // Operand 0 is read on cycle 5. All other operands are read on operand 0.
294 def : ItinRW<[SchedReadAdvance<5>, P5600WriteFPUL_MADDSUB],
295 [II_MADD_D, II_MADD_S, II_MSUB_D, II_MSUB_S, II_NMADD_D,
296 II_NMADD_S, II_NMSUB_D, II_NMSUB_S]>;
298 // madd.ps, msub.ps, nmadd.ps, nmsub.ps
299 // Operand 0 and 1 are read on cycle 5. All others are read on operand 0.
300 // (none of these instructions exist in the backend yet)
305 // This is typically used in conjunction with the load pipeline under the AGQ
306 // All the instructions are in the 'Tricky Instructions' section.
308 def P5600WriteLoadOtherUnitsToFPU : SchedWriteRes<[P5600IssueFPULoad]> {
312 // Tricky Instructions
313 // ===================
315 // These instructions are split across multiple uops (in different pipelines)
316 // that must cooperate to complete the operation
318 // FIXME: This isn't quite right since the implementation of WriteSequence
319 // current aggregates the resources and ignores the exact cycle they are
321 def P5600WriteMoveGPRToFPU : WriteSequence<[P5600WriteMoveGPRToOtherUnits,
322 P5600WriteMoveOtherUnitsToFPU]>;
324 // FIXME: This isn't quite right since the implementation of WriteSequence
325 // current aggregates the resources and ignores the exact cycle they are
327 def P5600WriteMoveFPUToGPR : WriteSequence<[P5600WriteMoveFPUSToOtherUnits,
328 P5600WriteGPRFromBypass]>;
330 // FIXME: This isn't quite right since the implementation of WriteSequence
331 // current aggregates the resources and ignores the exact cycle they are
333 def P5600WriteStoreFPUS : WriteSequence<[P5600WriteMoveFPUSToOtherUnits,
334 P5600WriteStoreFromOtherUnits]>;
336 // FIXME: This isn't quite right since the implementation of WriteSequence
337 // current aggregates the resources and ignores the exact cycle they are
339 def P5600WriteStoreFPUL : WriteSequence<[P5600WriteMoveFPULToOtherUnits,
340 P5600WriteStoreFromOtherUnits]>;
342 // FIXME: This isn't quite right since the implementation of WriteSequence
343 // current aggregates the resources and ignores the exact cycle they are
345 def P5600WriteLoadFPU : WriteSequence<[P5600WriteLoadToOtherUnits,
346 P5600WriteLoadOtherUnitsToFPU]>;
349 def : ItinRW<[P5600WriteMoveGPRToFPU], [II_CTC1, II_MTC1, II_MTHC1]>;
351 // bc1[ft], cfc1, mfc1, mfhc1, movf, movt
352 def : ItinRW<[P5600WriteMoveFPUToGPR],
353 [II_BC1F, II_BC1T, II_CFC1, II_MFC1, II_MFHC1, II_MOVF, II_MOVT]>;
355 // swc1, swxc1, st.[bhwd]
356 def : ItinRW<[P5600WriteStoreFPUS], [II_SWC1, II_SWXC1]>;
357 def : InstRW<[P5600WriteStoreFPUS], (instregex "^ST_[BHWD]$")>;
359 // movn.[ds], movz.[ds]
360 def : ItinRW<[P5600WriteStoreFPUL], [II_MOVN_D, II_MOVN_S, II_MOVZ_D, II_MOVZ_S]>;
362 // l[dw]x?c1, ld.[bhwd]
363 def : ItinRW<[P5600WriteLoadFPU], [II_LDC1, II_LDXC1, II_LWC1, II_LWXC1]>;
364 def : InstRW<[P5600WriteLoadFPU], (instregex "LD_[BHWD]")>;
366 // Unsupported Instructions
367 // ========================
369 // The following instruction classes are never valid on P5600.
370 // II_DADDIU, II_DADDU, II_DMFC1, II_DMTC1, II_DMULT, II_DMULTU, II_DROTR,
371 // II_DROTR32, II_DROTRV, II_DDIV, II_DSLL, II_DSLL32, II_DSLLV, II_DSRA,
372 // II_DSRA32, II_DSRAV, II_DSRL, II_DSRL32, II_DSRLV, II_DSUBU, II_DDIVU,
373 // II_JALRC, II_LD, II_LD[LR], II_LUXC1, II_RESTORE, II_SAVE, II_SD, II_SDC1,
374 // II_SDL, II_SDR, II_SDXC1
376 // The following instructions are never valid on P5600.
377 // addq.ph, rdhwr, repl.ph, repl.qb, subq.ph, subu_s.qb
382 // This section is largely temporary guesswork.
384 // ceil.[lw].[ds], floor.[lw].[ds]
385 // Reason behind guess: trunc.[lw].ds and the various cvt's are in FPUL
386 def : ItinRW<[P5600WriteFPUL], [II_CEIL, II_FLOOR, II_ROUND]>;
389 // Reason behind guess: rotr is in the same category and the two register forms
390 // generally follow the immediate forms in this category
391 def : ItinRW<[P5600WriteEitherALU], [II_ROTRV]>;