1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "MipsMachineFunction.h"
16 #include "MipsRegisterInfo.h"
17 #include "MipsSubtarget.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "mips-subtarget"
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "MipsGenSubtargetInfo.inc"
34 // FIXME: Maybe this should be on by default when Mips16 is specified
37 Mixed16_32("mips-mixed-16-32", cl::init(false),
38 cl::desc("Allow for a mixture of Mips16 "
39 "and Mips32 code in a single output file"),
42 static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false),
43 cl::desc("Compile all functions that don't use "
44 "floating point as Mips 16"),
47 static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
48 cl::desc("Enable mips16 hard float."),
52 Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
53 cl::desc("Enable mips16 constant islands."),
57 GPOpt("mgpopt", cl::Hidden,
58 cl::desc("Enable gp-relative addressing of mips small data items"));
60 void MipsSubtarget::anchor() { }
62 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
63 const std::string &FS, bool little,
64 const MipsTargetMachine &TM)
65 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
66 IsLittle(little), IsSingleFloat(false), IsFPXX(false), NoABICalls(false),
67 IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
68 IsGP64bit(false), HasVFPU(false), HasCnMips(false), HasMips3_32(false),
69 HasMips3_32r2(false), HasMips4_32(false), HasMips4_32r2(false),
70 HasMips5_32r2(false), InMips16Mode(false),
71 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
72 HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
73 HasMSA(false), TM(TM), TargetTriple(TT), TSInfo(*TM.getDataLayout()),
75 MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
76 FrameLowering(MipsFrameLowering::create(*this)),
77 TLInfo(MipsTargetLowering::create(TM, *this)) {
79 PreviousInMips16Mode = InMips16Mode;
81 if (MipsArchVersion == MipsDefault)
82 MipsArchVersion = Mips32;
84 // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
85 // been tested and currently exist for the integrated assembler only.
86 if (MipsArchVersion == Mips1)
87 report_fatal_error("Code generation for MIPS-I is not implemented", false);
88 if (MipsArchVersion == Mips5)
89 report_fatal_error("Code generation for MIPS-V is not implemented", false);
91 // Check if Architecture and ABI are compatible.
92 assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
93 (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
94 "Invalid Arch & ABI pair.");
96 if (hasMSA() && !isFP64bit())
97 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
101 if (!isABI_O32() && !useOddSPReg())
102 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
104 if (IsFPXX && (isABI_N32() || isABI_N64()))
105 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
108 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
113 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
116 if (NoABICalls && TM.getRelocationModel() == Reloc::PIC_)
117 report_fatal_error("position-independent code requires '-mabicalls'");
119 // Set UseSmallSection.
120 UseSmallSection = GPOpt;
121 if (!NoABICalls && GPOpt) {
122 errs() << "warning: cannot use small-data accesses for '-mabicalls'"
124 UseSmallSection = false;
128 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
129 bool MipsSubtarget::enablePostMachineScheduler() const { return true; }
131 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
132 CriticalPathRCs.clear();
133 CriticalPathRCs.push_back(isGP64bit() ?
134 &Mips::GPR64RegClass : &Mips::GPR32RegClass);
137 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
138 return CodeGenOpt::Aggressive;
142 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
143 const TargetMachine &TM) {
144 std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
146 // Parse features string.
147 ParseSubtargetFeatures(CPUName, FS);
148 // Initialize scheduling itinerary for the specified CPU.
149 InstrItins = getInstrItineraryForCPU(CPUName);
151 if (InMips16Mode && !TM.Options.UseSoftFloat)
152 InMips16HardFloat = true;
157 bool MipsSubtarget::abiUsesSoftFloat() const {
158 return TM.Options.UseSoftFloat && !InMips16HardFloat;
161 bool MipsSubtarget::useConstantIslands() {
162 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
163 return Mips16ConstantIslands;
166 Reloc::Model MipsSubtarget::getRelocationModel() const {
167 return TM.getRelocationModel();
170 bool MipsSubtarget::isABI_EABI() const { return getABI().IsEABI(); }
171 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
172 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
173 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
174 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }