1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "MipsSubtarget.h"
16 #include "MipsRegisterInfo.h"
17 #include "llvm/Support/TargetRegistry.h"
19 #define GET_SUBTARGETINFO_TARGET_DESC
20 #define GET_SUBTARGETINFO_CTOR
21 #include "MipsGenSubtargetInfo.inc"
25 void MipsSubtarget::anchor() { }
27 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
28 const std::string &FS, bool little,
30 MipsGenSubtargetInfo(TT, CPU, FS),
31 MipsArchVersion(Mips32), MipsABI(UnknownABI), IsLittle(little),
32 IsSingleFloat(false), IsFP64bit(false), IsGP64bit(false), HasVFPU(false),
33 IsLinux(true), HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false),
34 HasMinMax(false), HasSwap(false), HasBitCount(false), InMips16Mode(false),
35 HasDSP(false), HasDSPR2(false), IsAndroid(false)
37 std::string CPUName = CPU;
41 // Parse features string.
42 ParseSubtargetFeatures(CPUName, FS);
44 // Initialize scheduling itinerary for the specified CPU.
45 InstrItins = getInstrItineraryForCPU(CPUName);
47 // Set MipsABI if it hasn't been set yet.
48 if (MipsABI == UnknownABI)
49 MipsABI = hasMips64() ? N64 : O32;
51 // Check if Architecture and ABI are compatible.
52 assert(((!hasMips64() && (isABI_O32() || isABI_EABI())) ||
53 (hasMips64() && (isABI_N32() || isABI_N64()))) &&
54 "Invalid Arch & ABI pair.");
56 // Is the target system Linux ?
57 if (TT.find("linux") == std::string::npos)
60 // Set UseSmallSection.
61 UseSmallSection = !IsLinux && (RM == Reloc::Static);
65 MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel,
66 TargetSubtargetInfo::AntiDepBreakMode &Mode,
67 RegClassVector &CriticalPathRCs) const {
68 Mode = TargetSubtargetInfo::ANTIDEP_NONE;
69 CriticalPathRCs.clear();
70 CriticalPathRCs.push_back(hasMips64() ?
71 &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass);
72 return OptLevel >= CodeGenOpt::Aggressive;