1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "MipsMachineFunction.h"
16 #include "MipsRegisterInfo.h"
17 #include "MipsSubtarget.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "mips-subtarget"
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "MipsGenSubtargetInfo.inc"
34 // FIXME: Maybe this should be on by default when Mips16 is specified
36 static cl::opt<bool> Mixed16_32(
39 cl::desc("Allow for a mixture of Mips16 "
40 "and Mips32 code in a single source file"),
43 static cl::opt<bool> Mips_Os16(
46 cl::desc("Compile all functions that don' use "
47 "floating point as Mips 16"),
51 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
52 cl::desc("MIPS: mips16 hard float enable."),
56 Mips16ConstantIslands(
57 "mips16-constant-islands", cl::NotHidden,
58 cl::desc("MIPS: mips16 constant islands enable."),
61 /// Select the Mips CPU for the given triple and cpu name.
62 /// FIXME: Merge with the copy in MipsMCTargetDesc.cpp
63 static StringRef selectMipsCPU(Triple TT, StringRef CPU) {
64 if (CPU.empty() || CPU == "generic") {
65 if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
73 void MipsSubtarget::anchor() { }
75 static std::string computeDataLayout(const MipsSubtarget &ST) {
78 // There are both little and big endian mips.
86 // Pointers are 32 bit on some ABIs.
90 // 8 and 16 bit integers only need no have natural alignment, but try to
91 // align them to 32 bits. 64 bit integers have natural alignment.
92 Ret += "-i8:8:32-i16:16:32-i64:64";
94 // 32 bit registers are always available and the stack is at least 64 bit
95 // aligned. On N64 64 bit registers are also available and the stack is
97 if (ST.isABI_N64() || ST.isABI_N32())
98 Ret += "-n32:64-S128";
105 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
106 const std::string &FS, bool little,
107 MipsTargetMachine *_TM)
108 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
109 MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
110 IsFPXX(false), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
111 IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
112 IsLinux(true), HasMips3_32(false), HasMips3_32r2(false),
113 HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
114 InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
115 InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
116 AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
117 HasMSA(false), TM(_TM), TargetTriple(TT),
118 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
119 TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*this)),
120 FrameLowering(MipsFrameLowering::create(*this)),
121 TLInfo(MipsTargetLowering::create(*TM, *this)) {
123 PreviousInMips16Mode = InMips16Mode;
125 // Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
126 // MIPS-V. They have not been tested and currently exist for the integrated
128 if (MipsArchVersion == Mips1)
129 report_fatal_error("Code generation for MIPS-I is not implemented", false);
130 if (MipsArchVersion == Mips2)
131 report_fatal_error("Code generation for MIPS-II is not implemented", false);
132 if (MipsArchVersion == Mips3)
133 report_fatal_error("Code generation for MIPS-III is not implemented",
135 if (MipsArchVersion == Mips5)
136 report_fatal_error("Code generation for MIPS-V is not implemented", false);
138 // Assert exactly one ABI was chosen.
139 assert(MipsABI != UnknownABI);
140 assert((((getFeatureBits() & Mips::FeatureO32) != 0) +
141 ((getFeatureBits() & Mips::FeatureEABI) != 0) +
142 ((getFeatureBits() & Mips::FeatureN32) != 0) +
143 ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
145 // Check if Architecture and ABI are compatible.
146 assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
147 (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
148 "Invalid Arch & ABI pair.");
150 if (hasMSA() && !isFP64bit())
151 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
155 if (!isABI_O32() && !useOddSPReg())
156 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
158 if (IsFPXX && (isABI_N32() || isABI_N64()))
159 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
162 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
167 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
170 // Is the target system Linux ?
171 if (TT.find("linux") == std::string::npos)
174 // Set UseSmallSection.
175 // TODO: Investigate the IsLinux check. I suspect it's really checking for
177 UseSmallSection = !IsLinux && (TM->getRelocationModel() == Reloc::Static);
180 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
181 bool MipsSubtarget::enablePostMachineScheduler() const { return true; }
183 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
184 CriticalPathRCs.clear();
185 CriticalPathRCs.push_back(isGP64bit() ?
186 &Mips::GPR64RegClass : &Mips::GPR32RegClass);
189 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
190 return CodeGenOpt::Aggressive;
194 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
195 const TargetMachine *TM) {
196 std::string CPUName = selectMipsCPU(TargetTriple, CPU);
198 // Parse features string.
199 ParseSubtargetFeatures(CPUName, FS);
200 // Initialize scheduling itinerary for the specified CPU.
201 InstrItins = getInstrItineraryForCPU(CPUName);
203 if (InMips16Mode && !TM->Options.UseSoftFloat)
204 InMips16HardFloat = true;
209 bool MipsSubtarget::abiUsesSoftFloat() const {
210 return TM->Options.UseSoftFloat && !InMips16HardFloat;
213 bool MipsSubtarget::useConstantIslands() {
214 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
215 return Mips16ConstantIslands;
218 Reloc::Model MipsSubtarget::getRelocationModel() const {
219 return TM->getRelocationModel();