1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "MipsMachineFunction.h"
16 #include "MipsRegisterInfo.h"
17 #include "MipsSubtarget.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "mips-subtarget"
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "MipsGenSubtargetInfo.inc"
34 // FIXME: Maybe this should be on by default when Mips16 is specified
36 static cl::opt<bool> Mixed16_32(
39 cl::desc("Allow for a mixture of Mips16 "
40 "and Mips32 code in a single source file"),
43 static cl::opt<bool> Mips_Os16(
46 cl::desc("Compile all functions that don' use "
47 "floating point as Mips 16"),
51 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
52 cl::desc("MIPS: mips16 hard float enable."),
56 Mips16ConstantIslands(
57 "mips16-constant-islands", cl::NotHidden,
58 cl::desc("MIPS: mips16 constant islands enable."),
61 /// Select the Mips CPU for the given triple and cpu name.
62 /// FIXME: Merge with the copy in MipsMCTargetDesc.cpp
63 static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) {
64 if (CPU.empty() || CPU == "generic") {
66 if (TheTriple.getArch() == Triple::mips ||
67 TheTriple.getArch() == Triple::mipsel)
75 void MipsSubtarget::anchor() { }
77 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
78 const std::string &FS, bool little,
79 Reloc::Model _RM, MipsTargetMachine *_TM)
80 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
81 MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
82 IsFP64bit(false), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false),
83 HasCnMips(false), IsLinux(true), HasMips3_32(false), HasMips4_32(false),
84 HasMips4_32r2(false), HasSEInReg(false), HasSwap(false),
85 HasBitCount(false), InMips16Mode(false),
86 InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
87 HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
88 HasMSA(false), RM(_RM), OverrideMode(NoOverride), TM(_TM),
90 std::string CPUName = CPU;
91 CPUName = selectMipsCPU(TT, CPUName);
93 // Parse features string.
94 ParseSubtargetFeatures(CPUName, FS);
96 if (InMips16Mode && !TM->Options.UseSoftFloat) {
97 // Hard float for mips16 means essentially to compile as soft float
98 // but to use a runtime library for soft float that is written with
99 // native mips32 floating point instructions (those runtime routines
100 // run in mips32 hard float mode).
101 TM->Options.UseSoftFloat = true;
102 TM->Options.FloatABIType = FloatABI::Soft;
103 InMips16HardFloat = true;
106 PreviousInMips16Mode = InMips16Mode;
108 // Initialize scheduling itinerary for the specified CPU.
109 InstrItins = getInstrItineraryForCPU(CPUName);
111 // Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
112 // MIPS-V. They have not been tested and currently exist for the integrated
114 if (MipsArchVersion == Mips1)
115 report_fatal_error("Code generation for MIPS-I is not implemented", false);
116 if (MipsArchVersion == Mips2)
117 report_fatal_error("Code generation for MIPS-II is not implemented", false);
118 if (MipsArchVersion == Mips3)
119 report_fatal_error("Code generation for MIPS-III is not implemented",
121 if (MipsArchVersion == Mips5)
122 report_fatal_error("Code generation for MIPS-V is not implemented", false);
124 // Assert exactly one ABI was chosen.
125 assert(MipsABI != UnknownABI);
126 assert((((getFeatureBits() & Mips::FeatureO32) != 0) +
127 ((getFeatureBits() & Mips::FeatureEABI) != 0) +
128 ((getFeatureBits() & Mips::FeatureN32) != 0) +
129 ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
131 // Check if Architecture and ABI are compatible.
132 assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
133 (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
134 "Invalid Arch & ABI pair.");
136 if (hasMSA() && !isFP64bit())
137 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
142 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
147 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
150 // Is the target system Linux ?
151 if (TT.find("linux") == std::string::npos)
154 // Set UseSmallSection.
155 // TODO: Investigate the IsLinux check. I suspect it's really checking for
157 UseSmallSection = !IsLinux && (RM == Reloc::Static);
158 // set some subtarget specific features
164 MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel,
165 TargetSubtargetInfo::AntiDepBreakMode &Mode,
166 RegClassVector &CriticalPathRCs) const {
167 Mode = TargetSubtargetInfo::ANTIDEP_NONE;
168 CriticalPathRCs.clear();
169 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
170 : &Mips::GPR32RegClass);
171 return OptLevel >= CodeGenOpt::Aggressive;
174 //FIXME: This logic for reseting the subtarget along with
175 // the helper classes can probably be simplified but there are a lot of
176 // cases so we will defer rewriting this to later.
178 void MipsSubtarget::resetSubtarget(MachineFunction *MF) {
179 bool ChangeToMips16 = false, ChangeToNoMips16 = false;
180 DEBUG(dbgs() << "resetSubtargetFeatures" << "\n");
181 AttributeSet FnAttrs = MF->getFunction()->getAttributes();
182 ChangeToMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
184 ChangeToNoMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
186 assert (!(ChangeToMips16 & ChangeToNoMips16) &&
187 "mips16 and nomips16 specified on the same function");
188 if (ChangeToMips16) {
189 if (PreviousInMips16Mode)
191 OverrideMode = Mips16Override;
192 PreviousInMips16Mode = true;
193 TM->setHelperClassesMips16();
195 } else if (ChangeToNoMips16) {
196 if (!PreviousInMips16Mode)
198 OverrideMode = NoMips16Override;
199 PreviousInMips16Mode = false;
200 TM->setHelperClassesMipsSE();
203 if (OverrideMode == NoOverride)
205 OverrideMode = NoOverride;
206 DEBUG(dbgs() << "back to default" << "\n");
207 if (inMips16Mode() && !PreviousInMips16Mode) {
208 TM->setHelperClassesMips16();
209 PreviousInMips16Mode = true;
210 } else if (!inMips16Mode() && PreviousInMips16Mode) {
211 TM->setHelperClassesMipsSE();
212 PreviousInMips16Mode = false;
218 bool MipsSubtarget::mipsSEUsesSoftFloat() const {
219 return TM->Options.UseSoftFloat && !InMips16HardFloat;
222 bool MipsSubtarget::useConstantIslands() {
223 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
224 return Mips16ConstantIslands;