1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSSUBTARGET_H
15 #define MIPSSUBTARGET_H
17 #include "MCTargetDesc/MipsReginfo.h"
18 #include "llvm/MC/MCInstrItineraries.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Target/TargetSubtargetInfo.h"
23 #define GET_SUBTARGETINFO_HEADER
24 #include "MipsGenSubtargetInfo.inc"
29 class MipsTargetMachine;
31 class MipsSubtarget : public MipsGenSubtargetInfo {
32 virtual void anchor();
35 // NOTE: O64 will not be supported.
37 UnknownABI, O32, N32, N64, EABI
43 Mips32, Mips32r2, Mips64, Mips64r2
46 // Mips architecture version
47 MipsArchEnum MipsArchVersion;
49 // Mips supported ABIs
52 // IsLittle - The target is Little Endian
55 // IsSingleFloat - The target only supports single precision float
56 // point operations. This enable the target to use all 32 32-bit
57 // floating point registers instead of only using even ones.
60 // IsFP64bit - The target processor has 64-bit floating point registers.
63 // IsFP64bit - General-purpose registers are 64 bits wide
66 // HasVFPU - Processor has a vector floating point unit.
69 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
72 // UseSmallSection - Small section is used.
75 /// Features related to the presence of specific instructions.
77 // HasSEInReg - SEB and SEH (signext in register) instructions.
80 // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
83 // HasSwap - Byte and half swap instructions.
86 // HasBitCount - Count leading '1' and '0' bits.
89 // HasFPIdx -- Floating point indexed load/store instructions.
92 // InMips16 -- can process Mips16 instructions
96 bool InMips16HardFloat;
98 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
99 bool PreviousInMips16Mode;
101 // InMicroMips -- can process MicroMips instructions
102 bool InMicroMipsMode;
104 // HasDSP, HasDSPR2 -- supports DSP ASE.
105 bool HasDSP, HasDSPR2;
107 // Allow mixed Mips16 and Mips32 in one source file
108 bool AllowMixed16_32;
110 // Optimize for space by compiling all functions as Mips 16 unless
111 // it needs floating point. Functions needing floating point are
112 // compiled as Mips32
115 // HasMSA -- supports MSA ASE.
118 InstrItineraryData InstrItins;
120 // The instance to the register info section object
126 // We can override the determination of whether we are in mips16 mode
127 // as from the command line
128 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
130 MipsTargetMachine *TM;
133 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
134 AntiDepBreakMode& Mode,
135 RegClassVector& CriticalPathRCs) const;
137 /// Only O32 and EABI supported right now.
138 bool isABI_EABI() const { return MipsABI == EABI; }
139 bool isABI_N64() const { return MipsABI == N64; }
140 bool isABI_N32() const { return MipsABI == N32; }
141 bool isABI_O32() const { return MipsABI == O32; }
142 unsigned getTargetABI() const { return MipsABI; }
144 /// This constructor initializes the data members to match that
145 /// of the specified triple.
146 MipsSubtarget(const std::string &TT, const std::string &CPU,
147 const std::string &FS, bool little, Reloc::Model RM,
148 MipsTargetMachine *TM);
150 /// ParseSubtargetFeatures - Parses features string setting specified
151 /// subtarget options. Definition of function is auto generated by tblgen.
152 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
154 bool hasMips32() const { return MipsArchVersion >= Mips32; }
155 bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
156 MipsArchVersion == Mips64r2; }
157 bool hasMips64() const { return MipsArchVersion >= Mips64; }
158 bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
160 bool isLittle() const { return IsLittle; }
161 bool isFP64bit() const { return IsFP64bit; }
162 bool isNotFP64bit() const { return !IsFP64bit; }
163 bool isGP64bit() const { return IsGP64bit; }
164 bool isGP32bit() const { return !IsGP64bit; }
165 bool isSingleFloat() const { return IsSingleFloat; }
166 bool isNotSingleFloat() const { return !IsSingleFloat; }
167 bool hasVFPU() const { return HasVFPU; }
168 bool inMips16Mode() const {
169 switch (OverrideMode) {
174 case NoMips16Override:
177 llvm_unreachable("Unexpected mode");
179 bool inMips16ModeDefault() const {
182 bool inMips16HardFloat() const {
183 return inMips16Mode() && InMips16HardFloat;
185 bool inMicroMipsMode() const { return InMicroMipsMode; }
186 bool hasDSP() const { return HasDSP; }
187 bool hasDSPR2() const { return HasDSPR2; }
188 bool hasMSA() const { return HasMSA; }
189 bool isLinux() const { return IsLinux; }
190 bool useSmallSection() const { return UseSmallSection; }
192 bool hasStandardEncoding() const { return !inMips16Mode(); }
194 bool mipsSEUsesSoftFloat() const;
196 bool enableLongBranchPass() const {
197 return hasStandardEncoding() || allowMixed16_32();
200 /// Features related to the presence of specific instructions.
201 bool hasSEInReg() const { return HasSEInReg; }
202 bool hasCondMov() const { return HasCondMov; }
203 bool hasSwap() const { return HasSwap; }
204 bool hasBitCount() const { return HasBitCount; }
205 bool hasFPIdx() const { return HasFPIdx; }
206 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
208 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
209 bool allowMixed16_32() const { return inMips16ModeDefault() |
212 bool os16() const { return Os16;};
214 // for now constant islands are on for the whole compilation unit but we only
215 // really use them if in addition we are in mips16 mode
217 static bool useConstantIslands();
219 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
221 // Grab MipsRegInfo object
222 const MipsReginfo &getMReginfo() const { return MRI; }
224 // Grab relocation model
225 Reloc::Model getRelocationModel() const {return RM;}
227 /// \brief Reset the subtarget for the Mips target.
228 void resetSubtarget(MachineFunction *MF);
232 } // End llvm namespace