1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSSUBTARGET_H
15 #define MIPSSUBTARGET_H
17 #include "MipsFrameLowering.h"
18 #include "MipsISelLowering.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsJITInfo.h"
21 #include "MipsSelectionDAGInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc"
34 class MipsTargetMachine;
36 class MipsSubtarget : public MipsGenSubtargetInfo {
37 virtual void anchor();
40 // NOTE: O64 will not be supported.
42 UnknownABI, O32, N32, N64, EABI
47 Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
51 // Mips architecture version
52 MipsArchEnum MipsArchVersion;
54 // Mips supported ABIs
57 // IsLittle - The target is Little Endian
60 // IsSingleFloat - The target only supports single precision float
61 // point operations. This enable the target to use all 32 32-bit
62 // floating point registers instead of only using even ones.
65 // IsFPXX - MIPS O32 modeless ABI.
68 // IsFP64bit - The target processor has 64-bit floating point registers.
71 /// Are odd single-precision registers permitted?
72 /// This corresponds to -modd-spreg and -mno-odd-spreg
75 // IsNan2008 - IEEE 754-2008 NaN encoding.
78 // IsFP64bit - General-purpose registers are 64 bits wide
81 // HasVFPU - Processor has a vector floating point unit.
84 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
87 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
90 // UseSmallSection - Small section is used.
93 /// Features related to the presence of specific instructions.
95 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
98 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
101 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
104 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
107 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
110 // InMips16 -- can process Mips16 instructions
114 bool InMips16HardFloat;
116 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
117 bool PreviousInMips16Mode;
119 // InMicroMips -- can process MicroMips instructions
120 bool InMicroMipsMode;
122 // HasDSP, HasDSPR2 -- supports DSP ASE.
123 bool HasDSP, HasDSPR2;
125 // Allow mixed Mips16 and Mips32 in one source file
126 bool AllowMixed16_32;
128 // Optimize for space by compiling all functions as Mips 16 unless
129 // it needs floating point. Functions needing floating point are
130 // compiled as Mips32
133 // HasMSA -- supports MSA ASE.
136 InstrItineraryData InstrItins;
141 // We can override the determination of whether we are in mips16 mode
142 // as from the command line
143 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
145 MipsTargetMachine *TM;
149 const DataLayout DL; // Calculates type size & alignment
150 const MipsSelectionDAGInfo TSInfo;
152 std::unique_ptr<const MipsInstrInfo> InstrInfo;
153 std::unique_ptr<const MipsFrameLowering> FrameLowering;
154 std::unique_ptr<const MipsTargetLowering> TLInfo;
155 std::unique_ptr<const MipsInstrInfo> InstrInfo16;
156 std::unique_ptr<const MipsFrameLowering> FrameLowering16;
157 std::unique_ptr<const MipsTargetLowering> TLInfo16;
158 std::unique_ptr<const MipsInstrInfo> InstrInfoSE;
159 std::unique_ptr<const MipsFrameLowering> FrameLoweringSE;
160 std::unique_ptr<const MipsTargetLowering> TLInfoSE;
163 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
164 bool enablePostMachineScheduler() const override;
165 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
166 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
168 /// Only O32 and EABI supported right now.
169 bool isABI_EABI() const { return MipsABI == EABI; }
170 bool isABI_N64() const { return MipsABI == N64; }
171 bool isABI_N32() const { return MipsABI == N32; }
172 bool isABI_O32() const { return MipsABI == O32; }
173 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
174 unsigned getTargetABI() const { return MipsABI; }
176 /// This constructor initializes the data members to match that
177 /// of the specified triple.
178 MipsSubtarget(const std::string &TT, const std::string &CPU,
179 const std::string &FS, bool little, Reloc::Model RM,
180 MipsTargetMachine *TM);
182 /// ParseSubtargetFeatures - Parses features string setting specified
183 /// subtarget options. Definition of function is auto generated by tblgen.
184 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
186 bool hasMips1() const { return MipsArchVersion >= Mips1; }
187 bool hasMips2() const { return MipsArchVersion >= Mips2; }
188 bool hasMips3() const { return MipsArchVersion >= Mips3; }
189 bool hasMips4() const { return MipsArchVersion >= Mips4; }
190 bool hasMips5() const { return MipsArchVersion >= Mips5; }
191 bool hasMips4_32() const { return HasMips4_32; }
192 bool hasMips4_32r2() const { return HasMips4_32r2; }
193 bool hasMips32() const {
194 return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 &&
195 MipsArchVersion != Mips4 && MipsArchVersion != Mips5;
197 bool hasMips32r2() const {
198 return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 ||
199 MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
201 bool hasMips32r6() const {
202 return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6;
204 bool hasMips64() const { return MipsArchVersion >= Mips64; }
205 bool hasMips64r2() const {
206 return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
208 bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
210 bool hasCnMips() const { return HasCnMips; }
212 bool isLittle() const { return IsLittle; }
213 bool isFPXX() const { return IsFPXX; }
214 bool isFP64bit() const { return IsFP64bit; }
215 bool useOddSPReg() const { return UseOddSPReg; }
216 bool isNaN2008() const { return IsNaN2008bit; }
217 bool isNotFP64bit() const { return !IsFP64bit; }
218 bool isGP64bit() const { return IsGP64bit; }
219 bool isGP32bit() const { return !IsGP64bit; }
220 bool isSingleFloat() const { return IsSingleFloat; }
221 bool isNotSingleFloat() const { return !IsSingleFloat; }
222 bool hasVFPU() const { return HasVFPU; }
223 bool inMips16Mode() const {
224 switch (OverrideMode) {
229 case NoMips16Override:
232 llvm_unreachable("Unexpected mode");
234 bool inMips16ModeDefault() const {
237 bool inMips16HardFloat() const {
238 return inMips16Mode() && InMips16HardFloat;
240 bool inMicroMipsMode() const { return InMicroMipsMode; }
241 bool hasDSP() const { return HasDSP; }
242 bool hasDSPR2() const { return HasDSPR2; }
243 bool hasMSA() const { return HasMSA; }
244 bool isLinux() const { return IsLinux; }
245 bool useSmallSection() const { return UseSmallSection; }
247 bool hasStandardEncoding() const { return !inMips16Mode(); }
249 bool mipsSEUsesSoftFloat() const;
251 bool enableLongBranchPass() const {
252 return hasStandardEncoding() || allowMixed16_32();
255 /// Features related to the presence of specific instructions.
256 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
257 bool hasMTHC1() const { return hasMips32r2(); }
259 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
260 bool allowMixed16_32() const { return inMips16ModeDefault() |
263 bool os16() const { return Os16;};
265 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
266 bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); }
268 // for now constant islands are on for the whole compilation unit but we only
269 // really use them if in addition we are in mips16 mode
270 static bool useConstantIslands();
272 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
274 // Grab relocation model
275 Reloc::Model getRelocationModel() const {return RM;}
277 /// \brief Reset the subtarget for the Mips target.
278 void resetSubtarget(MachineFunction *MF);
280 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
281 const TargetMachine *TM);
283 /// Does the system support unaligned memory access.
285 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
286 /// specify which component of the system provides it. Hardware, software, and
287 /// hybrid implementations are all valid.
288 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
290 // Set helper classes
291 void setHelperClassesMips16();
292 void setHelperClassesMipsSE();
294 MipsJITInfo *getJITInfo() { return &JITInfo; }
295 const MipsSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
296 const DataLayout *getDataLayout() const { return &DL; }
297 const MipsInstrInfo *getInstrInfo() const { return InstrInfo.get(); }
298 const TargetFrameLowering *getFrameLowering() const {
299 return FrameLowering.get();
301 const MipsRegisterInfo *getRegisterInfo() const {
302 return &InstrInfo->getRegisterInfo();
304 const MipsTargetLowering *getTargetLowering() const { return TLInfo.get(); }
306 } // End llvm namespace