1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
17 #include "MipsFrameLowering.h"
18 #include "MipsISelLowering.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsSelectionDAGInfo.h"
21 #include "llvm/IR/DataLayout.h"
22 #include "llvm/MC/MCInstrItineraries.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
25 #include "MCTargetDesc/MipsABIInfo.h"
28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc"
34 class MipsTargetMachine;
36 class MipsSubtarget : public MipsGenSubtargetInfo {
37 virtual void anchor();
41 Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
45 // Mips architecture version
46 MipsArchEnum MipsArchVersion;
51 // IsLittle - The target is Little Endian
54 // IsSingleFloat - The target only supports single precision float
55 // point operations. This enable the target to use all 32 32-bit
56 // floating point registers instead of only using even ones.
59 // IsFPXX - MIPS O32 modeless ABI.
62 // NoABICalls - Disable SVR4-style position-independent code.
65 // IsFP64bit - The target processor has 64-bit floating point registers.
68 /// Are odd single-precision registers permitted?
69 /// This corresponds to -modd-spreg and -mno-odd-spreg
72 // IsNan2008 - IEEE 754-2008 NaN encoding.
75 // IsFP64bit - General-purpose registers are 64 bits wide
78 // HasVFPU - Processor has a vector floating point unit.
81 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
84 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
87 // UseSmallSection - Small section is used.
90 /// Features related to the presence of specific instructions.
92 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
95 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
98 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
101 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
104 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
107 // InMips16 -- can process Mips16 instructions
111 bool InMips16HardFloat;
113 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
114 bool PreviousInMips16Mode;
116 // InMicroMips -- can process MicroMips instructions
117 bool InMicroMipsMode;
119 // HasDSP, HasDSPR2 -- supports DSP ASE.
120 bool HasDSP, HasDSPR2;
122 // Allow mixed Mips16 and Mips32 in one source file
123 bool AllowMixed16_32;
125 // Optimize for space by compiling all functions as Mips 16 unless
126 // it needs floating point. Functions needing floating point are
127 // compiled as Mips32
130 // HasMSA -- supports MSA ASE.
133 InstrItineraryData InstrItins;
135 // We can override the determination of whether we are in mips16 mode
136 // as from the command line
137 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
139 const MipsTargetMachine &TM;
143 const DataLayout DL; // Calculates type size & alignment
144 const MipsSelectionDAGInfo TSInfo;
145 std::unique_ptr<const MipsInstrInfo> InstrInfo;
146 std::unique_ptr<const MipsFrameLowering> FrameLowering;
147 std::unique_ptr<const MipsTargetLowering> TLInfo;
150 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
151 bool enablePostMachineScheduler() const override;
152 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
153 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
155 /// Only O32 and EABI supported right now.
156 bool isABI_EABI() const { return ABI.IsEABI(); }
157 bool isABI_N64() const { return ABI.IsN64(); }
158 bool isABI_N32() const { return ABI.IsN32(); }
159 bool isABI_O32() const { return ABI.IsO32(); }
160 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
161 const MipsABIInfo &getABI() const { return ABI; }
163 /// This constructor initializes the data members to match that
164 /// of the specified triple.
165 MipsSubtarget(const std::string &TT, const std::string &CPU,
166 const std::string &FS, bool little,
167 const MipsTargetMachine &TM);
169 /// ParseSubtargetFeatures - Parses features string setting specified
170 /// subtarget options. Definition of function is auto generated by tblgen.
171 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
173 bool hasMips1() const { return MipsArchVersion >= Mips1; }
174 bool hasMips2() const { return MipsArchVersion >= Mips2; }
175 bool hasMips3() const { return MipsArchVersion >= Mips3; }
176 bool hasMips4() const { return MipsArchVersion >= Mips4; }
177 bool hasMips5() const { return MipsArchVersion >= Mips5; }
178 bool hasMips4_32() const { return HasMips4_32; }
179 bool hasMips4_32r2() const { return HasMips4_32r2; }
180 bool hasMips32() const {
181 return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 &&
182 MipsArchVersion != Mips4 && MipsArchVersion != Mips5;
184 bool hasMips32r2() const {
185 return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 ||
186 MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
188 bool hasMips32r6() const {
189 return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6;
191 bool hasMips64() const { return MipsArchVersion >= Mips64; }
192 bool hasMips64r2() const {
193 return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
195 bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
197 bool hasCnMips() const { return HasCnMips; }
199 bool isLittle() const { return IsLittle; }
200 bool isABICalls() const { return !NoABICalls; }
201 bool isFPXX() const { return IsFPXX; }
202 bool isFP64bit() const { return IsFP64bit; }
203 bool useOddSPReg() const { return UseOddSPReg; }
204 bool noOddSPReg() const { return !UseOddSPReg; }
205 bool isNaN2008() const { return IsNaN2008bit; }
206 bool isGP64bit() const { return IsGP64bit; }
207 bool isGP32bit() const { return !IsGP64bit; }
208 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
209 bool isSingleFloat() const { return IsSingleFloat; }
210 bool hasVFPU() const { return HasVFPU; }
211 bool inMips16Mode() const { return InMips16Mode; }
212 bool inMips16ModeDefault() const {
215 // Hard float for mips16 means essentially to compile as soft float
216 // but to use a runtime library for soft float that is written with
217 // native mips32 floating point instructions (those runtime routines
218 // run in mips32 hard float mode).
219 bool inMips16HardFloat() const {
220 return inMips16Mode() && InMips16HardFloat;
222 bool inMicroMipsMode() const { return InMicroMipsMode; }
223 bool hasDSP() const { return HasDSP; }
224 bool hasDSPR2() const { return HasDSPR2; }
225 bool hasMSA() const { return HasMSA; }
226 bool useSmallSection() const { return UseSmallSection; }
228 bool hasStandardEncoding() const { return !inMips16Mode(); }
230 bool abiUsesSoftFloat() const;
232 bool enableLongBranchPass() const {
233 return hasStandardEncoding() || allowMixed16_32();
236 /// Features related to the presence of specific instructions.
237 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
238 bool hasMTHC1() const { return hasMips32r2(); }
240 bool allowMixed16_32() const { return inMips16ModeDefault() |
243 bool os16() const { return Os16;};
245 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
247 // for now constant islands are on for the whole compilation unit but we only
248 // really use them if in addition we are in mips16 mode
249 static bool useConstantIslands();
251 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
253 // Grab relocation model
254 Reloc::Model getRelocationModel() const;
256 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
257 const TargetMachine &TM);
259 /// Does the system support unaligned memory access.
261 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
262 /// specify which component of the system provides it. Hardware, software, and
263 /// hybrid implementations are all valid.
264 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
266 // Set helper classes
267 void setHelperClassesMips16();
268 void setHelperClassesMipsSE();
270 const MipsSelectionDAGInfo *getSelectionDAGInfo() const override {
273 const DataLayout *getDataLayout() const override { return &DL; }
274 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
275 const TargetFrameLowering *getFrameLowering() const override {
276 return FrameLowering.get();
278 const MipsRegisterInfo *getRegisterInfo() const override {
279 return &InstrInfo->getRegisterInfo();
281 const MipsTargetLowering *getTargetLowering() const override {
284 const InstrItineraryData *getInstrItineraryData() const override {
288 } // End llvm namespace