1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSSUBTARGET_H
15 #define MIPSSUBTARGET_H
17 #include "llvm/Target/TargetSubtargetInfo.h"
18 #include "llvm/MC/MCInstrItineraries.h"
21 #define GET_SUBTARGETINFO_HEADER
22 #include "MipsGenSubtargetInfo.inc"
27 class MipsSubtarget : public MipsGenSubtargetInfo {
28 virtual void anchor();
31 // NOTE: O64 will not be supported.
33 UnknownABI, O32, N32, N64, EABI
39 Mips32, Mips32r2, Mips64, Mips64r2
42 // Mips architecture version
43 MipsArchEnum MipsArchVersion;
45 // Mips supported ABIs
48 // IsLittle - The target is Little Endian
51 // IsSingleFloat - The target only supports single precision float
52 // point operations. This enable the target to use all 32 32-bit
53 // floating point registers instead of only using even ones.
56 // IsFP64bit - The target processor has 64-bit floating point registers.
59 // IsFP64bit - General-purpose registers are 64 bits wide
62 // HasVFPU - Processor has a vector floating point unit.
65 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
68 // UseSmallSection - Small section is used.
71 /// Features related to the presence of specific instructions.
73 // HasSEInReg - SEB and SEH (signext in register) instructions.
76 // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
79 // HasMulDivAdd - Multiply add and sub (MADD, MADDu, MSUB, MSUBu)
83 // HasMinMax - MIN and MAX instructions.
86 // HasSwap - Byte and half swap instructions.
89 // HasBitCount - Count leading '1' and '0' bits.
92 // HasFPIdx -- Floating point indexed load/store instructions.
95 // InMips16 -- can process Mips16 instructions
98 // HasDSP, HasDSPR2 -- supports DSP ASE.
99 bool HasDSP, HasDSPR2;
101 // IsAndroid -- target is android
104 InstrItineraryData InstrItins;
107 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
108 AntiDepBreakMode& Mode,
109 RegClassVector& CriticalPathRCs) const;
111 /// Only O32 and EABI supported right now.
112 bool isABI_EABI() const { return MipsABI == EABI; }
113 bool isABI_N64() const { return MipsABI == N64; }
114 bool isABI_N32() const { return MipsABI == N32; }
115 bool isABI_O32() const { return MipsABI == O32; }
116 unsigned getTargetABI() const { return MipsABI; }
118 /// This constructor initializes the data members to match that
119 /// of the specified triple.
120 MipsSubtarget(const std::string &TT, const std::string &CPU,
121 const std::string &FS, bool little, Reloc::Model RM);
123 /// ParseSubtargetFeatures - Parses features string setting specified
124 /// subtarget options. Definition of function is auto generated by tblgen.
125 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
127 bool hasMips32() const { return MipsArchVersion >= Mips32; }
128 bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
129 MipsArchVersion == Mips64r2; }
130 bool hasMips64() const { return MipsArchVersion >= Mips64; }
131 bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
133 bool isLittle() const { return IsLittle; }
134 bool isFP64bit() const { return IsFP64bit; }
135 bool isGP64bit() const { return IsGP64bit; }
136 bool isGP32bit() const { return !IsGP64bit; }
137 bool isSingleFloat() const { return IsSingleFloat; }
138 bool isNotSingleFloat() const { return !IsSingleFloat; }
139 bool hasVFPU() const { return HasVFPU; }
140 bool inMips16Mode() const { return InMips16Mode; }
141 bool hasDSP() const { return HasDSP; }
142 bool hasDSPR2() const { return HasDSPR2; }
143 bool isAndroid() const { return IsAndroid; }
144 bool isLinux() const { return IsLinux; }
145 bool useSmallSection() const { return UseSmallSection; }
147 bool hasStandardEncoding() const { return !inMips16Mode(); }
149 /// Features related to the presence of specific instructions.
150 bool hasSEInReg() const { return HasSEInReg; }
151 bool hasCondMov() const { return HasCondMov; }
152 bool hasMulDivAdd() const { return HasMulDivAdd; }
153 bool hasMinMax() const { return HasMinMax; }
154 bool hasSwap() const { return HasSwap; }
155 bool hasBitCount() const { return HasBitCount; }
156 bool hasFPIdx() const { return HasFPIdx; }
158 } // End llvm namespace