1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSSUBTARGET_H
15 #define MIPSSUBTARGET_H
17 #include "MipsFrameLowering.h"
18 #include "MipsISelLowering.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsSelectionDAGInfo.h"
21 #include "llvm/IR/DataLayout.h"
22 #include "llvm/MC/MCInstrItineraries.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "MipsGenSubtargetInfo.inc"
33 class MipsTargetMachine;
35 class MipsSubtarget : public MipsGenSubtargetInfo {
36 virtual void anchor();
39 // NOTE: O64 will not be supported.
41 UnknownABI, O32, N32, N64, EABI
46 Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64,
50 // Mips architecture version
51 MipsArchEnum MipsArchVersion;
53 // Mips supported ABIs
56 // IsLittle - The target is Little Endian
59 // IsSingleFloat - The target only supports single precision float
60 // point operations. This enable the target to use all 32 32-bit
61 // floating point registers instead of only using even ones.
64 // IsFPXX - MIPS O32 modeless ABI.
67 // IsFP64bit - The target processor has 64-bit floating point registers.
70 /// Are odd single-precision registers permitted?
71 /// This corresponds to -modd-spreg and -mno-odd-spreg
74 // IsNan2008 - IEEE 754-2008 NaN encoding.
77 // IsFP64bit - General-purpose registers are 64 bits wide
80 // HasVFPU - Processor has a vector floating point unit.
83 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
86 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
89 // UseSmallSection - Small section is used.
92 /// Features related to the presence of specific instructions.
94 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
97 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
100 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
103 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
106 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
109 // InMips16 -- can process Mips16 instructions
113 bool InMips16HardFloat;
115 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
116 bool PreviousInMips16Mode;
118 // InMicroMips -- can process MicroMips instructions
119 bool InMicroMipsMode;
121 // HasDSP, HasDSPR2 -- supports DSP ASE.
122 bool HasDSP, HasDSPR2;
124 // Allow mixed Mips16 and Mips32 in one source file
125 bool AllowMixed16_32;
127 // Optimize for space by compiling all functions as Mips 16 unless
128 // it needs floating point. Functions needing floating point are
129 // compiled as Mips32
132 // HasMSA -- supports MSA ASE.
135 InstrItineraryData InstrItins;
137 // We can override the determination of whether we are in mips16 mode
138 // as from the command line
139 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
141 MipsTargetMachine *TM;
145 const DataLayout DL; // Calculates type size & alignment
146 const MipsSelectionDAGInfo TSInfo;
147 std::unique_ptr<const MipsInstrInfo> InstrInfo;
148 std::unique_ptr<const MipsFrameLowering> FrameLowering;
149 std::unique_ptr<const MipsTargetLowering> TLInfo;
152 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
153 bool enablePostMachineScheduler() const override;
154 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
155 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override;
157 /// Only O32 and EABI supported right now.
158 bool isABI_EABI() const { return MipsABI == EABI; }
159 bool isABI_N64() const { return MipsABI == N64; }
160 bool isABI_N32() const { return MipsABI == N32; }
161 bool isABI_O32() const { return MipsABI == O32; }
162 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
163 unsigned getTargetABI() const { return MipsABI; }
165 /// This constructor initializes the data members to match that
166 /// of the specified triple.
167 MipsSubtarget(const std::string &TT, const std::string &CPU,
168 const std::string &FS, bool little, MipsTargetMachine *TM);
170 /// ParseSubtargetFeatures - Parses features string setting specified
171 /// subtarget options. Definition of function is auto generated by tblgen.
172 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
174 bool hasMips1() const { return MipsArchVersion >= Mips1; }
175 bool hasMips2() const { return MipsArchVersion >= Mips2; }
176 bool hasMips3() const { return MipsArchVersion >= Mips3; }
177 bool hasMips4() const { return MipsArchVersion >= Mips4; }
178 bool hasMips5() const { return MipsArchVersion >= Mips5; }
179 bool hasMips4_32() const { return HasMips4_32; }
180 bool hasMips4_32r2() const { return HasMips4_32r2; }
181 bool hasMips32() const {
182 return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 &&
183 MipsArchVersion != Mips4 && MipsArchVersion != Mips5;
185 bool hasMips32r2() const {
186 return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 ||
187 MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
189 bool hasMips32r6() const {
190 return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6;
192 bool hasMips64() const { return MipsArchVersion >= Mips64; }
193 bool hasMips64r2() const {
194 return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
196 bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
198 bool hasCnMips() const { return HasCnMips; }
200 bool isLittle() const { return IsLittle; }
201 bool isFPXX() const { return IsFPXX; }
202 bool isFP64bit() const { return IsFP64bit; }
203 bool useOddSPReg() const { return UseOddSPReg; }
204 bool noOddSPReg() const { return !UseOddSPReg; }
205 bool isNaN2008() const { return IsNaN2008bit; }
206 bool isNotFP64bit() const { return !IsFP64bit; }
207 bool isGP64bit() const { return IsGP64bit; }
208 bool isGP32bit() const { return !IsGP64bit; }
209 bool isSingleFloat() const { return IsSingleFloat; }
210 bool isNotSingleFloat() const { return !IsSingleFloat; }
211 bool hasVFPU() const { return HasVFPU; }
212 bool inMips16Mode() const { return InMips16Mode; }
213 bool inMips16ModeDefault() const {
216 // Hard float for mips16 means essentially to compile as soft float
217 // but to use a runtime library for soft float that is written with
218 // native mips32 floating point instructions (those runtime routines
219 // run in mips32 hard float mode).
220 bool inMips16HardFloat() const {
221 return inMips16Mode() && InMips16HardFloat;
223 bool inMicroMipsMode() const { return InMicroMipsMode; }
224 bool hasDSP() const { return HasDSP; }
225 bool hasDSPR2() const { return HasDSPR2; }
226 bool hasMSA() const { return HasMSA; }
227 bool isLinux() const { return IsLinux; }
228 bool useSmallSection() const { return UseSmallSection; }
230 bool hasStandardEncoding() const { return !inMips16Mode(); }
232 bool abiUsesSoftFloat() const;
234 bool enableLongBranchPass() const {
235 return hasStandardEncoding() || allowMixed16_32();
238 /// Features related to the presence of specific instructions.
239 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
240 bool hasMTHC1() const { return hasMips32r2(); }
242 bool allowMixed16_32() const { return inMips16ModeDefault() |
245 bool os16() const { return Os16;};
247 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
248 bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); }
250 // for now constant islands are on for the whole compilation unit but we only
251 // really use them if in addition we are in mips16 mode
252 static bool useConstantIslands();
254 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
256 // Grab relocation model
257 Reloc::Model getRelocationModel() const;
259 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
260 const TargetMachine *TM);
262 /// Does the system support unaligned memory access.
264 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
265 /// specify which component of the system provides it. Hardware, software, and
266 /// hybrid implementations are all valid.
267 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
269 // Set helper classes
270 void setHelperClassesMips16();
271 void setHelperClassesMipsSE();
273 const MipsSelectionDAGInfo *getSelectionDAGInfo() const override {
276 const DataLayout *getDataLayout() const override { return &DL; }
277 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
278 const TargetFrameLowering *getFrameLowering() const override {
279 return FrameLowering.get();
281 const MipsRegisterInfo *getRegisterInfo() const override {
282 return &InstrInfo->getRegisterInfo();
284 const MipsTargetLowering *getTargetLowering() const override {
287 const InstrItineraryData *getInstrItineraryData() const override {
291 } // End llvm namespace