1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Mips target spec.
12 //===----------------------------------------------------------------------===//
14 #include "MipsTargetMachine.h"
16 #include "Mips16FrameLowering.h"
17 #include "Mips16HardFloat.h"
18 #include "Mips16ISelDAGToDAG.h"
19 #include "Mips16ISelLowering.h"
20 #include "Mips16InstrInfo.h"
21 #include "MipsFrameLowering.h"
22 #include "MipsInstrInfo.h"
23 #include "MipsModuleISelDAGToDAG.h"
25 #include "MipsSEFrameLowering.h"
26 #include "MipsSEISelDAGToDAG.h"
27 #include "MipsSEISelLowering.h"
28 #include "MipsSEInstrInfo.h"
29 #include "MipsTargetObjectFile.h"
30 #include "llvm/Analysis/TargetTransformInfo.h"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/PassManager.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/TargetRegistry.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Transforms/Scalar.h"
39 #define DEBUG_TYPE "mips"
41 extern "C" void LLVMInitializeMipsTarget() {
42 // Register the target.
43 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
44 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
45 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
46 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
49 static std::string computeDataLayout(bool isLittle, MipsABIInfo &ABI) {
52 // There are both little and big endian mips.
60 // Pointers are 32 bit on some ABIs.
64 // 8 and 16 bit integers only need no have natural alignment, but try to
65 // align them to 32 bits. 64 bit integers have natural alignment.
66 Ret += "-i8:8:32-i16:16:32-i64:64";
68 // 32 bit registers are always available and the stack is at least 64 bit
69 // aligned. On N64 64 bit registers are also available and the stack is
71 if (ABI.IsN64() || ABI.IsN32())
72 Ret += "-n32:64-S128";
79 // On function prologue, the stack is created by decrementing
80 // its pointer. Once decremented, all references are done with positive
81 // offset from the stack/frame pointer, using StackGrowsUp enables
82 // an easier handling.
83 // Using CodeModel::Large enables different CALL behavior.
84 MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
85 StringRef CPU, StringRef FS,
86 const TargetOptions &Options,
87 Reloc::Model RM, CodeModel::Model CM,
88 CodeGenOpt::Level OL, bool isLittle)
89 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
90 isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
91 ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)),
92 DL(computeDataLayout(isLittle, ABI)), Subtarget(nullptr),
93 DefaultSubtarget(TT, CPU, FS, isLittle, *this),
94 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
96 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
98 Subtarget = &DefaultSubtarget;
102 MipsTargetMachine::~MipsTargetMachine() {}
104 void MipsebTargetMachine::anchor() { }
106 MipsebTargetMachine::
107 MipsebTargetMachine(const Target &T, StringRef TT,
108 StringRef CPU, StringRef FS, const TargetOptions &Options,
109 Reloc::Model RM, CodeModel::Model CM,
110 CodeGenOpt::Level OL)
111 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
113 void MipselTargetMachine::anchor() { }
115 MipselTargetMachine::
116 MipselTargetMachine(const Target &T, StringRef TT,
117 StringRef CPU, StringRef FS, const TargetOptions &Options,
118 Reloc::Model RM, CodeModel::Model CM,
119 CodeGenOpt::Level OL)
120 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
122 const MipsSubtarget *
123 MipsTargetMachine::getSubtargetImpl(const Function &F) const {
124 AttributeSet FnAttrs = F.getAttributes();
126 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
128 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
130 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
131 ? CPUAttr.getValueAsString().str()
133 std::string FS = !FSAttr.hasAttribute(Attribute::None)
134 ? FSAttr.getValueAsString().str()
137 !FnAttrs.getAttribute(AttributeSet::FunctionIndex, "mips16")
138 .hasAttribute(Attribute::None);
139 bool hasNoMips16Attr =
140 !FnAttrs.getAttribute(AttributeSet::FunctionIndex, "nomips16")
141 .hasAttribute(Attribute::None);
143 // FIXME: This is related to the code below to reset the target options,
144 // we need to know whether or not the soft float flag is set on the
145 // function before we can generate a subtarget. We also need to use
146 // it as a key for the subtarget since that can be the only difference
147 // between two functions.
149 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "use-soft-float");
150 bool softFloat = !SFAttr.hasAttribute(Attribute::None)
151 ? SFAttr.getValueAsString() == "true"
152 : Options.UseSoftFloat;
155 FS += FS.empty() ? "+mips16" : ",+mips16";
156 else if (hasNoMips16Attr)
157 FS += FS.empty() ? "-mips16" : ",-mips16";
159 auto &I = SubtargetMap[CPU + FS + (softFloat ? "use-soft-float=true"
160 : "use-soft-float=false")];
162 // This needs to be done before we create a new subtarget since any
163 // creation will depend on the TM and the code generation flags on the
164 // function that reside in TargetOptions.
165 resetTargetOptions(F);
166 I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, *this);
171 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
172 DEBUG(dbgs() << "resetSubtarget\n");
174 Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction()));
175 MF->setSubtarget(Subtarget);
180 /// Mips Code Generator Pass Configuration Options.
181 class MipsPassConfig : public TargetPassConfig {
183 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
184 : TargetPassConfig(TM, PM) {
185 // The current implementation of long branch pass requires a scratch
186 // register ($at) to be available before branch instructions. Tail merging
187 // can break this requirement, so disable it when long branch pass is
189 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
192 MipsTargetMachine &getMipsTargetMachine() const {
193 return getTM<MipsTargetMachine>();
196 const MipsSubtarget &getMipsSubtarget() const {
197 return *getMipsTargetMachine().getSubtargetImpl();
200 void addIRPasses() override;
201 bool addInstSelector() override;
202 void addMachineSSAOptimization() override;
203 void addPreEmitPass() override;
205 void addPreRegAlloc() override;
210 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
211 return new MipsPassConfig(this, PM);
214 void MipsPassConfig::addIRPasses() {
215 TargetPassConfig::addIRPasses();
216 addPass(createAtomicExpandPass(&getMipsTargetMachine()));
217 if (getMipsSubtarget().os16())
218 addPass(createMipsOs16(getMipsTargetMachine()));
219 if (getMipsSubtarget().inMips16HardFloat())
220 addPass(createMips16HardFloat(getMipsTargetMachine()));
222 // Install an instruction selector pass using
223 // the ISelDag to gen Mips code.
224 bool MipsPassConfig::addInstSelector() {
225 addPass(createMipsModuleISelDag(getMipsTargetMachine()));
226 addPass(createMips16ISelDag(getMipsTargetMachine()));
227 addPass(createMipsSEISelDag(getMipsTargetMachine()));
231 void MipsPassConfig::addMachineSSAOptimization() {
232 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
233 TargetPassConfig::addMachineSSAOptimization();
236 void MipsPassConfig::addPreRegAlloc() {
237 if (getOptLevel() == CodeGenOpt::None)
238 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
241 TargetIRAnalysis MipsTargetMachine::getTargetIRAnalysis() {
242 return TargetIRAnalysis([this](Function &F) {
243 if (Subtarget->allowMixed16_32()) {
244 DEBUG(errs() << "No Target Transform Info Pass Added\n");
245 // FIXME: This is no longer necessary as the TTI returned is per-function.
246 return TargetTransformInfo(getDataLayout());
249 DEBUG(errs() << "Target Transform Info Pass Added\n");
250 return TargetTransformInfo(BasicTTIImpl(this, F));
254 // Implemented by targets that want to run passes immediately before
255 // machine code is emitted. return true if -print-machineinstrs should
256 // print out the code after the passes.
257 void MipsPassConfig::addPreEmitPass() {
258 MipsTargetMachine &TM = getMipsTargetMachine();
259 addPass(createMipsDelaySlotFillerPass(TM));
260 addPass(createMipsLongBranchPass(TM));
261 addPass(createMipsConstantIslandPass(TM));