1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Mips target spec.
12 //===----------------------------------------------------------------------===//
15 #include "MipsTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Target/TargetRegistry.h"
20 extern "C" void LLVMInitializeMipsTarget() {
21 // Register the target.
22 RegisterTargetMachine<MipsTargetMachine> X(TheMipsTarget);
23 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
26 // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
27 // The stack is always 8 byte aligned
28 // On function prologue, the stack is created by decrementing
29 // its pointer. Once decremented, all references are done with positive
30 // offset from the stack/frame pointer, using StackGrowsUp enables
31 // an easier handling.
32 // Using CodeModel::Large enables different CALL behavior.
34 MipsTargetMachine(const Target &T, StringRef TT,
35 StringRef CPU, StringRef FS,
36 Reloc::Model RM, CodeModel::Model CM,
38 LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
39 Subtarget(TT, CPU, FS, isLittle),
41 std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
42 std::string("E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
44 FrameLowering(Subtarget),
45 TLInfo(*this), TSInfo(*this), JITInfo() {
49 MipselTargetMachine(const Target &T, StringRef TT,
50 StringRef CPU, StringRef FS,
51 Reloc::Model RM, CodeModel::Model CM) :
52 MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {}
54 // Install an instruction selector pass using
55 // the ISelDag to gen Mips code.
56 bool MipsTargetMachine::
57 addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
59 PM.add(createMipsISelDag(*this));
63 // Implemented by targets that want to run passes immediately before
64 // machine code is emitted. return true if -print-machineinstrs should
65 // print out the code after the passes.
66 bool MipsTargetMachine::
67 addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
69 PM.add(createMipsDelaySlotFillerPass(*this));
73 bool MipsTargetMachine::
74 addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
75 PM.add(createMipsEmitGPRestorePass(*this));
79 bool MipsTargetMachine::
80 addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) {
81 PM.add(createMipsExpandPseudoPass(*this));
85 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
86 CodeGenOpt::Level OptLevel,
87 JITCodeEmitter &JCE) {
88 // Machine code emitter pass for Mips.
89 PM.add(createMipsJITCodeEmitterPass(*this, JCE));