1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips --*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Mips target spec.
12 //===----------------------------------------------------------------------===//
15 #include "MipsTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/Support/TargetRegistry.h"
21 extern "C" void LLVMInitializeMipsTarget() {
22 // Register the target.
23 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
24 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
25 RegisterTargetMachine<Mips64ebTargetMachine> A(TheMips64Target);
26 RegisterTargetMachine<Mips64elTargetMachine> B(TheMips64elTarget);
29 // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
30 // The stack is always 8 byte aligned
31 // On function prologue, the stack is created by decrementing
32 // its pointer. Once decremented, all references are done with positive
33 // offset from the stack/frame pointer, using StackGrowsUp enables
34 // an easier handling.
35 // Using CodeModel::Large enables different CALL behavior.
37 MipsTargetMachine(const Target &T, StringRef TT,
38 StringRef CPU, StringRef FS, const TargetOptions &Options,
39 Reloc::Model RM, CodeModel::Model CM,
42 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
43 Subtarget(TT, CPU, FS, isLittle),
45 (Subtarget.isABI_N64() ?
46 "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
47 "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
48 (Subtarget.isABI_N64() ?
49 "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
50 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
52 FrameLowering(Subtarget),
53 TLInfo(*this), TSInfo(*this), JITInfo() {
56 void MipsebTargetMachine::anchor() { }
59 MipsebTargetMachine(const Target &T, StringRef TT,
60 StringRef CPU, StringRef FS, const TargetOptions &Options,
61 Reloc::Model RM, CodeModel::Model CM,
63 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
65 void MipselTargetMachine::anchor() { }
68 MipselTargetMachine(const Target &T, StringRef TT,
69 StringRef CPU, StringRef FS, const TargetOptions &Options,
70 Reloc::Model RM, CodeModel::Model CM,
72 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
74 void Mips64ebTargetMachine::anchor() { }
76 Mips64ebTargetMachine::
77 Mips64ebTargetMachine(const Target &T, StringRef TT,
78 StringRef CPU, StringRef FS, const TargetOptions &Options,
79 Reloc::Model RM, CodeModel::Model CM,
81 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
83 void Mips64elTargetMachine::anchor() { }
85 Mips64elTargetMachine::
86 Mips64elTargetMachine(const Target &T, StringRef TT,
87 StringRef CPU, StringRef FS, const TargetOptions &Options,
88 Reloc::Model RM, CodeModel::Model CM,
90 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
93 /// Mips Code Generator Pass Configuration Options.
94 class MipsPassConfig : public TargetPassConfig {
96 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
97 : TargetPassConfig(TM, PM) {}
99 MipsTargetMachine &getMipsTargetMachine() const {
100 return getTM<MipsTargetMachine>();
103 const MipsSubtarget &getMipsSubtarget() const {
104 return *getMipsTargetMachine().getSubtargetImpl();
107 virtual bool addInstSelector();
108 virtual bool addPreRegAlloc();
109 virtual bool addPostRegAlloc();
110 virtual bool addPreEmitPass();
114 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
115 return new MipsPassConfig(this, PM);
118 // Install an instruction selector pass using
119 // the ISelDag to gen Mips code.
120 bool MipsPassConfig::addInstSelector()
122 PM.add(createMipsISelDag(getMipsTargetMachine()));
126 // Implemented by targets that want to run passes immediately before
127 // machine code is emitted. return true if -print-machineinstrs should
128 // print out the code after the passes.
129 bool MipsPassConfig::addPreEmitPass()
131 PM.add(createMipsDelaySlotFillerPass(getMipsTargetMachine()));
135 bool MipsPassConfig::addPreRegAlloc() {
136 // Do not restore $gp if target is Mips64.
137 // In N32/64, $gp is a callee-saved register.
138 if (!getMipsSubtarget().hasMips64())
139 PM.add(createMipsEmitGPRestorePass(getMipsTargetMachine()));
143 bool MipsPassConfig::addPostRegAlloc() {
144 PM.add(createMipsExpandPseudoPass(getMipsTargetMachine()));
148 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
149 JITCodeEmitter &JCE) {
150 // Machine code emitter pass for Mips.
151 PM.add(createMipsJITCodeEmitterPass(*this, JCE));