1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Mips target spec.
12 //===----------------------------------------------------------------------===//
14 #include "MipsTargetMachine.h"
16 #include "Mips16FrameLowering.h"
17 #include "Mips16HardFloat.h"
18 #include "Mips16ISelDAGToDAG.h"
19 #include "Mips16ISelLowering.h"
20 #include "Mips16InstrInfo.h"
21 #include "MipsFrameLowering.h"
22 #include "MipsInstrInfo.h"
23 #include "MipsModuleISelDAGToDAG.h"
25 #include "MipsSEFrameLowering.h"
26 #include "MipsSEISelDAGToDAG.h"
27 #include "MipsSEISelLowering.h"
28 #include "MipsSEInstrInfo.h"
29 #include "llvm/Analysis/TargetTransformInfo.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/PassManager.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Transforms/Scalar.h"
40 extern "C" void LLVMInitializeMipsTarget() {
41 // Register the target.
42 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
43 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
44 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
45 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
48 static std::string computeDataLayout(const MipsSubtarget &ST) {
51 // There are both little and big endian mips.
59 // Pointers are 32 bit on some ABIs.
63 // 8 and 16 bit integers only need no have natural alignment, but try to
64 // align them to 32 bits. 64 bit integers have natural alignment.
65 Ret += "-i8:8:32-i16:16:32-i64:64";
67 // 32 bit registers are always available and the stack is at least 64 bit
68 // aligned. On N64 64 bit registers are also available and the stack is
70 if (ST.isABI_N64() || ST.isABI_N32())
71 Ret += "-n32:64-S128";
78 // On function prologue, the stack is created by decrementing
79 // its pointer. Once decremented, all references are done with positive
80 // offset from the stack/frame pointer, using StackGrowsUp enables
81 // an easier handling.
82 // Using CodeModel::Large enables different CALL behavior.
84 MipsTargetMachine(const Target &T, StringRef TT,
85 StringRef CPU, StringRef FS, const TargetOptions &Options,
86 Reloc::Model RM, CodeModel::Model CM,
89 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
90 Subtarget(TT, CPU, FS, isLittle, RM, this),
91 DL(computeDataLayout(Subtarget)),
92 InstrInfo(MipsInstrInfo::create(*this)),
93 FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
94 TLInfo(MipsTargetLowering::create(*this)), TSInfo(*this),
95 InstrItins(Subtarget.getInstrItineraryData()), JITInfo() {
100 void MipsTargetMachine::setHelperClassesMips16() {
101 InstrInfoSE.swap(InstrInfo);
102 FrameLoweringSE.swap(FrameLowering);
103 TLInfoSE.swap(TLInfo);
105 InstrInfo.reset(MipsInstrInfo::create(*this));
106 FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
107 TLInfo.reset(MipsTargetLowering::create(*this));
109 InstrInfo16.swap(InstrInfo);
110 FrameLowering16.swap(FrameLowering);
111 TLInfo16.swap(TLInfo);
113 assert(TLInfo && "null target lowering 16");
114 assert(InstrInfo && "null instr info 16");
115 assert(FrameLowering && "null frame lowering 16");
118 void MipsTargetMachine::setHelperClassesMipsSE() {
119 InstrInfo16.swap(InstrInfo);
120 FrameLowering16.swap(FrameLowering);
121 TLInfo16.swap(TLInfo);
123 InstrInfo.reset(MipsInstrInfo::create(*this));
124 FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
125 TLInfo.reset(MipsTargetLowering::create(*this));
127 InstrInfoSE.swap(InstrInfo);
128 FrameLoweringSE.swap(FrameLowering);
129 TLInfoSE.swap(TLInfo);
131 assert(TLInfo && "null target lowering in SE");
132 assert(InstrInfo && "null instr info SE");
133 assert(FrameLowering && "null frame lowering SE");
135 void MipsebTargetMachine::anchor() { }
137 MipsebTargetMachine::
138 MipsebTargetMachine(const Target &T, StringRef TT,
139 StringRef CPU, StringRef FS, const TargetOptions &Options,
140 Reloc::Model RM, CodeModel::Model CM,
141 CodeGenOpt::Level OL)
142 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
144 void MipselTargetMachine::anchor() { }
146 MipselTargetMachine::
147 MipselTargetMachine(const Target &T, StringRef TT,
148 StringRef CPU, StringRef FS, const TargetOptions &Options,
149 Reloc::Model RM, CodeModel::Model CM,
150 CodeGenOpt::Level OL)
151 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
154 /// Mips Code Generator Pass Configuration Options.
155 class MipsPassConfig : public TargetPassConfig {
157 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
158 : TargetPassConfig(TM, PM) {
159 // The current implementation of long branch pass requires a scratch
160 // register ($at) to be available before branch instructions. Tail merging
161 // can break this requirement, so disable it when long branch pass is
163 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
166 MipsTargetMachine &getMipsTargetMachine() const {
167 return getTM<MipsTargetMachine>();
170 const MipsSubtarget &getMipsSubtarget() const {
171 return *getMipsTargetMachine().getSubtargetImpl();
174 virtual void addIRPasses();
175 virtual bool addInstSelector();
176 virtual void addMachineSSAOptimization();
177 virtual bool addPreEmitPass();
179 virtual bool addPreRegAlloc();
184 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
185 return new MipsPassConfig(this, PM);
188 void MipsPassConfig::addIRPasses() {
189 TargetPassConfig::addIRPasses();
190 if (getMipsSubtarget().os16())
191 addPass(createMipsOs16(getMipsTargetMachine()));
192 if (getMipsSubtarget().inMips16HardFloat())
193 addPass(createMips16HardFloat(getMipsTargetMachine()));
194 addPass(createPartiallyInlineLibCallsPass());
196 // Install an instruction selector pass using
197 // the ISelDag to gen Mips code.
198 bool MipsPassConfig::addInstSelector() {
199 if (getMipsSubtarget().allowMixed16_32()) {
200 addPass(createMipsModuleISelDag(getMipsTargetMachine()));
201 addPass(createMips16ISelDag(getMipsTargetMachine()));
202 addPass(createMipsSEISelDag(getMipsTargetMachine()));
204 addPass(createMipsISelDag(getMipsTargetMachine()));
209 void MipsPassConfig::addMachineSSAOptimization() {
210 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
211 TargetPassConfig::addMachineSSAOptimization();
214 bool MipsPassConfig::addPreRegAlloc() {
215 if (getOptLevel() == CodeGenOpt::None) {
216 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
223 void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
224 if (Subtarget.allowMixed16_32()) {
225 DEBUG(errs() << "No ");
226 //FIXME: The Basic Target Transform Info
227 // pass needs to become a function pass instead of
228 // being an immutable pass and then this method as it exists now
229 // would be unnecessary.
230 PM.add(createNoTargetTransformInfoPass());
232 LLVMTargetMachine::addAnalysisPasses(PM);
233 DEBUG(errs() << "Target Transform Info Pass Added\n");
236 // Implemented by targets that want to run passes immediately before
237 // machine code is emitted. return true if -print-machineinstrs should
238 // print out the code after the passes.
239 bool MipsPassConfig::addPreEmitPass() {
240 MipsTargetMachine &TM = getMipsTargetMachine();
241 const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
242 addPass(createMipsDelaySlotFillerPass(TM));
244 if (Subtarget.enableLongBranchPass())
245 addPass(createMipsLongBranchPass(TM));
246 if (Subtarget.inMips16Mode() ||
247 Subtarget.allowMixed16_32())
248 addPass(createMipsConstantIslandPass(TM));
253 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
254 JITCodeEmitter &JCE) {
255 // Machine code emitter pass for Mips.
256 PM.add(createMipsJITCodeEmitterPass(*this, JCE));