1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Mips target spec.
12 //===----------------------------------------------------------------------===//
14 #include "MipsTargetMachine.h"
16 #include "Mips16FrameLowering.h"
17 #include "Mips16HardFloat.h"
18 #include "Mips16ISelDAGToDAG.h"
19 #include "Mips16ISelLowering.h"
20 #include "Mips16InstrInfo.h"
21 #include "MipsFrameLowering.h"
22 #include "MipsInstrInfo.h"
23 #include "MipsModuleISelDAGToDAG.h"
25 #include "MipsSEFrameLowering.h"
26 #include "MipsSEISelDAGToDAG.h"
27 #include "MipsSEISelLowering.h"
28 #include "MipsSEInstrInfo.h"
29 #include "MipsTargetObjectFile.h"
30 #include "llvm/Analysis/TargetTransformInfo.h"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/IR/LegacyPassManager.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/TargetRegistry.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Transforms/Scalar.h"
39 #define DEBUG_TYPE "mips"
41 extern "C" void LLVMInitializeMipsTarget() {
42 // Register the target.
43 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
44 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
45 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
46 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
49 static std::string computeDataLayout(StringRef TT, StringRef CPU,
50 const TargetOptions &Options,
54 MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions);
56 // There are both little and big endian mips.
64 // Pointers are 32 bit on some ABIs.
68 // 8 and 16 bit integers only need no have natural alignment, but try to
69 // align them to 32 bits. 64 bit integers have natural alignment.
70 Ret += "-i8:8:32-i16:16:32-i64:64";
72 // 32 bit registers are always available and the stack is at least 64 bit
73 // aligned. On N64 64 bit registers are also available and the stack is
75 if (ABI.IsN64() || ABI.IsN32())
76 Ret += "-n32:64-S128";
83 // On function prologue, the stack is created by decrementing
84 // its pointer. Once decremented, all references are done with positive
85 // offset from the stack/frame pointer, using StackGrowsUp enables
86 // an easier handling.
87 // Using CodeModel::Large enables different CALL behavior.
88 MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
89 StringRef CPU, StringRef FS,
90 const TargetOptions &Options,
91 Reloc::Model RM, CodeModel::Model CM,
92 CodeGenOpt::Level OL, bool isLittle)
93 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
94 CPU, FS, Options, RM, CM, OL),
95 isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
96 ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)),
97 Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
98 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
100 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
102 Subtarget = &DefaultSubtarget;
106 MipsTargetMachine::~MipsTargetMachine() {}
108 void MipsebTargetMachine::anchor() { }
110 MipsebTargetMachine::
111 MipsebTargetMachine(const Target &T, StringRef TT,
112 StringRef CPU, StringRef FS, const TargetOptions &Options,
113 Reloc::Model RM, CodeModel::Model CM,
114 CodeGenOpt::Level OL)
115 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
117 void MipselTargetMachine::anchor() { }
119 MipselTargetMachine::
120 MipselTargetMachine(const Target &T, StringRef TT,
121 StringRef CPU, StringRef FS, const TargetOptions &Options,
122 Reloc::Model RM, CodeModel::Model CM,
123 CodeGenOpt::Level OL)
124 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
126 const MipsSubtarget *
127 MipsTargetMachine::getSubtargetImpl(const Function &F) const {
128 Attribute CPUAttr = F.getFnAttribute("target-cpu");
129 Attribute FSAttr = F.getFnAttribute("target-features");
131 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
132 ? CPUAttr.getValueAsString().str()
134 std::string FS = !FSAttr.hasAttribute(Attribute::None)
135 ? FSAttr.getValueAsString().str()
138 !F.getFnAttribute("mips16").hasAttribute(Attribute::None);
139 bool hasNoMips16Attr =
140 !F.getFnAttribute("nomips16").hasAttribute(Attribute::None);
142 // FIXME: This is related to the code below to reset the target options,
143 // we need to know whether or not the soft float flag is set on the
144 // function before we can generate a subtarget. We also need to use
145 // it as a key for the subtarget since that can be the only difference
146 // between two functions.
147 Attribute SFAttr = F.getFnAttribute("use-soft-float");
148 bool softFloat = !SFAttr.hasAttribute(Attribute::None)
149 ? SFAttr.getValueAsString() == "true"
150 : Options.UseSoftFloat;
153 FS += FS.empty() ? "+mips16" : ",+mips16";
154 else if (hasNoMips16Attr)
155 FS += FS.empty() ? "-mips16" : ",-mips16";
157 auto &I = SubtargetMap[CPU + FS + (softFloat ? "use-soft-float=true"
158 : "use-soft-float=false")];
160 // This needs to be done before we create a new subtarget since any
161 // creation will depend on the TM and the code generation flags on the
162 // function that reside in TargetOptions.
163 resetTargetOptions(F);
164 I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, *this);
169 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
170 DEBUG(dbgs() << "resetSubtarget\n");
172 Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction()));
173 MF->setSubtarget(Subtarget);
178 /// Mips Code Generator Pass Configuration Options.
179 class MipsPassConfig : public TargetPassConfig {
181 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
182 : TargetPassConfig(TM, PM) {
183 // The current implementation of long branch pass requires a scratch
184 // register ($at) to be available before branch instructions. Tail merging
185 // can break this requirement, so disable it when long branch pass is
187 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
190 MipsTargetMachine &getMipsTargetMachine() const {
191 return getTM<MipsTargetMachine>();
194 const MipsSubtarget &getMipsSubtarget() const {
195 return *getMipsTargetMachine().getSubtargetImpl();
198 void addIRPasses() override;
199 bool addInstSelector() override;
200 void addMachineSSAOptimization() override;
201 void addPreEmitPass() override;
203 void addPreRegAlloc() override;
208 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
209 return new MipsPassConfig(this, PM);
212 void MipsPassConfig::addIRPasses() {
213 TargetPassConfig::addIRPasses();
214 addPass(createAtomicExpandPass(&getMipsTargetMachine()));
215 if (getMipsSubtarget().os16())
216 addPass(createMipsOs16(getMipsTargetMachine()));
217 if (getMipsSubtarget().inMips16HardFloat())
218 addPass(createMips16HardFloat(getMipsTargetMachine()));
220 // Install an instruction selector pass using
221 // the ISelDag to gen Mips code.
222 bool MipsPassConfig::addInstSelector() {
223 addPass(createMipsModuleISelDag(getMipsTargetMachine()));
224 addPass(createMips16ISelDag(getMipsTargetMachine()));
225 addPass(createMipsSEISelDag(getMipsTargetMachine()));
229 void MipsPassConfig::addMachineSSAOptimization() {
230 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
231 TargetPassConfig::addMachineSSAOptimization();
234 void MipsPassConfig::addPreRegAlloc() {
235 if (getOptLevel() == CodeGenOpt::None)
236 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
239 TargetIRAnalysis MipsTargetMachine::getTargetIRAnalysis() {
240 return TargetIRAnalysis([this](Function &F) {
241 if (Subtarget->allowMixed16_32()) {
242 DEBUG(errs() << "No Target Transform Info Pass Added\n");
243 // FIXME: This is no longer necessary as the TTI returned is per-function.
244 return TargetTransformInfo(getDataLayout());
247 DEBUG(errs() << "Target Transform Info Pass Added\n");
248 return TargetTransformInfo(BasicTTIImpl(this, F));
252 // Implemented by targets that want to run passes immediately before
253 // machine code is emitted. return true if -print-machineinstrs should
254 // print out the code after the passes.
255 void MipsPassConfig::addPreEmitPass() {
256 MipsTargetMachine &TM = getMipsTargetMachine();
257 addPass(createMipsDelaySlotFillerPass(TM));
258 addPass(createMipsLongBranchPass(TM));
259 addPass(createMipsConstantIslandPass(TM));