1 //===-- NVPTXISelDAGToDAG.cpp - A dag to dag inst selector for NVPTX ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXISelDAGToDAG.h"
15 #include "NVPTXUtilities.h"
16 #include "llvm/Analysis/ValueTracking.h"
17 #include "llvm/IR/GlobalValue.h"
18 #include "llvm/IR/Instructions.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Target/TargetIntrinsicInfo.h"
27 #define DEBUG_TYPE "nvptx-isel"
29 static cl::opt<int> UsePrecDivF32(
30 "nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden,
31 cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
32 " IEEE Compliant F32 div.rnd if available."),
36 UsePrecSqrtF32("nvptx-prec-sqrtf32", cl::Hidden,
37 cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
41 FtzEnabled("nvptx-f32ftz", cl::ZeroOrMore, cl::Hidden,
42 cl::desc("NVPTX Specific: Flush f32 subnormals to sign-preserving zero."),
46 /// createNVPTXISelDag - This pass converts a legalized DAG into a
47 /// NVPTX-specific DAG, ready for instruction scheduling.
48 FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
49 llvm::CodeGenOpt::Level OptLevel) {
50 return new NVPTXDAGToDAGISel(TM, OptLevel);
53 NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
54 CodeGenOpt::Level OptLevel)
55 : SelectionDAGISel(tm, OptLevel), TM(tm) {
56 doMulWide = (OptLevel > 0);
59 bool NVPTXDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
60 Subtarget = &static_cast<const NVPTXSubtarget &>(MF.getSubtarget());
61 return SelectionDAGISel::runOnMachineFunction(MF);
64 int NVPTXDAGToDAGISel::getDivF32Level() const {
65 if (UsePrecDivF32.getNumOccurrences() > 0) {
66 // If nvptx-prec-div32=N is used on the command-line, always honor it
69 // Otherwise, use div.approx if fast math is enabled
70 if (TM.Options.UnsafeFPMath)
77 bool NVPTXDAGToDAGISel::usePrecSqrtF32() const {
78 if (UsePrecSqrtF32.getNumOccurrences() > 0) {
79 // If nvptx-prec-sqrtf32 is used on the command-line, always honor it
80 return UsePrecSqrtF32;
82 // Otherwise, use sqrt.approx if fast math is enabled
83 return !TM.Options.UnsafeFPMath;
87 bool NVPTXDAGToDAGISel::useF32FTZ() const {
88 if (FtzEnabled.getNumOccurrences() > 0) {
89 // If nvptx-f32ftz is used on the command-line, always honor it
92 const Function *F = MF->getFunction();
93 // Otherwise, check for an nvptx-f32ftz attribute on the function
94 if (F->hasFnAttribute("nvptx-f32ftz"))
95 return F->getFnAttribute("nvptx-f32ftz").getValueAsString() == "true";
101 bool NVPTXDAGToDAGISel::allowFMA() const {
102 const NVPTXTargetLowering *TL = Subtarget->getTargetLowering();
103 return TL->allowFMA(*MF, OptLevel);
106 /// Select - Select instructions not customized! Used for
107 /// expanded, promoted and normal instructions.
108 SDNode *NVPTXDAGToDAGISel::Select(SDNode *N) {
110 if (N->isMachineOpcode()) {
112 return nullptr; // Already selected.
115 SDNode *ResNode = nullptr;
116 switch (N->getOpcode()) {
118 ResNode = SelectLoad(N);
121 ResNode = SelectStore(N);
123 case NVPTXISD::LoadV2:
124 case NVPTXISD::LoadV4:
125 ResNode = SelectLoadVector(N);
127 case NVPTXISD::LDGV2:
128 case NVPTXISD::LDGV4:
129 case NVPTXISD::LDUV2:
130 case NVPTXISD::LDUV4:
131 ResNode = SelectLDGLDU(N);
133 case NVPTXISD::StoreV2:
134 case NVPTXISD::StoreV4:
135 ResNode = SelectStoreVector(N);
137 case NVPTXISD::LoadParam:
138 case NVPTXISD::LoadParamV2:
139 case NVPTXISD::LoadParamV4:
140 ResNode = SelectLoadParam(N);
142 case NVPTXISD::StoreRetval:
143 case NVPTXISD::StoreRetvalV2:
144 case NVPTXISD::StoreRetvalV4:
145 ResNode = SelectStoreRetval(N);
147 case NVPTXISD::StoreParam:
148 case NVPTXISD::StoreParamV2:
149 case NVPTXISD::StoreParamV4:
150 case NVPTXISD::StoreParamS32:
151 case NVPTXISD::StoreParamU32:
152 ResNode = SelectStoreParam(N);
154 case ISD::INTRINSIC_WO_CHAIN:
155 ResNode = SelectIntrinsicNoChain(N);
157 case ISD::INTRINSIC_W_CHAIN:
158 ResNode = SelectIntrinsicChain(N);
160 case NVPTXISD::Tex1DFloatS32:
161 case NVPTXISD::Tex1DFloatFloat:
162 case NVPTXISD::Tex1DFloatFloatLevel:
163 case NVPTXISD::Tex1DFloatFloatGrad:
164 case NVPTXISD::Tex1DS32S32:
165 case NVPTXISD::Tex1DS32Float:
166 case NVPTXISD::Tex1DS32FloatLevel:
167 case NVPTXISD::Tex1DS32FloatGrad:
168 case NVPTXISD::Tex1DU32S32:
169 case NVPTXISD::Tex1DU32Float:
170 case NVPTXISD::Tex1DU32FloatLevel:
171 case NVPTXISD::Tex1DU32FloatGrad:
172 case NVPTXISD::Tex1DArrayFloatS32:
173 case NVPTXISD::Tex1DArrayFloatFloat:
174 case NVPTXISD::Tex1DArrayFloatFloatLevel:
175 case NVPTXISD::Tex1DArrayFloatFloatGrad:
176 case NVPTXISD::Tex1DArrayS32S32:
177 case NVPTXISD::Tex1DArrayS32Float:
178 case NVPTXISD::Tex1DArrayS32FloatLevel:
179 case NVPTXISD::Tex1DArrayS32FloatGrad:
180 case NVPTXISD::Tex1DArrayU32S32:
181 case NVPTXISD::Tex1DArrayU32Float:
182 case NVPTXISD::Tex1DArrayU32FloatLevel:
183 case NVPTXISD::Tex1DArrayU32FloatGrad:
184 case NVPTXISD::Tex2DFloatS32:
185 case NVPTXISD::Tex2DFloatFloat:
186 case NVPTXISD::Tex2DFloatFloatLevel:
187 case NVPTXISD::Tex2DFloatFloatGrad:
188 case NVPTXISD::Tex2DS32S32:
189 case NVPTXISD::Tex2DS32Float:
190 case NVPTXISD::Tex2DS32FloatLevel:
191 case NVPTXISD::Tex2DS32FloatGrad:
192 case NVPTXISD::Tex2DU32S32:
193 case NVPTXISD::Tex2DU32Float:
194 case NVPTXISD::Tex2DU32FloatLevel:
195 case NVPTXISD::Tex2DU32FloatGrad:
196 case NVPTXISD::Tex2DArrayFloatS32:
197 case NVPTXISD::Tex2DArrayFloatFloat:
198 case NVPTXISD::Tex2DArrayFloatFloatLevel:
199 case NVPTXISD::Tex2DArrayFloatFloatGrad:
200 case NVPTXISD::Tex2DArrayS32S32:
201 case NVPTXISD::Tex2DArrayS32Float:
202 case NVPTXISD::Tex2DArrayS32FloatLevel:
203 case NVPTXISD::Tex2DArrayS32FloatGrad:
204 case NVPTXISD::Tex2DArrayU32S32:
205 case NVPTXISD::Tex2DArrayU32Float:
206 case NVPTXISD::Tex2DArrayU32FloatLevel:
207 case NVPTXISD::Tex2DArrayU32FloatGrad:
208 case NVPTXISD::Tex3DFloatS32:
209 case NVPTXISD::Tex3DFloatFloat:
210 case NVPTXISD::Tex3DFloatFloatLevel:
211 case NVPTXISD::Tex3DFloatFloatGrad:
212 case NVPTXISD::Tex3DS32S32:
213 case NVPTXISD::Tex3DS32Float:
214 case NVPTXISD::Tex3DS32FloatLevel:
215 case NVPTXISD::Tex3DS32FloatGrad:
216 case NVPTXISD::Tex3DU32S32:
217 case NVPTXISD::Tex3DU32Float:
218 case NVPTXISD::Tex3DU32FloatLevel:
219 case NVPTXISD::Tex3DU32FloatGrad:
220 case NVPTXISD::TexCubeFloatFloat:
221 case NVPTXISD::TexCubeFloatFloatLevel:
222 case NVPTXISD::TexCubeS32Float:
223 case NVPTXISD::TexCubeS32FloatLevel:
224 case NVPTXISD::TexCubeU32Float:
225 case NVPTXISD::TexCubeU32FloatLevel:
226 case NVPTXISD::TexCubeArrayFloatFloat:
227 case NVPTXISD::TexCubeArrayFloatFloatLevel:
228 case NVPTXISD::TexCubeArrayS32Float:
229 case NVPTXISD::TexCubeArrayS32FloatLevel:
230 case NVPTXISD::TexCubeArrayU32Float:
231 case NVPTXISD::TexCubeArrayU32FloatLevel:
232 case NVPTXISD::Tld4R2DFloatFloat:
233 case NVPTXISD::Tld4G2DFloatFloat:
234 case NVPTXISD::Tld4B2DFloatFloat:
235 case NVPTXISD::Tld4A2DFloatFloat:
236 case NVPTXISD::Tld4R2DS64Float:
237 case NVPTXISD::Tld4G2DS64Float:
238 case NVPTXISD::Tld4B2DS64Float:
239 case NVPTXISD::Tld4A2DS64Float:
240 case NVPTXISD::Tld4R2DU64Float:
241 case NVPTXISD::Tld4G2DU64Float:
242 case NVPTXISD::Tld4B2DU64Float:
243 case NVPTXISD::Tld4A2DU64Float:
244 case NVPTXISD::TexUnified1DFloatS32:
245 case NVPTXISD::TexUnified1DFloatFloat:
246 case NVPTXISD::TexUnified1DFloatFloatLevel:
247 case NVPTXISD::TexUnified1DFloatFloatGrad:
248 case NVPTXISD::TexUnified1DS32S32:
249 case NVPTXISD::TexUnified1DS32Float:
250 case NVPTXISD::TexUnified1DS32FloatLevel:
251 case NVPTXISD::TexUnified1DS32FloatGrad:
252 case NVPTXISD::TexUnified1DU32S32:
253 case NVPTXISD::TexUnified1DU32Float:
254 case NVPTXISD::TexUnified1DU32FloatLevel:
255 case NVPTXISD::TexUnified1DU32FloatGrad:
256 case NVPTXISD::TexUnified1DArrayFloatS32:
257 case NVPTXISD::TexUnified1DArrayFloatFloat:
258 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
259 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
260 case NVPTXISD::TexUnified1DArrayS32S32:
261 case NVPTXISD::TexUnified1DArrayS32Float:
262 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
263 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
264 case NVPTXISD::TexUnified1DArrayU32S32:
265 case NVPTXISD::TexUnified1DArrayU32Float:
266 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
267 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
268 case NVPTXISD::TexUnified2DFloatS32:
269 case NVPTXISD::TexUnified2DFloatFloat:
270 case NVPTXISD::TexUnified2DFloatFloatLevel:
271 case NVPTXISD::TexUnified2DFloatFloatGrad:
272 case NVPTXISD::TexUnified2DS32S32:
273 case NVPTXISD::TexUnified2DS32Float:
274 case NVPTXISD::TexUnified2DS32FloatLevel:
275 case NVPTXISD::TexUnified2DS32FloatGrad:
276 case NVPTXISD::TexUnified2DU32S32:
277 case NVPTXISD::TexUnified2DU32Float:
278 case NVPTXISD::TexUnified2DU32FloatLevel:
279 case NVPTXISD::TexUnified2DU32FloatGrad:
280 case NVPTXISD::TexUnified2DArrayFloatS32:
281 case NVPTXISD::TexUnified2DArrayFloatFloat:
282 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
283 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
284 case NVPTXISD::TexUnified2DArrayS32S32:
285 case NVPTXISD::TexUnified2DArrayS32Float:
286 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
287 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
288 case NVPTXISD::TexUnified2DArrayU32S32:
289 case NVPTXISD::TexUnified2DArrayU32Float:
290 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
291 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
292 case NVPTXISD::TexUnified3DFloatS32:
293 case NVPTXISD::TexUnified3DFloatFloat:
294 case NVPTXISD::TexUnified3DFloatFloatLevel:
295 case NVPTXISD::TexUnified3DFloatFloatGrad:
296 case NVPTXISD::TexUnified3DS32S32:
297 case NVPTXISD::TexUnified3DS32Float:
298 case NVPTXISD::TexUnified3DS32FloatLevel:
299 case NVPTXISD::TexUnified3DS32FloatGrad:
300 case NVPTXISD::TexUnified3DU32S32:
301 case NVPTXISD::TexUnified3DU32Float:
302 case NVPTXISD::TexUnified3DU32FloatLevel:
303 case NVPTXISD::TexUnified3DU32FloatGrad:
304 case NVPTXISD::TexUnifiedCubeFloatFloat:
305 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
306 case NVPTXISD::TexUnifiedCubeS32Float:
307 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
308 case NVPTXISD::TexUnifiedCubeU32Float:
309 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
310 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
311 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
312 case NVPTXISD::TexUnifiedCubeArrayS32Float:
313 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
314 case NVPTXISD::TexUnifiedCubeArrayU32Float:
315 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
316 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
317 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
318 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
319 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
320 case NVPTXISD::Tld4UnifiedR2DS64Float:
321 case NVPTXISD::Tld4UnifiedG2DS64Float:
322 case NVPTXISD::Tld4UnifiedB2DS64Float:
323 case NVPTXISD::Tld4UnifiedA2DS64Float:
324 case NVPTXISD::Tld4UnifiedR2DU64Float:
325 case NVPTXISD::Tld4UnifiedG2DU64Float:
326 case NVPTXISD::Tld4UnifiedB2DU64Float:
327 case NVPTXISD::Tld4UnifiedA2DU64Float:
328 ResNode = SelectTextureIntrinsic(N);
330 case NVPTXISD::Suld1DI8Clamp:
331 case NVPTXISD::Suld1DI16Clamp:
332 case NVPTXISD::Suld1DI32Clamp:
333 case NVPTXISD::Suld1DI64Clamp:
334 case NVPTXISD::Suld1DV2I8Clamp:
335 case NVPTXISD::Suld1DV2I16Clamp:
336 case NVPTXISD::Suld1DV2I32Clamp:
337 case NVPTXISD::Suld1DV2I64Clamp:
338 case NVPTXISD::Suld1DV4I8Clamp:
339 case NVPTXISD::Suld1DV4I16Clamp:
340 case NVPTXISD::Suld1DV4I32Clamp:
341 case NVPTXISD::Suld1DArrayI8Clamp:
342 case NVPTXISD::Suld1DArrayI16Clamp:
343 case NVPTXISD::Suld1DArrayI32Clamp:
344 case NVPTXISD::Suld1DArrayI64Clamp:
345 case NVPTXISD::Suld1DArrayV2I8Clamp:
346 case NVPTXISD::Suld1DArrayV2I16Clamp:
347 case NVPTXISD::Suld1DArrayV2I32Clamp:
348 case NVPTXISD::Suld1DArrayV2I64Clamp:
349 case NVPTXISD::Suld1DArrayV4I8Clamp:
350 case NVPTXISD::Suld1DArrayV4I16Clamp:
351 case NVPTXISD::Suld1DArrayV4I32Clamp:
352 case NVPTXISD::Suld2DI8Clamp:
353 case NVPTXISD::Suld2DI16Clamp:
354 case NVPTXISD::Suld2DI32Clamp:
355 case NVPTXISD::Suld2DI64Clamp:
356 case NVPTXISD::Suld2DV2I8Clamp:
357 case NVPTXISD::Suld2DV2I16Clamp:
358 case NVPTXISD::Suld2DV2I32Clamp:
359 case NVPTXISD::Suld2DV2I64Clamp:
360 case NVPTXISD::Suld2DV4I8Clamp:
361 case NVPTXISD::Suld2DV4I16Clamp:
362 case NVPTXISD::Suld2DV4I32Clamp:
363 case NVPTXISD::Suld2DArrayI8Clamp:
364 case NVPTXISD::Suld2DArrayI16Clamp:
365 case NVPTXISD::Suld2DArrayI32Clamp:
366 case NVPTXISD::Suld2DArrayI64Clamp:
367 case NVPTXISD::Suld2DArrayV2I8Clamp:
368 case NVPTXISD::Suld2DArrayV2I16Clamp:
369 case NVPTXISD::Suld2DArrayV2I32Clamp:
370 case NVPTXISD::Suld2DArrayV2I64Clamp:
371 case NVPTXISD::Suld2DArrayV4I8Clamp:
372 case NVPTXISD::Suld2DArrayV4I16Clamp:
373 case NVPTXISD::Suld2DArrayV4I32Clamp:
374 case NVPTXISD::Suld3DI8Clamp:
375 case NVPTXISD::Suld3DI16Clamp:
376 case NVPTXISD::Suld3DI32Clamp:
377 case NVPTXISD::Suld3DI64Clamp:
378 case NVPTXISD::Suld3DV2I8Clamp:
379 case NVPTXISD::Suld3DV2I16Clamp:
380 case NVPTXISD::Suld3DV2I32Clamp:
381 case NVPTXISD::Suld3DV2I64Clamp:
382 case NVPTXISD::Suld3DV4I8Clamp:
383 case NVPTXISD::Suld3DV4I16Clamp:
384 case NVPTXISD::Suld3DV4I32Clamp:
385 case NVPTXISD::Suld1DI8Trap:
386 case NVPTXISD::Suld1DI16Trap:
387 case NVPTXISD::Suld1DI32Trap:
388 case NVPTXISD::Suld1DI64Trap:
389 case NVPTXISD::Suld1DV2I8Trap:
390 case NVPTXISD::Suld1DV2I16Trap:
391 case NVPTXISD::Suld1DV2I32Trap:
392 case NVPTXISD::Suld1DV2I64Trap:
393 case NVPTXISD::Suld1DV4I8Trap:
394 case NVPTXISD::Suld1DV4I16Trap:
395 case NVPTXISD::Suld1DV4I32Trap:
396 case NVPTXISD::Suld1DArrayI8Trap:
397 case NVPTXISD::Suld1DArrayI16Trap:
398 case NVPTXISD::Suld1DArrayI32Trap:
399 case NVPTXISD::Suld1DArrayI64Trap:
400 case NVPTXISD::Suld1DArrayV2I8Trap:
401 case NVPTXISD::Suld1DArrayV2I16Trap:
402 case NVPTXISD::Suld1DArrayV2I32Trap:
403 case NVPTXISD::Suld1DArrayV2I64Trap:
404 case NVPTXISD::Suld1DArrayV4I8Trap:
405 case NVPTXISD::Suld1DArrayV4I16Trap:
406 case NVPTXISD::Suld1DArrayV4I32Trap:
407 case NVPTXISD::Suld2DI8Trap:
408 case NVPTXISD::Suld2DI16Trap:
409 case NVPTXISD::Suld2DI32Trap:
410 case NVPTXISD::Suld2DI64Trap:
411 case NVPTXISD::Suld2DV2I8Trap:
412 case NVPTXISD::Suld2DV2I16Trap:
413 case NVPTXISD::Suld2DV2I32Trap:
414 case NVPTXISD::Suld2DV2I64Trap:
415 case NVPTXISD::Suld2DV4I8Trap:
416 case NVPTXISD::Suld2DV4I16Trap:
417 case NVPTXISD::Suld2DV4I32Trap:
418 case NVPTXISD::Suld2DArrayI8Trap:
419 case NVPTXISD::Suld2DArrayI16Trap:
420 case NVPTXISD::Suld2DArrayI32Trap:
421 case NVPTXISD::Suld2DArrayI64Trap:
422 case NVPTXISD::Suld2DArrayV2I8Trap:
423 case NVPTXISD::Suld2DArrayV2I16Trap:
424 case NVPTXISD::Suld2DArrayV2I32Trap:
425 case NVPTXISD::Suld2DArrayV2I64Trap:
426 case NVPTXISD::Suld2DArrayV4I8Trap:
427 case NVPTXISD::Suld2DArrayV4I16Trap:
428 case NVPTXISD::Suld2DArrayV4I32Trap:
429 case NVPTXISD::Suld3DI8Trap:
430 case NVPTXISD::Suld3DI16Trap:
431 case NVPTXISD::Suld3DI32Trap:
432 case NVPTXISD::Suld3DI64Trap:
433 case NVPTXISD::Suld3DV2I8Trap:
434 case NVPTXISD::Suld3DV2I16Trap:
435 case NVPTXISD::Suld3DV2I32Trap:
436 case NVPTXISD::Suld3DV2I64Trap:
437 case NVPTXISD::Suld3DV4I8Trap:
438 case NVPTXISD::Suld3DV4I16Trap:
439 case NVPTXISD::Suld3DV4I32Trap:
440 case NVPTXISD::Suld1DI8Zero:
441 case NVPTXISD::Suld1DI16Zero:
442 case NVPTXISD::Suld1DI32Zero:
443 case NVPTXISD::Suld1DI64Zero:
444 case NVPTXISD::Suld1DV2I8Zero:
445 case NVPTXISD::Suld1DV2I16Zero:
446 case NVPTXISD::Suld1DV2I32Zero:
447 case NVPTXISD::Suld1DV2I64Zero:
448 case NVPTXISD::Suld1DV4I8Zero:
449 case NVPTXISD::Suld1DV4I16Zero:
450 case NVPTXISD::Suld1DV4I32Zero:
451 case NVPTXISD::Suld1DArrayI8Zero:
452 case NVPTXISD::Suld1DArrayI16Zero:
453 case NVPTXISD::Suld1DArrayI32Zero:
454 case NVPTXISD::Suld1DArrayI64Zero:
455 case NVPTXISD::Suld1DArrayV2I8Zero:
456 case NVPTXISD::Suld1DArrayV2I16Zero:
457 case NVPTXISD::Suld1DArrayV2I32Zero:
458 case NVPTXISD::Suld1DArrayV2I64Zero:
459 case NVPTXISD::Suld1DArrayV4I8Zero:
460 case NVPTXISD::Suld1DArrayV4I16Zero:
461 case NVPTXISD::Suld1DArrayV4I32Zero:
462 case NVPTXISD::Suld2DI8Zero:
463 case NVPTXISD::Suld2DI16Zero:
464 case NVPTXISD::Suld2DI32Zero:
465 case NVPTXISD::Suld2DI64Zero:
466 case NVPTXISD::Suld2DV2I8Zero:
467 case NVPTXISD::Suld2DV2I16Zero:
468 case NVPTXISD::Suld2DV2I32Zero:
469 case NVPTXISD::Suld2DV2I64Zero:
470 case NVPTXISD::Suld2DV4I8Zero:
471 case NVPTXISD::Suld2DV4I16Zero:
472 case NVPTXISD::Suld2DV4I32Zero:
473 case NVPTXISD::Suld2DArrayI8Zero:
474 case NVPTXISD::Suld2DArrayI16Zero:
475 case NVPTXISD::Suld2DArrayI32Zero:
476 case NVPTXISD::Suld2DArrayI64Zero:
477 case NVPTXISD::Suld2DArrayV2I8Zero:
478 case NVPTXISD::Suld2DArrayV2I16Zero:
479 case NVPTXISD::Suld2DArrayV2I32Zero:
480 case NVPTXISD::Suld2DArrayV2I64Zero:
481 case NVPTXISD::Suld2DArrayV4I8Zero:
482 case NVPTXISD::Suld2DArrayV4I16Zero:
483 case NVPTXISD::Suld2DArrayV4I32Zero:
484 case NVPTXISD::Suld3DI8Zero:
485 case NVPTXISD::Suld3DI16Zero:
486 case NVPTXISD::Suld3DI32Zero:
487 case NVPTXISD::Suld3DI64Zero:
488 case NVPTXISD::Suld3DV2I8Zero:
489 case NVPTXISD::Suld3DV2I16Zero:
490 case NVPTXISD::Suld3DV2I32Zero:
491 case NVPTXISD::Suld3DV2I64Zero:
492 case NVPTXISD::Suld3DV4I8Zero:
493 case NVPTXISD::Suld3DV4I16Zero:
494 case NVPTXISD::Suld3DV4I32Zero:
495 ResNode = SelectSurfaceIntrinsic(N);
501 ResNode = SelectBFE(N);
503 case ISD::ADDRSPACECAST:
504 ResNode = SelectAddrSpaceCast(N);
511 return SelectCode(N);
514 SDNode *NVPTXDAGToDAGISel::SelectIntrinsicChain(SDNode *N) {
515 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
519 case Intrinsic::nvvm_ldg_global_f:
520 case Intrinsic::nvvm_ldg_global_i:
521 case Intrinsic::nvvm_ldg_global_p:
522 case Intrinsic::nvvm_ldu_global_f:
523 case Intrinsic::nvvm_ldu_global_i:
524 case Intrinsic::nvvm_ldu_global_p:
525 return SelectLDGLDU(N);
529 static unsigned int getCodeAddrSpace(MemSDNode *N) {
530 const Value *Src = N->getMemOperand()->getValue();
533 return NVPTX::PTXLdStInstCode::GENERIC;
535 if (auto *PT = dyn_cast<PointerType>(Src->getType())) {
536 switch (PT->getAddressSpace()) {
537 case llvm::ADDRESS_SPACE_LOCAL: return NVPTX::PTXLdStInstCode::LOCAL;
538 case llvm::ADDRESS_SPACE_GLOBAL: return NVPTX::PTXLdStInstCode::GLOBAL;
539 case llvm::ADDRESS_SPACE_SHARED: return NVPTX::PTXLdStInstCode::SHARED;
540 case llvm::ADDRESS_SPACE_GENERIC: return NVPTX::PTXLdStInstCode::GENERIC;
541 case llvm::ADDRESS_SPACE_PARAM: return NVPTX::PTXLdStInstCode::PARAM;
542 case llvm::ADDRESS_SPACE_CONST: return NVPTX::PTXLdStInstCode::CONSTANT;
546 return NVPTX::PTXLdStInstCode::GENERIC;
549 static bool canLowerToLDG(MemSDNode *N, const NVPTXSubtarget &Subtarget,
550 unsigned CodeAddrSpace, MachineFunction *F) {
551 // To use non-coherent caching, the load has to be from global
552 // memory and we have to prove that the memory area is not written
553 // to anywhere for the duration of the kernel call, not even after
556 // To ensure that there are no writes to the memory, we require the
557 // underlying pointer to be a noalias (__restrict) kernel parameter
558 // that is never used for a write. We can only do this for kernel
559 // functions since from within a device function, we cannot know if
560 // there were or will be writes to the memory from the caller - or we
561 // could, but then we would have to do inter-procedural analysis.
562 if (!Subtarget.hasLDG() || CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL ||
563 !isKernelFunction(*F->getFunction())) {
567 // We use GetUnderlyingObjects() here instead of
568 // GetUnderlyingObject() mainly because the former looks through phi
569 // nodes while the latter does not. We need to look through phi
570 // nodes to handle pointer induction variables.
571 SmallVector<Value *, 8> Objs;
572 GetUnderlyingObjects(const_cast<Value *>(N->getMemOperand()->getValue()),
573 Objs, F->getDataLayout());
574 for (Value *Obj : Objs) {
575 auto *A = dyn_cast<const Argument>(Obj);
576 if (!A || !A->onlyReadsMemory() || !A->hasNoAliasAttr()) return false;
582 SDNode *NVPTXDAGToDAGISel::SelectIntrinsicNoChain(SDNode *N) {
583 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
587 case Intrinsic::nvvm_texsurf_handle_internal:
588 return SelectTexSurfHandle(N);
592 SDNode *NVPTXDAGToDAGISel::SelectTexSurfHandle(SDNode *N) {
593 // Op 0 is the intrinsic ID
594 SDValue Wrapper = N->getOperand(1);
595 SDValue GlobalVal = Wrapper.getOperand(0);
596 return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64,
600 SDNode *NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
601 SDValue Src = N->getOperand(0);
602 AddrSpaceCastSDNode *CastN = cast<AddrSpaceCastSDNode>(N);
603 unsigned SrcAddrSpace = CastN->getSrcAddressSpace();
604 unsigned DstAddrSpace = CastN->getDestAddressSpace();
606 assert(SrcAddrSpace != DstAddrSpace &&
607 "addrspacecast must be between different address spaces");
609 if (DstAddrSpace == ADDRESS_SPACE_GENERIC) {
610 // Specific to generic
612 switch (SrcAddrSpace) {
613 default: report_fatal_error("Bad address space in addrspacecast");
614 case ADDRESS_SPACE_GLOBAL:
615 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes;
617 case ADDRESS_SPACE_SHARED:
618 Opc = TM.is64Bit() ? NVPTX::cvta_shared_yes_64 : NVPTX::cvta_shared_yes;
620 case ADDRESS_SPACE_CONST:
621 Opc = TM.is64Bit() ? NVPTX::cvta_const_yes_64 : NVPTX::cvta_const_yes;
623 case ADDRESS_SPACE_LOCAL:
624 Opc = TM.is64Bit() ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes;
627 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
629 // Generic to specific
630 if (SrcAddrSpace != 0)
631 report_fatal_error("Cannot cast between two non-generic address spaces");
633 switch (DstAddrSpace) {
634 default: report_fatal_error("Bad address space in addrspacecast");
635 case ADDRESS_SPACE_GLOBAL:
636 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64
637 : NVPTX::cvta_to_global_yes;
639 case ADDRESS_SPACE_SHARED:
640 Opc = TM.is64Bit() ? NVPTX::cvta_to_shared_yes_64
641 : NVPTX::cvta_to_shared_yes;
643 case ADDRESS_SPACE_CONST:
645 TM.is64Bit() ? NVPTX::cvta_to_const_yes_64 : NVPTX::cvta_to_const_yes;
647 case ADDRESS_SPACE_LOCAL:
649 TM.is64Bit() ? NVPTX::cvta_to_local_yes_64 : NVPTX::cvta_to_local_yes;
651 case ADDRESS_SPACE_PARAM:
652 Opc = TM.is64Bit() ? NVPTX::nvvm_ptr_gen_to_param_64
653 : NVPTX::nvvm_ptr_gen_to_param;
656 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
660 SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
662 LoadSDNode *LD = cast<LoadSDNode>(N);
663 EVT LoadedVT = LD->getMemoryVT();
664 SDNode *NVPTXLD = nullptr;
666 // do not support pre/post inc/dec
670 if (!LoadedVT.isSimple())
673 // Address Space Setting
674 unsigned int codeAddrSpace = getCodeAddrSpace(LD);
676 if (canLowerToLDG(LD, *Subtarget, codeAddrSpace, MF)) {
677 return SelectLDGLDU(N);
681 // - .volatile is only availalble for .global and .shared
682 bool isVolatile = LD->isVolatile();
683 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
684 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
685 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
689 MVT SimpleVT = LoadedVT.getSimpleVT();
690 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
691 if (SimpleVT.isVector()) {
692 unsigned num = SimpleVT.getVectorNumElements();
694 vecType = NVPTX::PTXLdStInstCode::V2;
696 vecType = NVPTX::PTXLdStInstCode::V4;
701 // Type Setting: fromType + fromTypeWidth
703 // Sign : ISD::SEXTLOAD
704 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
706 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
707 MVT ScalarVT = SimpleVT.getScalarType();
708 // Read at least 8 bits (predicates are stored as 8-bit values)
709 unsigned fromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
710 unsigned int fromType;
711 if ((LD->getExtensionType() == ISD::SEXTLOAD))
712 fromType = NVPTX::PTXLdStInstCode::Signed;
713 else if (ScalarVT.isFloatingPoint())
714 fromType = NVPTX::PTXLdStInstCode::Float;
716 fromType = NVPTX::PTXLdStInstCode::Unsigned;
718 // Create the machine instruction DAG
719 SDValue Chain = N->getOperand(0);
720 SDValue N1 = N->getOperand(1);
722 SDValue Offset, Base;
724 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
726 if (SelectDirectAddr(N1, Addr)) {
729 Opcode = NVPTX::LD_i8_avar;
732 Opcode = NVPTX::LD_i16_avar;
735 Opcode = NVPTX::LD_i32_avar;
738 Opcode = NVPTX::LD_i64_avar;
741 Opcode = NVPTX::LD_f32_avar;
744 Opcode = NVPTX::LD_f64_avar;
749 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
750 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
751 getI32Imm(fromTypeWidth, dl), Addr, Chain };
752 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
753 } else if (TM.is64Bit() ? SelectADDRsi64(N1.getNode(), N1, Base, Offset)
754 : SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
757 Opcode = NVPTX::LD_i8_asi;
760 Opcode = NVPTX::LD_i16_asi;
763 Opcode = NVPTX::LD_i32_asi;
766 Opcode = NVPTX::LD_i64_asi;
769 Opcode = NVPTX::LD_f32_asi;
772 Opcode = NVPTX::LD_f64_asi;
777 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
778 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
779 getI32Imm(fromTypeWidth, dl), Base, Offset, Chain };
780 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
781 } else if (TM.is64Bit() ? SelectADDRri64(N1.getNode(), N1, Base, Offset)
782 : SelectADDRri(N1.getNode(), N1, Base, Offset)) {
786 Opcode = NVPTX::LD_i8_ari_64;
789 Opcode = NVPTX::LD_i16_ari_64;
792 Opcode = NVPTX::LD_i32_ari_64;
795 Opcode = NVPTX::LD_i64_ari_64;
798 Opcode = NVPTX::LD_f32_ari_64;
801 Opcode = NVPTX::LD_f64_ari_64;
809 Opcode = NVPTX::LD_i8_ari;
812 Opcode = NVPTX::LD_i16_ari;
815 Opcode = NVPTX::LD_i32_ari;
818 Opcode = NVPTX::LD_i64_ari;
821 Opcode = NVPTX::LD_f32_ari;
824 Opcode = NVPTX::LD_f64_ari;
830 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
831 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
832 getI32Imm(fromTypeWidth, dl), Base, Offset, Chain };
833 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
838 Opcode = NVPTX::LD_i8_areg_64;
841 Opcode = NVPTX::LD_i16_areg_64;
844 Opcode = NVPTX::LD_i32_areg_64;
847 Opcode = NVPTX::LD_i64_areg_64;
850 Opcode = NVPTX::LD_f32_areg_64;
853 Opcode = NVPTX::LD_f64_areg_64;
861 Opcode = NVPTX::LD_i8_areg;
864 Opcode = NVPTX::LD_i16_areg;
867 Opcode = NVPTX::LD_i32_areg;
870 Opcode = NVPTX::LD_i64_areg;
873 Opcode = NVPTX::LD_f32_areg;
876 Opcode = NVPTX::LD_f64_areg;
882 SDValue Ops[] = { getI32Imm(isVolatile, dl), getI32Imm(codeAddrSpace, dl),
883 getI32Imm(vecType, dl), getI32Imm(fromType, dl),
884 getI32Imm(fromTypeWidth, dl), N1, Chain };
885 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
889 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
890 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
891 cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
897 SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
899 SDValue Chain = N->getOperand(0);
900 SDValue Op1 = N->getOperand(1);
901 SDValue Addr, Offset, Base;
905 MemSDNode *MemSD = cast<MemSDNode>(N);
906 EVT LoadedVT = MemSD->getMemoryVT();
908 if (!LoadedVT.isSimple())
911 // Address Space Setting
912 unsigned int CodeAddrSpace = getCodeAddrSpace(MemSD);
914 if (canLowerToLDG(MemSD, *Subtarget, CodeAddrSpace, MF)) {
915 return SelectLDGLDU(N);
919 // - .volatile is only availalble for .global and .shared
920 bool IsVolatile = MemSD->isVolatile();
921 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
922 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
923 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
927 MVT SimpleVT = LoadedVT.getSimpleVT();
929 // Type Setting: fromType + fromTypeWidth
931 // Sign : ISD::SEXTLOAD
932 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
934 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
935 MVT ScalarVT = SimpleVT.getScalarType();
936 // Read at least 8 bits (predicates are stored as 8-bit values)
937 unsigned FromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
938 unsigned int FromType;
939 // The last operand holds the original LoadSDNode::getExtensionType() value
940 unsigned ExtensionType = cast<ConstantSDNode>(
941 N->getOperand(N->getNumOperands() - 1))->getZExtValue();
942 if (ExtensionType == ISD::SEXTLOAD)
943 FromType = NVPTX::PTXLdStInstCode::Signed;
944 else if (ScalarVT.isFloatingPoint())
945 FromType = NVPTX::PTXLdStInstCode::Float;
947 FromType = NVPTX::PTXLdStInstCode::Unsigned;
951 switch (N->getOpcode()) {
952 case NVPTXISD::LoadV2:
953 VecType = NVPTX::PTXLdStInstCode::V2;
955 case NVPTXISD::LoadV4:
956 VecType = NVPTX::PTXLdStInstCode::V4;
962 EVT EltVT = N->getValueType(0);
964 if (SelectDirectAddr(Op1, Addr)) {
965 switch (N->getOpcode()) {
968 case NVPTXISD::LoadV2:
969 switch (EltVT.getSimpleVT().SimpleTy) {
973 Opcode = NVPTX::LDV_i8_v2_avar;
976 Opcode = NVPTX::LDV_i16_v2_avar;
979 Opcode = NVPTX::LDV_i32_v2_avar;
982 Opcode = NVPTX::LDV_i64_v2_avar;
985 Opcode = NVPTX::LDV_f32_v2_avar;
988 Opcode = NVPTX::LDV_f64_v2_avar;
992 case NVPTXISD::LoadV4:
993 switch (EltVT.getSimpleVT().SimpleTy) {
997 Opcode = NVPTX::LDV_i8_v4_avar;
1000 Opcode = NVPTX::LDV_i16_v4_avar;
1003 Opcode = NVPTX::LDV_i32_v4_avar;
1006 Opcode = NVPTX::LDV_f32_v4_avar;
1012 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1013 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1014 getI32Imm(FromTypeWidth, DL), Addr, Chain };
1015 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1016 } else if (TM.is64Bit() ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset)
1017 : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
1018 switch (N->getOpcode()) {
1021 case NVPTXISD::LoadV2:
1022 switch (EltVT.getSimpleVT().SimpleTy) {
1026 Opcode = NVPTX::LDV_i8_v2_asi;
1029 Opcode = NVPTX::LDV_i16_v2_asi;
1032 Opcode = NVPTX::LDV_i32_v2_asi;
1035 Opcode = NVPTX::LDV_i64_v2_asi;
1038 Opcode = NVPTX::LDV_f32_v2_asi;
1041 Opcode = NVPTX::LDV_f64_v2_asi;
1045 case NVPTXISD::LoadV4:
1046 switch (EltVT.getSimpleVT().SimpleTy) {
1050 Opcode = NVPTX::LDV_i8_v4_asi;
1053 Opcode = NVPTX::LDV_i16_v4_asi;
1056 Opcode = NVPTX::LDV_i32_v4_asi;
1059 Opcode = NVPTX::LDV_f32_v4_asi;
1065 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1066 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1067 getI32Imm(FromTypeWidth, DL), Base, Offset, Chain };
1068 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1069 } else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1070 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1072 switch (N->getOpcode()) {
1075 case NVPTXISD::LoadV2:
1076 switch (EltVT.getSimpleVT().SimpleTy) {
1080 Opcode = NVPTX::LDV_i8_v2_ari_64;
1083 Opcode = NVPTX::LDV_i16_v2_ari_64;
1086 Opcode = NVPTX::LDV_i32_v2_ari_64;
1089 Opcode = NVPTX::LDV_i64_v2_ari_64;
1092 Opcode = NVPTX::LDV_f32_v2_ari_64;
1095 Opcode = NVPTX::LDV_f64_v2_ari_64;
1099 case NVPTXISD::LoadV4:
1100 switch (EltVT.getSimpleVT().SimpleTy) {
1104 Opcode = NVPTX::LDV_i8_v4_ari_64;
1107 Opcode = NVPTX::LDV_i16_v4_ari_64;
1110 Opcode = NVPTX::LDV_i32_v4_ari_64;
1113 Opcode = NVPTX::LDV_f32_v4_ari_64;
1119 switch (N->getOpcode()) {
1122 case NVPTXISD::LoadV2:
1123 switch (EltVT.getSimpleVT().SimpleTy) {
1127 Opcode = NVPTX::LDV_i8_v2_ari;
1130 Opcode = NVPTX::LDV_i16_v2_ari;
1133 Opcode = NVPTX::LDV_i32_v2_ari;
1136 Opcode = NVPTX::LDV_i64_v2_ari;
1139 Opcode = NVPTX::LDV_f32_v2_ari;
1142 Opcode = NVPTX::LDV_f64_v2_ari;
1146 case NVPTXISD::LoadV4:
1147 switch (EltVT.getSimpleVT().SimpleTy) {
1151 Opcode = NVPTX::LDV_i8_v4_ari;
1154 Opcode = NVPTX::LDV_i16_v4_ari;
1157 Opcode = NVPTX::LDV_i32_v4_ari;
1160 Opcode = NVPTX::LDV_f32_v4_ari;
1167 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1168 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1169 getI32Imm(FromTypeWidth, DL), Base, Offset, Chain };
1171 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1174 switch (N->getOpcode()) {
1177 case NVPTXISD::LoadV2:
1178 switch (EltVT.getSimpleVT().SimpleTy) {
1182 Opcode = NVPTX::LDV_i8_v2_areg_64;
1185 Opcode = NVPTX::LDV_i16_v2_areg_64;
1188 Opcode = NVPTX::LDV_i32_v2_areg_64;
1191 Opcode = NVPTX::LDV_i64_v2_areg_64;
1194 Opcode = NVPTX::LDV_f32_v2_areg_64;
1197 Opcode = NVPTX::LDV_f64_v2_areg_64;
1201 case NVPTXISD::LoadV4:
1202 switch (EltVT.getSimpleVT().SimpleTy) {
1206 Opcode = NVPTX::LDV_i8_v4_areg_64;
1209 Opcode = NVPTX::LDV_i16_v4_areg_64;
1212 Opcode = NVPTX::LDV_i32_v4_areg_64;
1215 Opcode = NVPTX::LDV_f32_v4_areg_64;
1221 switch (N->getOpcode()) {
1224 case NVPTXISD::LoadV2:
1225 switch (EltVT.getSimpleVT().SimpleTy) {
1229 Opcode = NVPTX::LDV_i8_v2_areg;
1232 Opcode = NVPTX::LDV_i16_v2_areg;
1235 Opcode = NVPTX::LDV_i32_v2_areg;
1238 Opcode = NVPTX::LDV_i64_v2_areg;
1241 Opcode = NVPTX::LDV_f32_v2_areg;
1244 Opcode = NVPTX::LDV_f64_v2_areg;
1248 case NVPTXISD::LoadV4:
1249 switch (EltVT.getSimpleVT().SimpleTy) {
1253 Opcode = NVPTX::LDV_i8_v4_areg;
1256 Opcode = NVPTX::LDV_i16_v4_areg;
1259 Opcode = NVPTX::LDV_i32_v4_areg;
1262 Opcode = NVPTX::LDV_f32_v4_areg;
1269 SDValue Ops[] = { getI32Imm(IsVolatile, DL), getI32Imm(CodeAddrSpace, DL),
1270 getI32Imm(VecType, DL), getI32Imm(FromType, DL),
1271 getI32Imm(FromTypeWidth, DL), Op1, Chain };
1272 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1275 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1276 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
1277 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1282 SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(SDNode *N) {
1284 SDValue Chain = N->getOperand(0);
1289 // If this is an LDG intrinsic, the address is the third operand. Its its an
1290 // LDG/LDU SD node (from custom vector handling), then its the second operand
1291 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
1292 Op1 = N->getOperand(2);
1293 Mem = cast<MemIntrinsicSDNode>(N);
1294 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1298 case Intrinsic::nvvm_ldg_global_f:
1299 case Intrinsic::nvvm_ldg_global_i:
1300 case Intrinsic::nvvm_ldg_global_p:
1303 case Intrinsic::nvvm_ldu_global_f:
1304 case Intrinsic::nvvm_ldu_global_i:
1305 case Intrinsic::nvvm_ldu_global_p:
1310 Op1 = N->getOperand(1);
1311 Mem = cast<MemSDNode>(N);
1317 SDValue Base, Offset, Addr;
1319 EVT EltVT = Mem->getMemoryVT();
1320 if (EltVT.isVector()) {
1321 EltVT = EltVT.getVectorElementType();
1324 if (SelectDirectAddr(Op1, Addr)) {
1325 switch (N->getOpcode()) {
1328 case ISD::INTRINSIC_W_CHAIN:
1330 switch (EltVT.getSimpleVT().SimpleTy) {
1334 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8avar;
1337 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16avar;
1340 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32avar;
1343 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64avar;
1346 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32avar;
1349 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64avar;
1353 switch (EltVT.getSimpleVT().SimpleTy) {
1357 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8avar;
1360 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16avar;
1363 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32avar;
1366 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64avar;
1369 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32avar;
1372 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64avar;
1377 case NVPTXISD::LDGV2:
1378 switch (EltVT.getSimpleVT().SimpleTy) {
1382 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_avar;
1385 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_avar;
1388 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_avar;
1391 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_avar;
1394 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_avar;
1397 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_avar;
1401 case NVPTXISD::LDUV2:
1402 switch (EltVT.getSimpleVT().SimpleTy) {
1406 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_avar;
1409 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_avar;
1412 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_avar;
1415 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_avar;
1418 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_avar;
1421 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_avar;
1425 case NVPTXISD::LDGV4:
1426 switch (EltVT.getSimpleVT().SimpleTy) {
1430 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_avar;
1433 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_avar;
1436 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_avar;
1439 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_avar;
1443 case NVPTXISD::LDUV4:
1444 switch (EltVT.getSimpleVT().SimpleTy) {
1448 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_avar;
1451 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_avar;
1454 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_avar;
1457 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_avar;
1463 SDValue Ops[] = { Addr, Chain };
1464 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1465 } else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1466 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1468 switch (N->getOpcode()) {
1472 case ISD::INTRINSIC_W_CHAIN:
1474 switch (EltVT.getSimpleVT().SimpleTy) {
1478 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari64;
1481 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari64;
1484 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari64;
1487 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari64;
1490 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari64;
1493 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari64;
1497 switch (EltVT.getSimpleVT().SimpleTy) {
1501 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari64;
1504 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari64;
1507 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari64;
1510 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari64;
1513 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari64;
1516 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari64;
1521 case NVPTXISD::LoadV2:
1522 case NVPTXISD::LDGV2:
1523 switch (EltVT.getSimpleVT().SimpleTy) {
1527 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari64;
1530 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari64;
1533 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari64;
1536 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari64;
1539 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari64;
1542 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari64;
1546 case NVPTXISD::LDUV2:
1547 switch (EltVT.getSimpleVT().SimpleTy) {
1551 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari64;
1554 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari64;
1557 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari64;
1560 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari64;
1563 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari64;
1566 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari64;
1570 case NVPTXISD::LoadV4:
1571 case NVPTXISD::LDGV4:
1572 switch (EltVT.getSimpleVT().SimpleTy) {
1576 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari64;
1579 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari64;
1582 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari64;
1585 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari64;
1589 case NVPTXISD::LDUV4:
1590 switch (EltVT.getSimpleVT().SimpleTy) {
1594 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari64;
1597 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari64;
1600 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari64;
1603 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari64;
1609 switch (N->getOpcode()) {
1613 case ISD::INTRINSIC_W_CHAIN:
1615 switch (EltVT.getSimpleVT().SimpleTy) {
1619 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari;
1622 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari;
1625 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari;
1628 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari;
1631 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari;
1634 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari;
1638 switch (EltVT.getSimpleVT().SimpleTy) {
1642 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari;
1645 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari;
1648 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari;
1651 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari;
1654 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari;
1657 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari;
1662 case NVPTXISD::LoadV2:
1663 case NVPTXISD::LDGV2:
1664 switch (EltVT.getSimpleVT().SimpleTy) {
1668 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari32;
1671 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari32;
1674 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari32;
1677 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari32;
1680 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari32;
1683 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari32;
1687 case NVPTXISD::LDUV2:
1688 switch (EltVT.getSimpleVT().SimpleTy) {
1692 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari32;
1695 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari32;
1698 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari32;
1701 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari32;
1704 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari32;
1707 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari32;
1711 case NVPTXISD::LoadV4:
1712 case NVPTXISD::LDGV4:
1713 switch (EltVT.getSimpleVT().SimpleTy) {
1717 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari32;
1720 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari32;
1723 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari32;
1726 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari32;
1730 case NVPTXISD::LDUV4:
1731 switch (EltVT.getSimpleVT().SimpleTy) {
1735 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari32;
1738 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari32;
1741 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari32;
1744 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari32;
1751 SDValue Ops[] = { Base, Offset, Chain };
1753 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1756 switch (N->getOpcode()) {
1760 case ISD::INTRINSIC_W_CHAIN:
1762 switch (EltVT.getSimpleVT().SimpleTy) {
1766 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg64;
1769 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg64;
1772 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg64;
1775 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg64;
1778 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg64;
1781 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg64;
1785 switch (EltVT.getSimpleVT().SimpleTy) {
1789 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg64;
1792 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg64;
1795 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg64;
1798 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg64;
1801 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg64;
1804 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg64;
1809 case NVPTXISD::LoadV2:
1810 case NVPTXISD::LDGV2:
1811 switch (EltVT.getSimpleVT().SimpleTy) {
1815 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg64;
1818 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg64;
1821 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg64;
1824 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg64;
1827 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg64;
1830 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg64;
1834 case NVPTXISD::LDUV2:
1835 switch (EltVT.getSimpleVT().SimpleTy) {
1839 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg64;
1842 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg64;
1845 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg64;
1848 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg64;
1851 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg64;
1854 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg64;
1858 case NVPTXISD::LoadV4:
1859 case NVPTXISD::LDGV4:
1860 switch (EltVT.getSimpleVT().SimpleTy) {
1864 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64;
1867 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg64;
1870 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg64;
1873 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg64;
1877 case NVPTXISD::LDUV4:
1878 switch (EltVT.getSimpleVT().SimpleTy) {
1882 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64;
1885 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg64;
1888 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg64;
1891 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg64;
1897 switch (N->getOpcode()) {
1901 case ISD::INTRINSIC_W_CHAIN:
1903 switch (EltVT.getSimpleVT().SimpleTy) {
1907 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg;
1910 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg;
1913 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg;
1916 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg;
1919 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg;
1922 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg;
1926 switch (EltVT.getSimpleVT().SimpleTy) {
1930 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg;
1933 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg;
1936 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg;
1939 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg;
1942 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg;
1945 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg;
1950 case NVPTXISD::LoadV2:
1951 case NVPTXISD::LDGV2:
1952 switch (EltVT.getSimpleVT().SimpleTy) {
1956 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg32;
1959 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg32;
1962 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg32;
1965 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg32;
1968 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg32;
1971 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg32;
1975 case NVPTXISD::LDUV2:
1976 switch (EltVT.getSimpleVT().SimpleTy) {
1980 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg32;
1983 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg32;
1986 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg32;
1989 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg32;
1992 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg32;
1995 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg32;
1999 case NVPTXISD::LoadV4:
2000 case NVPTXISD::LDGV4:
2001 switch (EltVT.getSimpleVT().SimpleTy) {
2005 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32;
2008 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg32;
2011 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg32;
2014 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg32;
2018 case NVPTXISD::LDUV4:
2019 switch (EltVT.getSimpleVT().SimpleTy) {
2023 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32;
2026 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg32;
2029 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg32;
2032 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg32;
2039 SDValue Ops[] = { Op1, Chain };
2040 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
2043 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2044 MemRefs0[0] = Mem->getMemOperand();
2045 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
2050 SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
2052 StoreSDNode *ST = cast<StoreSDNode>(N);
2053 EVT StoreVT = ST->getMemoryVT();
2054 SDNode *NVPTXST = nullptr;
2056 // do not support pre/post inc/dec
2057 if (ST->isIndexed())
2060 if (!StoreVT.isSimple())
2063 // Address Space Setting
2064 unsigned int codeAddrSpace = getCodeAddrSpace(ST);
2067 // - .volatile is only availalble for .global and .shared
2068 bool isVolatile = ST->isVolatile();
2069 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
2070 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
2071 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
2075 MVT SimpleVT = StoreVT.getSimpleVT();
2076 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
2077 if (SimpleVT.isVector()) {
2078 unsigned num = SimpleVT.getVectorNumElements();
2080 vecType = NVPTX::PTXLdStInstCode::V2;
2082 vecType = NVPTX::PTXLdStInstCode::V4;
2087 // Type Setting: toType + toTypeWidth
2088 // - for integer type, always use 'u'
2090 MVT ScalarVT = SimpleVT.getScalarType();
2091 unsigned toTypeWidth = ScalarVT.getSizeInBits();
2092 unsigned int toType;
2093 if (ScalarVT.isFloatingPoint())
2094 toType = NVPTX::PTXLdStInstCode::Float;
2096 toType = NVPTX::PTXLdStInstCode::Unsigned;
2098 // Create the machine instruction DAG
2099 SDValue Chain = N->getOperand(0);
2100 SDValue N1 = N->getOperand(1);
2101 SDValue N2 = N->getOperand(2);
2103 SDValue Offset, Base;
2105 MVT::SimpleValueType SourceVT = N1.getNode()->getSimpleValueType(0).SimpleTy;
2107 if (SelectDirectAddr(N2, Addr)) {
2110 Opcode = NVPTX::ST_i8_avar;
2113 Opcode = NVPTX::ST_i16_avar;
2116 Opcode = NVPTX::ST_i32_avar;
2119 Opcode = NVPTX::ST_i64_avar;
2122 Opcode = NVPTX::ST_f32_avar;
2125 Opcode = NVPTX::ST_f64_avar;
2130 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2131 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2132 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Addr,
2134 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2135 } else if (TM.is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2136 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
2139 Opcode = NVPTX::ST_i8_asi;
2142 Opcode = NVPTX::ST_i16_asi;
2145 Opcode = NVPTX::ST_i32_asi;
2148 Opcode = NVPTX::ST_i64_asi;
2151 Opcode = NVPTX::ST_f32_asi;
2154 Opcode = NVPTX::ST_f64_asi;
2159 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2160 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2161 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Base,
2163 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2164 } else if (TM.is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2165 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
2169 Opcode = NVPTX::ST_i8_ari_64;
2172 Opcode = NVPTX::ST_i16_ari_64;
2175 Opcode = NVPTX::ST_i32_ari_64;
2178 Opcode = NVPTX::ST_i64_ari_64;
2181 Opcode = NVPTX::ST_f32_ari_64;
2184 Opcode = NVPTX::ST_f64_ari_64;
2192 Opcode = NVPTX::ST_i8_ari;
2195 Opcode = NVPTX::ST_i16_ari;
2198 Opcode = NVPTX::ST_i32_ari;
2201 Opcode = NVPTX::ST_i64_ari;
2204 Opcode = NVPTX::ST_f32_ari;
2207 Opcode = NVPTX::ST_f64_ari;
2213 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2214 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2215 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Base,
2217 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2222 Opcode = NVPTX::ST_i8_areg_64;
2225 Opcode = NVPTX::ST_i16_areg_64;
2228 Opcode = NVPTX::ST_i32_areg_64;
2231 Opcode = NVPTX::ST_i64_areg_64;
2234 Opcode = NVPTX::ST_f32_areg_64;
2237 Opcode = NVPTX::ST_f64_areg_64;
2245 Opcode = NVPTX::ST_i8_areg;
2248 Opcode = NVPTX::ST_i16_areg;
2251 Opcode = NVPTX::ST_i32_areg;
2254 Opcode = NVPTX::ST_i64_areg;
2257 Opcode = NVPTX::ST_f32_areg;
2260 Opcode = NVPTX::ST_f64_areg;
2266 SDValue Ops[] = { N1, getI32Imm(isVolatile, dl),
2267 getI32Imm(codeAddrSpace, dl), getI32Imm(vecType, dl),
2268 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), N2,
2270 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2274 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2275 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2276 cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2282 SDNode *NVPTXDAGToDAGISel::SelectStoreVector(SDNode *N) {
2283 SDValue Chain = N->getOperand(0);
2284 SDValue Op1 = N->getOperand(1);
2285 SDValue Addr, Offset, Base;
2289 EVT EltVT = Op1.getValueType();
2290 MemSDNode *MemSD = cast<MemSDNode>(N);
2291 EVT StoreVT = MemSD->getMemoryVT();
2293 // Address Space Setting
2294 unsigned CodeAddrSpace = getCodeAddrSpace(MemSD);
2296 if (CodeAddrSpace == NVPTX::PTXLdStInstCode::CONSTANT) {
2297 report_fatal_error("Cannot store to pointer that points to constant "
2302 // - .volatile is only availalble for .global and .shared
2303 bool IsVolatile = MemSD->isVolatile();
2304 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
2305 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
2306 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
2309 // Type Setting: toType + toTypeWidth
2310 // - for integer type, always use 'u'
2311 assert(StoreVT.isSimple() && "Store value is not simple");
2312 MVT ScalarVT = StoreVT.getSimpleVT().getScalarType();
2313 unsigned ToTypeWidth = ScalarVT.getSizeInBits();
2315 if (ScalarVT.isFloatingPoint())
2316 ToType = NVPTX::PTXLdStInstCode::Float;
2318 ToType = NVPTX::PTXLdStInstCode::Unsigned;
2320 SmallVector<SDValue, 12> StOps;
2324 switch (N->getOpcode()) {
2325 case NVPTXISD::StoreV2:
2326 VecType = NVPTX::PTXLdStInstCode::V2;
2327 StOps.push_back(N->getOperand(1));
2328 StOps.push_back(N->getOperand(2));
2329 N2 = N->getOperand(3);
2331 case NVPTXISD::StoreV4:
2332 VecType = NVPTX::PTXLdStInstCode::V4;
2333 StOps.push_back(N->getOperand(1));
2334 StOps.push_back(N->getOperand(2));
2335 StOps.push_back(N->getOperand(3));
2336 StOps.push_back(N->getOperand(4));
2337 N2 = N->getOperand(5);
2343 StOps.push_back(getI32Imm(IsVolatile, DL));
2344 StOps.push_back(getI32Imm(CodeAddrSpace, DL));
2345 StOps.push_back(getI32Imm(VecType, DL));
2346 StOps.push_back(getI32Imm(ToType, DL));
2347 StOps.push_back(getI32Imm(ToTypeWidth, DL));
2349 if (SelectDirectAddr(N2, Addr)) {
2350 switch (N->getOpcode()) {
2353 case NVPTXISD::StoreV2:
2354 switch (EltVT.getSimpleVT().SimpleTy) {
2358 Opcode = NVPTX::STV_i8_v2_avar;
2361 Opcode = NVPTX::STV_i16_v2_avar;
2364 Opcode = NVPTX::STV_i32_v2_avar;
2367 Opcode = NVPTX::STV_i64_v2_avar;
2370 Opcode = NVPTX::STV_f32_v2_avar;
2373 Opcode = NVPTX::STV_f64_v2_avar;
2377 case NVPTXISD::StoreV4:
2378 switch (EltVT.getSimpleVT().SimpleTy) {
2382 Opcode = NVPTX::STV_i8_v4_avar;
2385 Opcode = NVPTX::STV_i16_v4_avar;
2388 Opcode = NVPTX::STV_i32_v4_avar;
2391 Opcode = NVPTX::STV_f32_v4_avar;
2396 StOps.push_back(Addr);
2397 } else if (TM.is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2398 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
2399 switch (N->getOpcode()) {
2402 case NVPTXISD::StoreV2:
2403 switch (EltVT.getSimpleVT().SimpleTy) {
2407 Opcode = NVPTX::STV_i8_v2_asi;
2410 Opcode = NVPTX::STV_i16_v2_asi;
2413 Opcode = NVPTX::STV_i32_v2_asi;
2416 Opcode = NVPTX::STV_i64_v2_asi;
2419 Opcode = NVPTX::STV_f32_v2_asi;
2422 Opcode = NVPTX::STV_f64_v2_asi;
2426 case NVPTXISD::StoreV4:
2427 switch (EltVT.getSimpleVT().SimpleTy) {
2431 Opcode = NVPTX::STV_i8_v4_asi;
2434 Opcode = NVPTX::STV_i16_v4_asi;
2437 Opcode = NVPTX::STV_i32_v4_asi;
2440 Opcode = NVPTX::STV_f32_v4_asi;
2445 StOps.push_back(Base);
2446 StOps.push_back(Offset);
2447 } else if (TM.is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2448 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
2450 switch (N->getOpcode()) {
2453 case NVPTXISD::StoreV2:
2454 switch (EltVT.getSimpleVT().SimpleTy) {
2458 Opcode = NVPTX::STV_i8_v2_ari_64;
2461 Opcode = NVPTX::STV_i16_v2_ari_64;
2464 Opcode = NVPTX::STV_i32_v2_ari_64;
2467 Opcode = NVPTX::STV_i64_v2_ari_64;
2470 Opcode = NVPTX::STV_f32_v2_ari_64;
2473 Opcode = NVPTX::STV_f64_v2_ari_64;
2477 case NVPTXISD::StoreV4:
2478 switch (EltVT.getSimpleVT().SimpleTy) {
2482 Opcode = NVPTX::STV_i8_v4_ari_64;
2485 Opcode = NVPTX::STV_i16_v4_ari_64;
2488 Opcode = NVPTX::STV_i32_v4_ari_64;
2491 Opcode = NVPTX::STV_f32_v4_ari_64;
2497 switch (N->getOpcode()) {
2500 case NVPTXISD::StoreV2:
2501 switch (EltVT.getSimpleVT().SimpleTy) {
2505 Opcode = NVPTX::STV_i8_v2_ari;
2508 Opcode = NVPTX::STV_i16_v2_ari;
2511 Opcode = NVPTX::STV_i32_v2_ari;
2514 Opcode = NVPTX::STV_i64_v2_ari;
2517 Opcode = NVPTX::STV_f32_v2_ari;
2520 Opcode = NVPTX::STV_f64_v2_ari;
2524 case NVPTXISD::StoreV4:
2525 switch (EltVT.getSimpleVT().SimpleTy) {
2529 Opcode = NVPTX::STV_i8_v4_ari;
2532 Opcode = NVPTX::STV_i16_v4_ari;
2535 Opcode = NVPTX::STV_i32_v4_ari;
2538 Opcode = NVPTX::STV_f32_v4_ari;
2544 StOps.push_back(Base);
2545 StOps.push_back(Offset);
2548 switch (N->getOpcode()) {
2551 case NVPTXISD::StoreV2:
2552 switch (EltVT.getSimpleVT().SimpleTy) {
2556 Opcode = NVPTX::STV_i8_v2_areg_64;
2559 Opcode = NVPTX::STV_i16_v2_areg_64;
2562 Opcode = NVPTX::STV_i32_v2_areg_64;
2565 Opcode = NVPTX::STV_i64_v2_areg_64;
2568 Opcode = NVPTX::STV_f32_v2_areg_64;
2571 Opcode = NVPTX::STV_f64_v2_areg_64;
2575 case NVPTXISD::StoreV4:
2576 switch (EltVT.getSimpleVT().SimpleTy) {
2580 Opcode = NVPTX::STV_i8_v4_areg_64;
2583 Opcode = NVPTX::STV_i16_v4_areg_64;
2586 Opcode = NVPTX::STV_i32_v4_areg_64;
2589 Opcode = NVPTX::STV_f32_v4_areg_64;
2595 switch (N->getOpcode()) {
2598 case NVPTXISD::StoreV2:
2599 switch (EltVT.getSimpleVT().SimpleTy) {
2603 Opcode = NVPTX::STV_i8_v2_areg;
2606 Opcode = NVPTX::STV_i16_v2_areg;
2609 Opcode = NVPTX::STV_i32_v2_areg;
2612 Opcode = NVPTX::STV_i64_v2_areg;
2615 Opcode = NVPTX::STV_f32_v2_areg;
2618 Opcode = NVPTX::STV_f64_v2_areg;
2622 case NVPTXISD::StoreV4:
2623 switch (EltVT.getSimpleVT().SimpleTy) {
2627 Opcode = NVPTX::STV_i8_v4_areg;
2630 Opcode = NVPTX::STV_i16_v4_areg;
2633 Opcode = NVPTX::STV_i32_v4_areg;
2636 Opcode = NVPTX::STV_f32_v4_areg;
2642 StOps.push_back(N2);
2645 StOps.push_back(Chain);
2647 ST = CurDAG->getMachineNode(Opcode, DL, MVT::Other, StOps);
2649 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2650 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2651 cast<MachineSDNode>(ST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2656 SDNode *NVPTXDAGToDAGISel::SelectLoadParam(SDNode *Node) {
2657 SDValue Chain = Node->getOperand(0);
2658 SDValue Offset = Node->getOperand(2);
2659 SDValue Flag = Node->getOperand(3);
2661 MemSDNode *Mem = cast<MemSDNode>(Node);
2664 switch (Node->getOpcode()) {
2667 case NVPTXISD::LoadParam:
2670 case NVPTXISD::LoadParamV2:
2673 case NVPTXISD::LoadParamV4:
2678 EVT EltVT = Node->getValueType(0);
2679 EVT MemVT = Mem->getMemoryVT();
2687 switch (MemVT.getSimpleVT().SimpleTy) {
2691 Opc = NVPTX::LoadParamMemI8;
2694 Opc = NVPTX::LoadParamMemI8;
2697 Opc = NVPTX::LoadParamMemI16;
2700 Opc = NVPTX::LoadParamMemI32;
2703 Opc = NVPTX::LoadParamMemI64;
2706 Opc = NVPTX::LoadParamMemF32;
2709 Opc = NVPTX::LoadParamMemF64;
2714 switch (MemVT.getSimpleVT().SimpleTy) {
2718 Opc = NVPTX::LoadParamMemV2I8;
2721 Opc = NVPTX::LoadParamMemV2I8;
2724 Opc = NVPTX::LoadParamMemV2I16;
2727 Opc = NVPTX::LoadParamMemV2I32;
2730 Opc = NVPTX::LoadParamMemV2I64;
2733 Opc = NVPTX::LoadParamMemV2F32;
2736 Opc = NVPTX::LoadParamMemV2F64;
2741 switch (MemVT.getSimpleVT().SimpleTy) {
2745 Opc = NVPTX::LoadParamMemV4I8;
2748 Opc = NVPTX::LoadParamMemV4I8;
2751 Opc = NVPTX::LoadParamMemV4I16;
2754 Opc = NVPTX::LoadParamMemV4I32;
2757 Opc = NVPTX::LoadParamMemV4F32;
2765 VTs = CurDAG->getVTList(EltVT, MVT::Other, MVT::Glue);
2766 } else if (VecSize == 2) {
2767 VTs = CurDAG->getVTList(EltVT, EltVT, MVT::Other, MVT::Glue);
2769 EVT EVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other, MVT::Glue };
2770 VTs = CurDAG->getVTList(EVTs);
2773 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2775 SmallVector<SDValue, 2> Ops;
2776 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
2777 Ops.push_back(Chain);
2778 Ops.push_back(Flag);
2780 return CurDAG->getMachineNode(Opc, DL, VTs, Ops);
2783 SDNode *NVPTXDAGToDAGISel::SelectStoreRetval(SDNode *N) {
2785 SDValue Chain = N->getOperand(0);
2786 SDValue Offset = N->getOperand(1);
2787 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2788 MemSDNode *Mem = cast<MemSDNode>(N);
2790 // How many elements do we have?
2791 unsigned NumElts = 1;
2792 switch (N->getOpcode()) {
2795 case NVPTXISD::StoreRetval:
2798 case NVPTXISD::StoreRetvalV2:
2801 case NVPTXISD::StoreRetvalV4:
2806 // Build vector of operands
2807 SmallVector<SDValue, 6> Ops;
2808 for (unsigned i = 0; i < NumElts; ++i)
2809 Ops.push_back(N->getOperand(i + 2));
2810 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
2811 Ops.push_back(Chain);
2813 // Determine target opcode
2814 // If we have an i1, use an 8-bit store. The lowering code in
2815 // NVPTXISelLowering will have already emitted an upcast.
2816 unsigned Opcode = 0;
2821 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2825 Opcode = NVPTX::StoreRetvalI8;
2828 Opcode = NVPTX::StoreRetvalI8;
2831 Opcode = NVPTX::StoreRetvalI16;
2834 Opcode = NVPTX::StoreRetvalI32;
2837 Opcode = NVPTX::StoreRetvalI64;
2840 Opcode = NVPTX::StoreRetvalF32;
2843 Opcode = NVPTX::StoreRetvalF64;
2848 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2852 Opcode = NVPTX::StoreRetvalV2I8;
2855 Opcode = NVPTX::StoreRetvalV2I8;
2858 Opcode = NVPTX::StoreRetvalV2I16;
2861 Opcode = NVPTX::StoreRetvalV2I32;
2864 Opcode = NVPTX::StoreRetvalV2I64;
2867 Opcode = NVPTX::StoreRetvalV2F32;
2870 Opcode = NVPTX::StoreRetvalV2F64;
2875 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2879 Opcode = NVPTX::StoreRetvalV4I8;
2882 Opcode = NVPTX::StoreRetvalV4I8;
2885 Opcode = NVPTX::StoreRetvalV4I16;
2888 Opcode = NVPTX::StoreRetvalV4I32;
2891 Opcode = NVPTX::StoreRetvalV4F32;
2898 CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
2899 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2900 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2901 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
2906 SDNode *NVPTXDAGToDAGISel::SelectStoreParam(SDNode *N) {
2908 SDValue Chain = N->getOperand(0);
2909 SDValue Param = N->getOperand(1);
2910 unsigned ParamVal = cast<ConstantSDNode>(Param)->getZExtValue();
2911 SDValue Offset = N->getOperand(2);
2912 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2913 MemSDNode *Mem = cast<MemSDNode>(N);
2914 SDValue Flag = N->getOperand(N->getNumOperands() - 1);
2916 // How many elements do we have?
2917 unsigned NumElts = 1;
2918 switch (N->getOpcode()) {
2921 case NVPTXISD::StoreParamU32:
2922 case NVPTXISD::StoreParamS32:
2923 case NVPTXISD::StoreParam:
2926 case NVPTXISD::StoreParamV2:
2929 case NVPTXISD::StoreParamV4:
2934 // Build vector of operands
2935 SmallVector<SDValue, 8> Ops;
2936 for (unsigned i = 0; i < NumElts; ++i)
2937 Ops.push_back(N->getOperand(i + 3));
2938 Ops.push_back(CurDAG->getTargetConstant(ParamVal, DL, MVT::i32));
2939 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
2940 Ops.push_back(Chain);
2941 Ops.push_back(Flag);
2943 // Determine target opcode
2944 // If we have an i1, use an 8-bit store. The lowering code in
2945 // NVPTXISelLowering will have already emitted an upcast.
2946 unsigned Opcode = 0;
2947 switch (N->getOpcode()) {
2953 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2957 Opcode = NVPTX::StoreParamI8;
2960 Opcode = NVPTX::StoreParamI8;
2963 Opcode = NVPTX::StoreParamI16;
2966 Opcode = NVPTX::StoreParamI32;
2969 Opcode = NVPTX::StoreParamI64;
2972 Opcode = NVPTX::StoreParamF32;
2975 Opcode = NVPTX::StoreParamF64;
2980 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2984 Opcode = NVPTX::StoreParamV2I8;
2987 Opcode = NVPTX::StoreParamV2I8;
2990 Opcode = NVPTX::StoreParamV2I16;
2993 Opcode = NVPTX::StoreParamV2I32;
2996 Opcode = NVPTX::StoreParamV2I64;
2999 Opcode = NVPTX::StoreParamV2F32;
3002 Opcode = NVPTX::StoreParamV2F64;
3007 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
3011 Opcode = NVPTX::StoreParamV4I8;
3014 Opcode = NVPTX::StoreParamV4I8;
3017 Opcode = NVPTX::StoreParamV4I16;
3020 Opcode = NVPTX::StoreParamV4I32;
3023 Opcode = NVPTX::StoreParamV4F32;
3029 // Special case: if we have a sign-extend/zero-extend node, insert the
3030 // conversion instruction first, and use that as the value operand to
3031 // the selected StoreParam node.
3032 case NVPTXISD::StoreParamU32: {
3033 Opcode = NVPTX::StoreParamI32;
3034 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE, DL,
3036 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL,
3037 MVT::i32, Ops[0], CvtNone);
3038 Ops[0] = SDValue(Cvt, 0);
3041 case NVPTXISD::StoreParamS32: {
3042 Opcode = NVPTX::StoreParamI32;
3043 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE, DL,
3045 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL,
3046 MVT::i32, Ops[0], CvtNone);
3047 Ops[0] = SDValue(Cvt, 0);
3052 SDVTList RetVTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
3054 CurDAG->getMachineNode(Opcode, DL, RetVTs, Ops);
3055 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
3056 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
3057 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
3062 SDNode *NVPTXDAGToDAGISel::SelectTextureIntrinsic(SDNode *N) {
3063 SDValue Chain = N->getOperand(0);
3064 SDNode *Ret = nullptr;
3066 SmallVector<SDValue, 8> Ops;
3068 switch (N->getOpcode()) {
3069 default: return nullptr;
3070 case NVPTXISD::Tex1DFloatS32:
3071 Opc = NVPTX::TEX_1D_F32_S32;
3073 case NVPTXISD::Tex1DFloatFloat:
3074 Opc = NVPTX::TEX_1D_F32_F32;
3076 case NVPTXISD::Tex1DFloatFloatLevel:
3077 Opc = NVPTX::TEX_1D_F32_F32_LEVEL;
3079 case NVPTXISD::Tex1DFloatFloatGrad:
3080 Opc = NVPTX::TEX_1D_F32_F32_GRAD;
3082 case NVPTXISD::Tex1DS32S32:
3083 Opc = NVPTX::TEX_1D_S32_S32;
3085 case NVPTXISD::Tex1DS32Float:
3086 Opc = NVPTX::TEX_1D_S32_F32;
3088 case NVPTXISD::Tex1DS32FloatLevel:
3089 Opc = NVPTX::TEX_1D_S32_F32_LEVEL;
3091 case NVPTXISD::Tex1DS32FloatGrad:
3092 Opc = NVPTX::TEX_1D_S32_F32_GRAD;
3094 case NVPTXISD::Tex1DU32S32:
3095 Opc = NVPTX::TEX_1D_U32_S32;
3097 case NVPTXISD::Tex1DU32Float:
3098 Opc = NVPTX::TEX_1D_U32_F32;
3100 case NVPTXISD::Tex1DU32FloatLevel:
3101 Opc = NVPTX::TEX_1D_U32_F32_LEVEL;
3103 case NVPTXISD::Tex1DU32FloatGrad:
3104 Opc = NVPTX::TEX_1D_U32_F32_GRAD;
3106 case NVPTXISD::Tex1DArrayFloatS32:
3107 Opc = NVPTX::TEX_1D_ARRAY_F32_S32;
3109 case NVPTXISD::Tex1DArrayFloatFloat:
3110 Opc = NVPTX::TEX_1D_ARRAY_F32_F32;
3112 case NVPTXISD::Tex1DArrayFloatFloatLevel:
3113 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL;
3115 case NVPTXISD::Tex1DArrayFloatFloatGrad:
3116 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_GRAD;
3118 case NVPTXISD::Tex1DArrayS32S32:
3119 Opc = NVPTX::TEX_1D_ARRAY_S32_S32;
3121 case NVPTXISD::Tex1DArrayS32Float:
3122 Opc = NVPTX::TEX_1D_ARRAY_S32_F32;
3124 case NVPTXISD::Tex1DArrayS32FloatLevel:
3125 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL;
3127 case NVPTXISD::Tex1DArrayS32FloatGrad:
3128 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_GRAD;
3130 case NVPTXISD::Tex1DArrayU32S32:
3131 Opc = NVPTX::TEX_1D_ARRAY_U32_S32;
3133 case NVPTXISD::Tex1DArrayU32Float:
3134 Opc = NVPTX::TEX_1D_ARRAY_U32_F32;
3136 case NVPTXISD::Tex1DArrayU32FloatLevel:
3137 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL;
3139 case NVPTXISD::Tex1DArrayU32FloatGrad:
3140 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_GRAD;
3142 case NVPTXISD::Tex2DFloatS32:
3143 Opc = NVPTX::TEX_2D_F32_S32;
3145 case NVPTXISD::Tex2DFloatFloat:
3146 Opc = NVPTX::TEX_2D_F32_F32;
3148 case NVPTXISD::Tex2DFloatFloatLevel:
3149 Opc = NVPTX::TEX_2D_F32_F32_LEVEL;
3151 case NVPTXISD::Tex2DFloatFloatGrad:
3152 Opc = NVPTX::TEX_2D_F32_F32_GRAD;
3154 case NVPTXISD::Tex2DS32S32:
3155 Opc = NVPTX::TEX_2D_S32_S32;
3157 case NVPTXISD::Tex2DS32Float:
3158 Opc = NVPTX::TEX_2D_S32_F32;
3160 case NVPTXISD::Tex2DS32FloatLevel:
3161 Opc = NVPTX::TEX_2D_S32_F32_LEVEL;
3163 case NVPTXISD::Tex2DS32FloatGrad:
3164 Opc = NVPTX::TEX_2D_S32_F32_GRAD;
3166 case NVPTXISD::Tex2DU32S32:
3167 Opc = NVPTX::TEX_2D_U32_S32;
3169 case NVPTXISD::Tex2DU32Float:
3170 Opc = NVPTX::TEX_2D_U32_F32;
3172 case NVPTXISD::Tex2DU32FloatLevel:
3173 Opc = NVPTX::TEX_2D_U32_F32_LEVEL;
3175 case NVPTXISD::Tex2DU32FloatGrad:
3176 Opc = NVPTX::TEX_2D_U32_F32_GRAD;
3178 case NVPTXISD::Tex2DArrayFloatS32:
3179 Opc = NVPTX::TEX_2D_ARRAY_F32_S32;
3181 case NVPTXISD::Tex2DArrayFloatFloat:
3182 Opc = NVPTX::TEX_2D_ARRAY_F32_F32;
3184 case NVPTXISD::Tex2DArrayFloatFloatLevel:
3185 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL;
3187 case NVPTXISD::Tex2DArrayFloatFloatGrad:
3188 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_GRAD;
3190 case NVPTXISD::Tex2DArrayS32S32:
3191 Opc = NVPTX::TEX_2D_ARRAY_S32_S32;
3193 case NVPTXISD::Tex2DArrayS32Float:
3194 Opc = NVPTX::TEX_2D_ARRAY_S32_F32;
3196 case NVPTXISD::Tex2DArrayS32FloatLevel:
3197 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL;
3199 case NVPTXISD::Tex2DArrayS32FloatGrad:
3200 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_GRAD;
3202 case NVPTXISD::Tex2DArrayU32S32:
3203 Opc = NVPTX::TEX_2D_ARRAY_U32_S32;
3205 case NVPTXISD::Tex2DArrayU32Float:
3206 Opc = NVPTX::TEX_2D_ARRAY_U32_F32;
3208 case NVPTXISD::Tex2DArrayU32FloatLevel:
3209 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL;
3211 case NVPTXISD::Tex2DArrayU32FloatGrad:
3212 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_GRAD;
3214 case NVPTXISD::Tex3DFloatS32:
3215 Opc = NVPTX::TEX_3D_F32_S32;
3217 case NVPTXISD::Tex3DFloatFloat:
3218 Opc = NVPTX::TEX_3D_F32_F32;
3220 case NVPTXISD::Tex3DFloatFloatLevel:
3221 Opc = NVPTX::TEX_3D_F32_F32_LEVEL;
3223 case NVPTXISD::Tex3DFloatFloatGrad:
3224 Opc = NVPTX::TEX_3D_F32_F32_GRAD;
3226 case NVPTXISD::Tex3DS32S32:
3227 Opc = NVPTX::TEX_3D_S32_S32;
3229 case NVPTXISD::Tex3DS32Float:
3230 Opc = NVPTX::TEX_3D_S32_F32;
3232 case NVPTXISD::Tex3DS32FloatLevel:
3233 Opc = NVPTX::TEX_3D_S32_F32_LEVEL;
3235 case NVPTXISD::Tex3DS32FloatGrad:
3236 Opc = NVPTX::TEX_3D_S32_F32_GRAD;
3238 case NVPTXISD::Tex3DU32S32:
3239 Opc = NVPTX::TEX_3D_U32_S32;
3241 case NVPTXISD::Tex3DU32Float:
3242 Opc = NVPTX::TEX_3D_U32_F32;
3244 case NVPTXISD::Tex3DU32FloatLevel:
3245 Opc = NVPTX::TEX_3D_U32_F32_LEVEL;
3247 case NVPTXISD::Tex3DU32FloatGrad:
3248 Opc = NVPTX::TEX_3D_U32_F32_GRAD;
3250 case NVPTXISD::TexCubeFloatFloat:
3251 Opc = NVPTX::TEX_CUBE_F32_F32;
3253 case NVPTXISD::TexCubeFloatFloatLevel:
3254 Opc = NVPTX::TEX_CUBE_F32_F32_LEVEL;
3256 case NVPTXISD::TexCubeS32Float:
3257 Opc = NVPTX::TEX_CUBE_S32_F32;
3259 case NVPTXISD::TexCubeS32FloatLevel:
3260 Opc = NVPTX::TEX_CUBE_S32_F32_LEVEL;
3262 case NVPTXISD::TexCubeU32Float:
3263 Opc = NVPTX::TEX_CUBE_U32_F32;
3265 case NVPTXISD::TexCubeU32FloatLevel:
3266 Opc = NVPTX::TEX_CUBE_U32_F32_LEVEL;
3268 case NVPTXISD::TexCubeArrayFloatFloat:
3269 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32;
3271 case NVPTXISD::TexCubeArrayFloatFloatLevel:
3272 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL;
3274 case NVPTXISD::TexCubeArrayS32Float:
3275 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32;
3277 case NVPTXISD::TexCubeArrayS32FloatLevel:
3278 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL;
3280 case NVPTXISD::TexCubeArrayU32Float:
3281 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32;
3283 case NVPTXISD::TexCubeArrayU32FloatLevel:
3284 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL;
3286 case NVPTXISD::Tld4R2DFloatFloat:
3287 Opc = NVPTX::TLD4_R_2D_F32_F32;
3289 case NVPTXISD::Tld4G2DFloatFloat:
3290 Opc = NVPTX::TLD4_G_2D_F32_F32;
3292 case NVPTXISD::Tld4B2DFloatFloat:
3293 Opc = NVPTX::TLD4_B_2D_F32_F32;
3295 case NVPTXISD::Tld4A2DFloatFloat:
3296 Opc = NVPTX::TLD4_A_2D_F32_F32;
3298 case NVPTXISD::Tld4R2DS64Float:
3299 Opc = NVPTX::TLD4_R_2D_S32_F32;
3301 case NVPTXISD::Tld4G2DS64Float:
3302 Opc = NVPTX::TLD4_G_2D_S32_F32;
3304 case NVPTXISD::Tld4B2DS64Float:
3305 Opc = NVPTX::TLD4_B_2D_S32_F32;
3307 case NVPTXISD::Tld4A2DS64Float:
3308 Opc = NVPTX::TLD4_A_2D_S32_F32;
3310 case NVPTXISD::Tld4R2DU64Float:
3311 Opc = NVPTX::TLD4_R_2D_U32_F32;
3313 case NVPTXISD::Tld4G2DU64Float:
3314 Opc = NVPTX::TLD4_G_2D_U32_F32;
3316 case NVPTXISD::Tld4B2DU64Float:
3317 Opc = NVPTX::TLD4_B_2D_U32_F32;
3319 case NVPTXISD::Tld4A2DU64Float:
3320 Opc = NVPTX::TLD4_A_2D_U32_F32;
3322 case NVPTXISD::TexUnified1DFloatS32:
3323 Opc = NVPTX::TEX_UNIFIED_1D_F32_S32;
3325 case NVPTXISD::TexUnified1DFloatFloat:
3326 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32;
3328 case NVPTXISD::TexUnified1DFloatFloatLevel:
3329 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_LEVEL;
3331 case NVPTXISD::TexUnified1DFloatFloatGrad:
3332 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_GRAD;
3334 case NVPTXISD::TexUnified1DS32S32:
3335 Opc = NVPTX::TEX_UNIFIED_1D_S32_S32;
3337 case NVPTXISD::TexUnified1DS32Float:
3338 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32;
3340 case NVPTXISD::TexUnified1DS32FloatLevel:
3341 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_LEVEL;
3343 case NVPTXISD::TexUnified1DS32FloatGrad:
3344 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_GRAD;
3346 case NVPTXISD::TexUnified1DU32S32:
3347 Opc = NVPTX::TEX_UNIFIED_1D_U32_S32;
3349 case NVPTXISD::TexUnified1DU32Float:
3350 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32;
3352 case NVPTXISD::TexUnified1DU32FloatLevel:
3353 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_LEVEL;
3355 case NVPTXISD::TexUnified1DU32FloatGrad:
3356 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_GRAD;
3358 case NVPTXISD::TexUnified1DArrayFloatS32:
3359 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_S32;
3361 case NVPTXISD::TexUnified1DArrayFloatFloat:
3362 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32;
3364 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
3365 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL;
3367 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
3368 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD;
3370 case NVPTXISD::TexUnified1DArrayS32S32:
3371 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_S32;
3373 case NVPTXISD::TexUnified1DArrayS32Float:
3374 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32;
3376 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
3377 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL;
3379 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
3380 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD;
3382 case NVPTXISD::TexUnified1DArrayU32S32:
3383 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_S32;
3385 case NVPTXISD::TexUnified1DArrayU32Float:
3386 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32;
3388 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
3389 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL;
3391 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
3392 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD;
3394 case NVPTXISD::TexUnified2DFloatS32:
3395 Opc = NVPTX::TEX_UNIFIED_2D_F32_S32;
3397 case NVPTXISD::TexUnified2DFloatFloat:
3398 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32;
3400 case NVPTXISD::TexUnified2DFloatFloatLevel:
3401 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_LEVEL;
3403 case NVPTXISD::TexUnified2DFloatFloatGrad:
3404 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_GRAD;
3406 case NVPTXISD::TexUnified2DS32S32:
3407 Opc = NVPTX::TEX_UNIFIED_2D_S32_S32;
3409 case NVPTXISD::TexUnified2DS32Float:
3410 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32;
3412 case NVPTXISD::TexUnified2DS32FloatLevel:
3413 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_LEVEL;
3415 case NVPTXISD::TexUnified2DS32FloatGrad:
3416 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_GRAD;
3418 case NVPTXISD::TexUnified2DU32S32:
3419 Opc = NVPTX::TEX_UNIFIED_2D_U32_S32;
3421 case NVPTXISD::TexUnified2DU32Float:
3422 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32;
3424 case NVPTXISD::TexUnified2DU32FloatLevel:
3425 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_LEVEL;
3427 case NVPTXISD::TexUnified2DU32FloatGrad:
3428 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_GRAD;
3430 case NVPTXISD::TexUnified2DArrayFloatS32:
3431 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_S32;
3433 case NVPTXISD::TexUnified2DArrayFloatFloat:
3434 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32;
3436 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
3437 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL;
3439 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
3440 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD;
3442 case NVPTXISD::TexUnified2DArrayS32S32:
3443 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_S32;
3445 case NVPTXISD::TexUnified2DArrayS32Float:
3446 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32;
3448 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
3449 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL;
3451 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
3452 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD;
3454 case NVPTXISD::TexUnified2DArrayU32S32:
3455 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_S32;
3457 case NVPTXISD::TexUnified2DArrayU32Float:
3458 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32;
3460 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
3461 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL;
3463 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
3464 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD;
3466 case NVPTXISD::TexUnified3DFloatS32:
3467 Opc = NVPTX::TEX_UNIFIED_3D_F32_S32;
3469 case NVPTXISD::TexUnified3DFloatFloat:
3470 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32;
3472 case NVPTXISD::TexUnified3DFloatFloatLevel:
3473 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_LEVEL;
3475 case NVPTXISD::TexUnified3DFloatFloatGrad:
3476 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_GRAD;
3478 case NVPTXISD::TexUnified3DS32S32:
3479 Opc = NVPTX::TEX_UNIFIED_3D_S32_S32;
3481 case NVPTXISD::TexUnified3DS32Float:
3482 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32;
3484 case NVPTXISD::TexUnified3DS32FloatLevel:
3485 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_LEVEL;
3487 case NVPTXISD::TexUnified3DS32FloatGrad:
3488 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_GRAD;
3490 case NVPTXISD::TexUnified3DU32S32:
3491 Opc = NVPTX::TEX_UNIFIED_3D_U32_S32;
3493 case NVPTXISD::TexUnified3DU32Float:
3494 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32;
3496 case NVPTXISD::TexUnified3DU32FloatLevel:
3497 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_LEVEL;
3499 case NVPTXISD::TexUnified3DU32FloatGrad:
3500 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_GRAD;
3502 case NVPTXISD::TexUnifiedCubeFloatFloat:
3503 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32;
3505 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
3506 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32_LEVEL;
3508 case NVPTXISD::TexUnifiedCubeS32Float:
3509 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32;
3511 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
3512 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32_LEVEL;
3514 case NVPTXISD::TexUnifiedCubeU32Float:
3515 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32;
3517 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
3518 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32_LEVEL;
3520 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
3521 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32;
3523 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
3524 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL;
3526 case NVPTXISD::TexUnifiedCubeArrayS32Float:
3527 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32;
3529 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
3530 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL;
3532 case NVPTXISD::TexUnifiedCubeArrayU32Float:
3533 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32;
3535 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
3536 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL;
3538 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
3539 Opc = NVPTX::TLD4_UNIFIED_R_2D_F32_F32;
3541 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
3542 Opc = NVPTX::TLD4_UNIFIED_G_2D_F32_F32;
3544 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
3545 Opc = NVPTX::TLD4_UNIFIED_B_2D_F32_F32;
3547 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
3548 Opc = NVPTX::TLD4_UNIFIED_A_2D_F32_F32;
3550 case NVPTXISD::Tld4UnifiedR2DS64Float:
3551 Opc = NVPTX::TLD4_UNIFIED_R_2D_S32_F32;
3553 case NVPTXISD::Tld4UnifiedG2DS64Float:
3554 Opc = NVPTX::TLD4_UNIFIED_G_2D_S32_F32;
3556 case NVPTXISD::Tld4UnifiedB2DS64Float:
3557 Opc = NVPTX::TLD4_UNIFIED_B_2D_S32_F32;
3559 case NVPTXISD::Tld4UnifiedA2DS64Float:
3560 Opc = NVPTX::TLD4_UNIFIED_A_2D_S32_F32;
3562 case NVPTXISD::Tld4UnifiedR2DU64Float:
3563 Opc = NVPTX::TLD4_UNIFIED_R_2D_U32_F32;
3565 case NVPTXISD::Tld4UnifiedG2DU64Float:
3566 Opc = NVPTX::TLD4_UNIFIED_G_2D_U32_F32;
3568 case NVPTXISD::Tld4UnifiedB2DU64Float:
3569 Opc = NVPTX::TLD4_UNIFIED_B_2D_U32_F32;
3571 case NVPTXISD::Tld4UnifiedA2DU64Float:
3572 Opc = NVPTX::TLD4_UNIFIED_A_2D_U32_F32;
3576 // Copy over operands
3577 for (unsigned i = 1; i < N->getNumOperands(); ++i) {
3578 Ops.push_back(N->getOperand(i));
3581 Ops.push_back(Chain);
3582 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
3586 SDNode *NVPTXDAGToDAGISel::SelectSurfaceIntrinsic(SDNode *N) {
3587 SDValue Chain = N->getOperand(0);
3588 SDValue TexHandle = N->getOperand(1);
3589 SDNode *Ret = nullptr;
3591 SmallVector<SDValue, 8> Ops;
3592 switch (N->getOpcode()) {
3593 default: return nullptr;
3594 case NVPTXISD::Suld1DI8Clamp:
3595 Opc = NVPTX::SULD_1D_I8_CLAMP;
3596 Ops.push_back(TexHandle);
3597 Ops.push_back(N->getOperand(2));
3598 Ops.push_back(Chain);
3600 case NVPTXISD::Suld1DI16Clamp:
3601 Opc = NVPTX::SULD_1D_I16_CLAMP;
3602 Ops.push_back(TexHandle);
3603 Ops.push_back(N->getOperand(2));
3604 Ops.push_back(Chain);
3606 case NVPTXISD::Suld1DI32Clamp:
3607 Opc = NVPTX::SULD_1D_I32_CLAMP;
3608 Ops.push_back(TexHandle);
3609 Ops.push_back(N->getOperand(2));
3610 Ops.push_back(Chain);
3612 case NVPTXISD::Suld1DI64Clamp:
3613 Opc = NVPTX::SULD_1D_I64_CLAMP;
3614 Ops.push_back(TexHandle);
3615 Ops.push_back(N->getOperand(2));
3616 Ops.push_back(Chain);
3618 case NVPTXISD::Suld1DV2I8Clamp:
3619 Opc = NVPTX::SULD_1D_V2I8_CLAMP;
3620 Ops.push_back(TexHandle);
3621 Ops.push_back(N->getOperand(2));
3622 Ops.push_back(Chain);
3624 case NVPTXISD::Suld1DV2I16Clamp:
3625 Opc = NVPTX::SULD_1D_V2I16_CLAMP;
3626 Ops.push_back(TexHandle);
3627 Ops.push_back(N->getOperand(2));
3628 Ops.push_back(Chain);
3630 case NVPTXISD::Suld1DV2I32Clamp:
3631 Opc = NVPTX::SULD_1D_V2I32_CLAMP;
3632 Ops.push_back(TexHandle);
3633 Ops.push_back(N->getOperand(2));
3634 Ops.push_back(Chain);
3636 case NVPTXISD::Suld1DV2I64Clamp:
3637 Opc = NVPTX::SULD_1D_V2I64_CLAMP;
3638 Ops.push_back(TexHandle);
3639 Ops.push_back(N->getOperand(2));
3640 Ops.push_back(Chain);
3642 case NVPTXISD::Suld1DV4I8Clamp:
3643 Opc = NVPTX::SULD_1D_V4I8_CLAMP;
3644 Ops.push_back(TexHandle);
3645 Ops.push_back(N->getOperand(2));
3646 Ops.push_back(Chain);
3648 case NVPTXISD::Suld1DV4I16Clamp:
3649 Opc = NVPTX::SULD_1D_V4I16_CLAMP;
3650 Ops.push_back(TexHandle);
3651 Ops.push_back(N->getOperand(2));
3652 Ops.push_back(Chain);
3654 case NVPTXISD::Suld1DV4I32Clamp:
3655 Opc = NVPTX::SULD_1D_V4I32_CLAMP;
3656 Ops.push_back(TexHandle);
3657 Ops.push_back(N->getOperand(2));
3658 Ops.push_back(Chain);
3660 case NVPTXISD::Suld1DArrayI8Clamp:
3661 Opc = NVPTX::SULD_1D_ARRAY_I8_CLAMP;
3662 Ops.push_back(TexHandle);
3663 Ops.push_back(N->getOperand(2));
3664 Ops.push_back(N->getOperand(3));
3665 Ops.push_back(Chain);
3667 case NVPTXISD::Suld1DArrayI16Clamp:
3668 Opc = NVPTX::SULD_1D_ARRAY_I16_CLAMP;
3669 Ops.push_back(TexHandle);
3670 Ops.push_back(N->getOperand(2));
3671 Ops.push_back(N->getOperand(3));
3672 Ops.push_back(Chain);
3674 case NVPTXISD::Suld1DArrayI32Clamp:
3675 Opc = NVPTX::SULD_1D_ARRAY_I32_CLAMP;
3676 Ops.push_back(TexHandle);
3677 Ops.push_back(N->getOperand(2));
3678 Ops.push_back(N->getOperand(3));
3679 Ops.push_back(Chain);
3681 case NVPTXISD::Suld1DArrayI64Clamp:
3682 Opc = NVPTX::SULD_1D_ARRAY_I64_CLAMP;
3683 Ops.push_back(TexHandle);
3684 Ops.push_back(N->getOperand(2));
3685 Ops.push_back(N->getOperand(3));
3686 Ops.push_back(Chain);
3688 case NVPTXISD::Suld1DArrayV2I8Clamp:
3689 Opc = NVPTX::SULD_1D_ARRAY_V2I8_CLAMP;
3690 Ops.push_back(TexHandle);
3691 Ops.push_back(N->getOperand(2));
3692 Ops.push_back(N->getOperand(3));
3693 Ops.push_back(Chain);
3695 case NVPTXISD::Suld1DArrayV2I16Clamp:
3696 Opc = NVPTX::SULD_1D_ARRAY_V2I16_CLAMP;
3697 Ops.push_back(TexHandle);
3698 Ops.push_back(N->getOperand(2));
3699 Ops.push_back(N->getOperand(3));
3700 Ops.push_back(Chain);
3702 case NVPTXISD::Suld1DArrayV2I32Clamp:
3703 Opc = NVPTX::SULD_1D_ARRAY_V2I32_CLAMP;
3704 Ops.push_back(TexHandle);
3705 Ops.push_back(N->getOperand(2));
3706 Ops.push_back(N->getOperand(3));
3707 Ops.push_back(Chain);
3709 case NVPTXISD::Suld1DArrayV2I64Clamp:
3710 Opc = NVPTX::SULD_1D_ARRAY_V2I64_CLAMP;
3711 Ops.push_back(TexHandle);
3712 Ops.push_back(N->getOperand(2));
3713 Ops.push_back(N->getOperand(3));
3714 Ops.push_back(Chain);
3716 case NVPTXISD::Suld1DArrayV4I8Clamp:
3717 Opc = NVPTX::SULD_1D_ARRAY_V4I8_CLAMP;
3718 Ops.push_back(TexHandle);
3719 Ops.push_back(N->getOperand(2));
3720 Ops.push_back(N->getOperand(3));
3721 Ops.push_back(Chain);
3723 case NVPTXISD::Suld1DArrayV4I16Clamp:
3724 Opc = NVPTX::SULD_1D_ARRAY_V4I16_CLAMP;
3725 Ops.push_back(TexHandle);
3726 Ops.push_back(N->getOperand(2));
3727 Ops.push_back(N->getOperand(3));
3728 Ops.push_back(Chain);
3730 case NVPTXISD::Suld1DArrayV4I32Clamp:
3731 Opc = NVPTX::SULD_1D_ARRAY_V4I32_CLAMP;
3732 Ops.push_back(TexHandle);
3733 Ops.push_back(N->getOperand(2));
3734 Ops.push_back(N->getOperand(3));
3735 Ops.push_back(Chain);
3737 case NVPTXISD::Suld2DI8Clamp:
3738 Opc = NVPTX::SULD_2D_I8_CLAMP;
3739 Ops.push_back(TexHandle);
3740 Ops.push_back(N->getOperand(2));
3741 Ops.push_back(N->getOperand(3));
3742 Ops.push_back(Chain);
3744 case NVPTXISD::Suld2DI16Clamp:
3745 Opc = NVPTX::SULD_2D_I16_CLAMP;
3746 Ops.push_back(TexHandle);
3747 Ops.push_back(N->getOperand(2));
3748 Ops.push_back(N->getOperand(3));
3749 Ops.push_back(Chain);
3751 case NVPTXISD::Suld2DI32Clamp:
3752 Opc = NVPTX::SULD_2D_I32_CLAMP;
3753 Ops.push_back(TexHandle);
3754 Ops.push_back(N->getOperand(2));
3755 Ops.push_back(N->getOperand(3));
3756 Ops.push_back(Chain);
3758 case NVPTXISD::Suld2DI64Clamp:
3759 Opc = NVPTX::SULD_2D_I64_CLAMP;
3760 Ops.push_back(TexHandle);
3761 Ops.push_back(N->getOperand(2));
3762 Ops.push_back(N->getOperand(3));
3763 Ops.push_back(Chain);
3765 case NVPTXISD::Suld2DV2I8Clamp:
3766 Opc = NVPTX::SULD_2D_V2I8_CLAMP;
3767 Ops.push_back(TexHandle);
3768 Ops.push_back(N->getOperand(2));
3769 Ops.push_back(N->getOperand(3));
3770 Ops.push_back(Chain);
3772 case NVPTXISD::Suld2DV2I16Clamp:
3773 Opc = NVPTX::SULD_2D_V2I16_CLAMP;
3774 Ops.push_back(TexHandle);
3775 Ops.push_back(N->getOperand(2));
3776 Ops.push_back(N->getOperand(3));
3777 Ops.push_back(Chain);
3779 case NVPTXISD::Suld2DV2I32Clamp:
3780 Opc = NVPTX::SULD_2D_V2I32_CLAMP;
3781 Ops.push_back(TexHandle);
3782 Ops.push_back(N->getOperand(2));
3783 Ops.push_back(N->getOperand(3));
3784 Ops.push_back(Chain);
3786 case NVPTXISD::Suld2DV2I64Clamp:
3787 Opc = NVPTX::SULD_2D_V2I64_CLAMP;
3788 Ops.push_back(TexHandle);
3789 Ops.push_back(N->getOperand(2));
3790 Ops.push_back(N->getOperand(3));
3791 Ops.push_back(Chain);
3793 case NVPTXISD::Suld2DV4I8Clamp:
3794 Opc = NVPTX::SULD_2D_V4I8_CLAMP;
3795 Ops.push_back(TexHandle);
3796 Ops.push_back(N->getOperand(2));
3797 Ops.push_back(N->getOperand(3));
3798 Ops.push_back(Chain);
3800 case NVPTXISD::Suld2DV4I16Clamp:
3801 Opc = NVPTX::SULD_2D_V4I16_CLAMP;
3802 Ops.push_back(TexHandle);
3803 Ops.push_back(N->getOperand(2));
3804 Ops.push_back(N->getOperand(3));
3805 Ops.push_back(Chain);
3807 case NVPTXISD::Suld2DV4I32Clamp:
3808 Opc = NVPTX::SULD_2D_V4I32_CLAMP;
3809 Ops.push_back(TexHandle);
3810 Ops.push_back(N->getOperand(2));
3811 Ops.push_back(N->getOperand(3));
3812 Ops.push_back(Chain);
3814 case NVPTXISD::Suld2DArrayI8Clamp:
3815 Opc = NVPTX::SULD_2D_ARRAY_I8_CLAMP;
3816 Ops.push_back(TexHandle);
3817 Ops.push_back(N->getOperand(2));
3818 Ops.push_back(N->getOperand(3));
3819 Ops.push_back(N->getOperand(4));
3820 Ops.push_back(Chain);
3822 case NVPTXISD::Suld2DArrayI16Clamp:
3823 Opc = NVPTX::SULD_2D_ARRAY_I16_CLAMP;
3824 Ops.push_back(TexHandle);
3825 Ops.push_back(N->getOperand(2));
3826 Ops.push_back(N->getOperand(3));
3827 Ops.push_back(N->getOperand(4));
3828 Ops.push_back(Chain);
3830 case NVPTXISD::Suld2DArrayI32Clamp:
3831 Opc = NVPTX::SULD_2D_ARRAY_I32_CLAMP;
3832 Ops.push_back(TexHandle);
3833 Ops.push_back(N->getOperand(2));
3834 Ops.push_back(N->getOperand(3));
3835 Ops.push_back(N->getOperand(4));
3836 Ops.push_back(Chain);
3838 case NVPTXISD::Suld2DArrayI64Clamp:
3839 Opc = NVPTX::SULD_2D_ARRAY_I64_CLAMP;
3840 Ops.push_back(TexHandle);
3841 Ops.push_back(N->getOperand(2));
3842 Ops.push_back(N->getOperand(3));
3843 Ops.push_back(N->getOperand(4));
3844 Ops.push_back(Chain);
3846 case NVPTXISD::Suld2DArrayV2I8Clamp:
3847 Opc = NVPTX::SULD_2D_ARRAY_V2I8_CLAMP;
3848 Ops.push_back(TexHandle);
3849 Ops.push_back(N->getOperand(2));
3850 Ops.push_back(N->getOperand(3));
3851 Ops.push_back(N->getOperand(4));
3852 Ops.push_back(Chain);
3854 case NVPTXISD::Suld2DArrayV2I16Clamp:
3855 Opc = NVPTX::SULD_2D_ARRAY_V2I16_CLAMP;
3856 Ops.push_back(TexHandle);
3857 Ops.push_back(N->getOperand(2));
3858 Ops.push_back(N->getOperand(3));
3859 Ops.push_back(N->getOperand(4));
3860 Ops.push_back(Chain);
3862 case NVPTXISD::Suld2DArrayV2I32Clamp:
3863 Opc = NVPTX::SULD_2D_ARRAY_V2I32_CLAMP;
3864 Ops.push_back(TexHandle);
3865 Ops.push_back(N->getOperand(2));
3866 Ops.push_back(N->getOperand(3));
3867 Ops.push_back(N->getOperand(4));
3868 Ops.push_back(Chain);
3870 case NVPTXISD::Suld2DArrayV2I64Clamp:
3871 Opc = NVPTX::SULD_2D_ARRAY_V2I64_CLAMP;
3872 Ops.push_back(TexHandle);
3873 Ops.push_back(N->getOperand(2));
3874 Ops.push_back(N->getOperand(3));
3875 Ops.push_back(N->getOperand(4));
3876 Ops.push_back(Chain);
3878 case NVPTXISD::Suld2DArrayV4I8Clamp:
3879 Opc = NVPTX::SULD_2D_ARRAY_V4I8_CLAMP;
3880 Ops.push_back(TexHandle);
3881 Ops.push_back(N->getOperand(2));
3882 Ops.push_back(N->getOperand(3));
3883 Ops.push_back(N->getOperand(4));
3884 Ops.push_back(Chain);
3886 case NVPTXISD::Suld2DArrayV4I16Clamp:
3887 Opc = NVPTX::SULD_2D_ARRAY_V4I16_CLAMP;
3888 Ops.push_back(TexHandle);
3889 Ops.push_back(N->getOperand(2));
3890 Ops.push_back(N->getOperand(3));
3891 Ops.push_back(N->getOperand(4));
3892 Ops.push_back(Chain);
3894 case NVPTXISD::Suld2DArrayV4I32Clamp:
3895 Opc = NVPTX::SULD_2D_ARRAY_V4I32_CLAMP;
3896 Ops.push_back(TexHandle);
3897 Ops.push_back(N->getOperand(2));
3898 Ops.push_back(N->getOperand(3));
3899 Ops.push_back(N->getOperand(4));
3900 Ops.push_back(Chain);
3902 case NVPTXISD::Suld3DI8Clamp:
3903 Opc = NVPTX::SULD_3D_I8_CLAMP;
3904 Ops.push_back(TexHandle);
3905 Ops.push_back(N->getOperand(2));
3906 Ops.push_back(N->getOperand(3));
3907 Ops.push_back(N->getOperand(4));
3908 Ops.push_back(Chain);
3910 case NVPTXISD::Suld3DI16Clamp:
3911 Opc = NVPTX::SULD_3D_I16_CLAMP;
3912 Ops.push_back(TexHandle);
3913 Ops.push_back(N->getOperand(2));
3914 Ops.push_back(N->getOperand(3));
3915 Ops.push_back(N->getOperand(4));
3916 Ops.push_back(Chain);
3918 case NVPTXISD::Suld3DI32Clamp:
3919 Opc = NVPTX::SULD_3D_I32_CLAMP;
3920 Ops.push_back(TexHandle);
3921 Ops.push_back(N->getOperand(2));
3922 Ops.push_back(N->getOperand(3));
3923 Ops.push_back(N->getOperand(4));
3924 Ops.push_back(Chain);
3926 case NVPTXISD::Suld3DI64Clamp:
3927 Opc = NVPTX::SULD_3D_I64_CLAMP;
3928 Ops.push_back(TexHandle);
3929 Ops.push_back(N->getOperand(2));
3930 Ops.push_back(N->getOperand(3));
3931 Ops.push_back(N->getOperand(4));
3932 Ops.push_back(Chain);
3934 case NVPTXISD::Suld3DV2I8Clamp:
3935 Opc = NVPTX::SULD_3D_V2I8_CLAMP;
3936 Ops.push_back(TexHandle);
3937 Ops.push_back(N->getOperand(2));
3938 Ops.push_back(N->getOperand(3));
3939 Ops.push_back(N->getOperand(4));
3940 Ops.push_back(Chain);
3942 case NVPTXISD::Suld3DV2I16Clamp:
3943 Opc = NVPTX::SULD_3D_V2I16_CLAMP;
3944 Ops.push_back(TexHandle);
3945 Ops.push_back(N->getOperand(2));
3946 Ops.push_back(N->getOperand(3));
3947 Ops.push_back(N->getOperand(4));
3948 Ops.push_back(Chain);
3950 case NVPTXISD::Suld3DV2I32Clamp:
3951 Opc = NVPTX::SULD_3D_V2I32_CLAMP;
3952 Ops.push_back(TexHandle);
3953 Ops.push_back(N->getOperand(2));
3954 Ops.push_back(N->getOperand(3));
3955 Ops.push_back(N->getOperand(4));
3956 Ops.push_back(Chain);
3958 case NVPTXISD::Suld3DV2I64Clamp:
3959 Opc = NVPTX::SULD_3D_V2I64_CLAMP;
3960 Ops.push_back(TexHandle);
3961 Ops.push_back(N->getOperand(2));
3962 Ops.push_back(N->getOperand(3));
3963 Ops.push_back(N->getOperand(4));
3964 Ops.push_back(Chain);
3966 case NVPTXISD::Suld3DV4I8Clamp:
3967 Opc = NVPTX::SULD_3D_V4I8_CLAMP;
3968 Ops.push_back(TexHandle);
3969 Ops.push_back(N->getOperand(2));
3970 Ops.push_back(N->getOperand(3));
3971 Ops.push_back(N->getOperand(4));
3972 Ops.push_back(Chain);
3974 case NVPTXISD::Suld3DV4I16Clamp:
3975 Opc = NVPTX::SULD_3D_V4I16_CLAMP;
3976 Ops.push_back(TexHandle);
3977 Ops.push_back(N->getOperand(2));
3978 Ops.push_back(N->getOperand(3));
3979 Ops.push_back(N->getOperand(4));
3980 Ops.push_back(Chain);
3982 case NVPTXISD::Suld3DV4I32Clamp:
3983 Opc = NVPTX::SULD_3D_V4I32_CLAMP;
3984 Ops.push_back(TexHandle);
3985 Ops.push_back(N->getOperand(2));
3986 Ops.push_back(N->getOperand(3));
3987 Ops.push_back(N->getOperand(4));
3988 Ops.push_back(Chain);
3990 case NVPTXISD::Suld1DI8Trap:
3991 Opc = NVPTX::SULD_1D_I8_TRAP;
3992 Ops.push_back(TexHandle);
3993 Ops.push_back(N->getOperand(2));
3994 Ops.push_back(Chain);
3996 case NVPTXISD::Suld1DI16Trap:
3997 Opc = NVPTX::SULD_1D_I16_TRAP;
3998 Ops.push_back(TexHandle);
3999 Ops.push_back(N->getOperand(2));
4000 Ops.push_back(Chain);
4002 case NVPTXISD::Suld1DI32Trap:
4003 Opc = NVPTX::SULD_1D_I32_TRAP;
4004 Ops.push_back(TexHandle);
4005 Ops.push_back(N->getOperand(2));
4006 Ops.push_back(Chain);
4008 case NVPTXISD::Suld1DI64Trap:
4009 Opc = NVPTX::SULD_1D_I64_TRAP;
4010 Ops.push_back(TexHandle);
4011 Ops.push_back(N->getOperand(2));
4012 Ops.push_back(Chain);
4014 case NVPTXISD::Suld1DV2I8Trap:
4015 Opc = NVPTX::SULD_1D_V2I8_TRAP;
4016 Ops.push_back(TexHandle);
4017 Ops.push_back(N->getOperand(2));
4018 Ops.push_back(Chain);
4020 case NVPTXISD::Suld1DV2I16Trap:
4021 Opc = NVPTX::SULD_1D_V2I16_TRAP;
4022 Ops.push_back(TexHandle);
4023 Ops.push_back(N->getOperand(2));
4024 Ops.push_back(Chain);
4026 case NVPTXISD::Suld1DV2I32Trap:
4027 Opc = NVPTX::SULD_1D_V2I32_TRAP;
4028 Ops.push_back(TexHandle);
4029 Ops.push_back(N->getOperand(2));
4030 Ops.push_back(Chain);
4032 case NVPTXISD::Suld1DV2I64Trap:
4033 Opc = NVPTX::SULD_1D_V2I64_TRAP;
4034 Ops.push_back(TexHandle);
4035 Ops.push_back(N->getOperand(2));
4036 Ops.push_back(Chain);
4038 case NVPTXISD::Suld1DV4I8Trap:
4039 Opc = NVPTX::SULD_1D_V4I8_TRAP;
4040 Ops.push_back(TexHandle);
4041 Ops.push_back(N->getOperand(2));
4042 Ops.push_back(Chain);
4044 case NVPTXISD::Suld1DV4I16Trap:
4045 Opc = NVPTX::SULD_1D_V4I16_TRAP;
4046 Ops.push_back(TexHandle);
4047 Ops.push_back(N->getOperand(2));
4048 Ops.push_back(Chain);
4050 case NVPTXISD::Suld1DV4I32Trap:
4051 Opc = NVPTX::SULD_1D_V4I32_TRAP;
4052 Ops.push_back(TexHandle);
4053 Ops.push_back(N->getOperand(2));
4054 Ops.push_back(Chain);
4056 case NVPTXISD::Suld1DArrayI8Trap:
4057 Opc = NVPTX::SULD_1D_ARRAY_I8_TRAP;
4058 Ops.push_back(TexHandle);
4059 Ops.push_back(N->getOperand(2));
4060 Ops.push_back(N->getOperand(3));
4061 Ops.push_back(Chain);
4063 case NVPTXISD::Suld1DArrayI16Trap:
4064 Opc = NVPTX::SULD_1D_ARRAY_I16_TRAP;
4065 Ops.push_back(TexHandle);
4066 Ops.push_back(N->getOperand(2));
4067 Ops.push_back(N->getOperand(3));
4068 Ops.push_back(Chain);
4070 case NVPTXISD::Suld1DArrayI32Trap:
4071 Opc = NVPTX::SULD_1D_ARRAY_I32_TRAP;
4072 Ops.push_back(TexHandle);
4073 Ops.push_back(N->getOperand(2));
4074 Ops.push_back(N->getOperand(3));
4075 Ops.push_back(Chain);
4077 case NVPTXISD::Suld1DArrayI64Trap:
4078 Opc = NVPTX::SULD_1D_ARRAY_I64_TRAP;
4079 Ops.push_back(TexHandle);
4080 Ops.push_back(N->getOperand(2));
4081 Ops.push_back(N->getOperand(3));
4082 Ops.push_back(Chain);
4084 case NVPTXISD::Suld1DArrayV2I8Trap:
4085 Opc = NVPTX::SULD_1D_ARRAY_V2I8_TRAP;
4086 Ops.push_back(TexHandle);
4087 Ops.push_back(N->getOperand(2));
4088 Ops.push_back(N->getOperand(3));
4089 Ops.push_back(Chain);
4091 case NVPTXISD::Suld1DArrayV2I16Trap:
4092 Opc = NVPTX::SULD_1D_ARRAY_V2I16_TRAP;
4093 Ops.push_back(TexHandle);
4094 Ops.push_back(N->getOperand(2));
4095 Ops.push_back(N->getOperand(3));
4096 Ops.push_back(Chain);
4098 case NVPTXISD::Suld1DArrayV2I32Trap:
4099 Opc = NVPTX::SULD_1D_ARRAY_V2I32_TRAP;
4100 Ops.push_back(TexHandle);
4101 Ops.push_back(N->getOperand(2));
4102 Ops.push_back(N->getOperand(3));
4103 Ops.push_back(Chain);
4105 case NVPTXISD::Suld1DArrayV2I64Trap:
4106 Opc = NVPTX::SULD_1D_ARRAY_V2I64_TRAP;
4107 Ops.push_back(TexHandle);
4108 Ops.push_back(N->getOperand(2));
4109 Ops.push_back(N->getOperand(3));
4110 Ops.push_back(Chain);
4112 case NVPTXISD::Suld1DArrayV4I8Trap:
4113 Opc = NVPTX::SULD_1D_ARRAY_V4I8_TRAP;
4114 Ops.push_back(TexHandle);
4115 Ops.push_back(N->getOperand(2));
4116 Ops.push_back(N->getOperand(3));
4117 Ops.push_back(Chain);
4119 case NVPTXISD::Suld1DArrayV4I16Trap:
4120 Opc = NVPTX::SULD_1D_ARRAY_V4I16_TRAP;
4121 Ops.push_back(TexHandle);
4122 Ops.push_back(N->getOperand(2));
4123 Ops.push_back(N->getOperand(3));
4124 Ops.push_back(Chain);
4126 case NVPTXISD::Suld1DArrayV4I32Trap:
4127 Opc = NVPTX::SULD_1D_ARRAY_V4I32_TRAP;
4128 Ops.push_back(TexHandle);
4129 Ops.push_back(N->getOperand(2));
4130 Ops.push_back(N->getOperand(3));
4131 Ops.push_back(Chain);
4133 case NVPTXISD::Suld2DI8Trap:
4134 Opc = NVPTX::SULD_2D_I8_TRAP;
4135 Ops.push_back(TexHandle);
4136 Ops.push_back(N->getOperand(2));
4137 Ops.push_back(N->getOperand(3));
4138 Ops.push_back(Chain);
4140 case NVPTXISD::Suld2DI16Trap:
4141 Opc = NVPTX::SULD_2D_I16_TRAP;
4142 Ops.push_back(TexHandle);
4143 Ops.push_back(N->getOperand(2));
4144 Ops.push_back(N->getOperand(3));
4145 Ops.push_back(Chain);
4147 case NVPTXISD::Suld2DI32Trap:
4148 Opc = NVPTX::SULD_2D_I32_TRAP;
4149 Ops.push_back(TexHandle);
4150 Ops.push_back(N->getOperand(2));
4151 Ops.push_back(N->getOperand(3));
4152 Ops.push_back(Chain);
4154 case NVPTXISD::Suld2DI64Trap:
4155 Opc = NVPTX::SULD_2D_I64_TRAP;
4156 Ops.push_back(TexHandle);
4157 Ops.push_back(N->getOperand(2));
4158 Ops.push_back(N->getOperand(3));
4159 Ops.push_back(Chain);
4161 case NVPTXISD::Suld2DV2I8Trap:
4162 Opc = NVPTX::SULD_2D_V2I8_TRAP;
4163 Ops.push_back(TexHandle);
4164 Ops.push_back(N->getOperand(2));
4165 Ops.push_back(N->getOperand(3));
4166 Ops.push_back(Chain);
4168 case NVPTXISD::Suld2DV2I16Trap:
4169 Opc = NVPTX::SULD_2D_V2I16_TRAP;
4170 Ops.push_back(TexHandle);
4171 Ops.push_back(N->getOperand(2));
4172 Ops.push_back(N->getOperand(3));
4173 Ops.push_back(Chain);
4175 case NVPTXISD::Suld2DV2I32Trap:
4176 Opc = NVPTX::SULD_2D_V2I32_TRAP;
4177 Ops.push_back(TexHandle);
4178 Ops.push_back(N->getOperand(2));
4179 Ops.push_back(N->getOperand(3));
4180 Ops.push_back(Chain);
4182 case NVPTXISD::Suld2DV2I64Trap:
4183 Opc = NVPTX::SULD_2D_V2I64_TRAP;
4184 Ops.push_back(TexHandle);
4185 Ops.push_back(N->getOperand(2));
4186 Ops.push_back(N->getOperand(3));
4187 Ops.push_back(Chain);
4189 case NVPTXISD::Suld2DV4I8Trap:
4190 Opc = NVPTX::SULD_2D_V4I8_TRAP;
4191 Ops.push_back(TexHandle);
4192 Ops.push_back(N->getOperand(2));
4193 Ops.push_back(N->getOperand(3));
4194 Ops.push_back(Chain);
4196 case NVPTXISD::Suld2DV4I16Trap:
4197 Opc = NVPTX::SULD_2D_V4I16_TRAP;
4198 Ops.push_back(TexHandle);
4199 Ops.push_back(N->getOperand(2));
4200 Ops.push_back(N->getOperand(3));
4201 Ops.push_back(Chain);
4203 case NVPTXISD::Suld2DV4I32Trap:
4204 Opc = NVPTX::SULD_2D_V4I32_TRAP;
4205 Ops.push_back(TexHandle);
4206 Ops.push_back(N->getOperand(2));
4207 Ops.push_back(N->getOperand(3));
4208 Ops.push_back(Chain);
4210 case NVPTXISD::Suld2DArrayI8Trap:
4211 Opc = NVPTX::SULD_2D_ARRAY_I8_TRAP;
4212 Ops.push_back(TexHandle);
4213 Ops.push_back(N->getOperand(2));
4214 Ops.push_back(N->getOperand(3));
4215 Ops.push_back(N->getOperand(4));
4216 Ops.push_back(Chain);
4218 case NVPTXISD::Suld2DArrayI16Trap:
4219 Opc = NVPTX::SULD_2D_ARRAY_I16_TRAP;
4220 Ops.push_back(TexHandle);
4221 Ops.push_back(N->getOperand(2));
4222 Ops.push_back(N->getOperand(3));
4223 Ops.push_back(N->getOperand(4));
4224 Ops.push_back(Chain);
4226 case NVPTXISD::Suld2DArrayI32Trap:
4227 Opc = NVPTX::SULD_2D_ARRAY_I32_TRAP;
4228 Ops.push_back(TexHandle);
4229 Ops.push_back(N->getOperand(2));
4230 Ops.push_back(N->getOperand(3));
4231 Ops.push_back(N->getOperand(4));
4232 Ops.push_back(Chain);
4234 case NVPTXISD::Suld2DArrayI64Trap:
4235 Opc = NVPTX::SULD_2D_ARRAY_I64_TRAP;
4236 Ops.push_back(TexHandle);
4237 Ops.push_back(N->getOperand(2));
4238 Ops.push_back(N->getOperand(3));
4239 Ops.push_back(N->getOperand(4));
4240 Ops.push_back(Chain);
4242 case NVPTXISD::Suld2DArrayV2I8Trap:
4243 Opc = NVPTX::SULD_2D_ARRAY_V2I8_TRAP;
4244 Ops.push_back(TexHandle);
4245 Ops.push_back(N->getOperand(2));
4246 Ops.push_back(N->getOperand(3));
4247 Ops.push_back(N->getOperand(4));
4248 Ops.push_back(Chain);
4250 case NVPTXISD::Suld2DArrayV2I16Trap:
4251 Opc = NVPTX::SULD_2D_ARRAY_V2I16_TRAP;
4252 Ops.push_back(TexHandle);
4253 Ops.push_back(N->getOperand(2));
4254 Ops.push_back(N->getOperand(3));
4255 Ops.push_back(N->getOperand(4));
4256 Ops.push_back(Chain);
4258 case NVPTXISD::Suld2DArrayV2I32Trap:
4259 Opc = NVPTX::SULD_2D_ARRAY_V2I32_TRAP;
4260 Ops.push_back(TexHandle);
4261 Ops.push_back(N->getOperand(2));
4262 Ops.push_back(N->getOperand(3));
4263 Ops.push_back(N->getOperand(4));
4264 Ops.push_back(Chain);
4266 case NVPTXISD::Suld2DArrayV2I64Trap:
4267 Opc = NVPTX::SULD_2D_ARRAY_V2I64_TRAP;
4268 Ops.push_back(TexHandle);
4269 Ops.push_back(N->getOperand(2));
4270 Ops.push_back(N->getOperand(3));
4271 Ops.push_back(N->getOperand(4));
4272 Ops.push_back(Chain);
4274 case NVPTXISD::Suld2DArrayV4I8Trap:
4275 Opc = NVPTX::SULD_2D_ARRAY_V4I8_TRAP;
4276 Ops.push_back(TexHandle);
4277 Ops.push_back(N->getOperand(2));
4278 Ops.push_back(N->getOperand(3));
4279 Ops.push_back(N->getOperand(4));
4280 Ops.push_back(Chain);
4282 case NVPTXISD::Suld2DArrayV4I16Trap:
4283 Opc = NVPTX::SULD_2D_ARRAY_V4I16_TRAP;
4284 Ops.push_back(TexHandle);
4285 Ops.push_back(N->getOperand(2));
4286 Ops.push_back(N->getOperand(3));
4287 Ops.push_back(N->getOperand(4));
4288 Ops.push_back(Chain);
4290 case NVPTXISD::Suld2DArrayV4I32Trap:
4291 Opc = NVPTX::SULD_2D_ARRAY_V4I32_TRAP;
4292 Ops.push_back(TexHandle);
4293 Ops.push_back(N->getOperand(2));
4294 Ops.push_back(N->getOperand(3));
4295 Ops.push_back(N->getOperand(4));
4296 Ops.push_back(Chain);
4298 case NVPTXISD::Suld3DI8Trap:
4299 Opc = NVPTX::SULD_3D_I8_TRAP;
4300 Ops.push_back(TexHandle);
4301 Ops.push_back(N->getOperand(2));
4302 Ops.push_back(N->getOperand(3));
4303 Ops.push_back(N->getOperand(4));
4304 Ops.push_back(Chain);
4306 case NVPTXISD::Suld3DI16Trap:
4307 Opc = NVPTX::SULD_3D_I16_TRAP;
4308 Ops.push_back(TexHandle);
4309 Ops.push_back(N->getOperand(2));
4310 Ops.push_back(N->getOperand(3));
4311 Ops.push_back(N->getOperand(4));
4312 Ops.push_back(Chain);
4314 case NVPTXISD::Suld3DI32Trap:
4315 Opc = NVPTX::SULD_3D_I32_TRAP;
4316 Ops.push_back(TexHandle);
4317 Ops.push_back(N->getOperand(2));
4318 Ops.push_back(N->getOperand(3));
4319 Ops.push_back(N->getOperand(4));
4320 Ops.push_back(Chain);
4322 case NVPTXISD::Suld3DI64Trap:
4323 Opc = NVPTX::SULD_3D_I64_TRAP;
4324 Ops.push_back(TexHandle);
4325 Ops.push_back(N->getOperand(2));
4326 Ops.push_back(N->getOperand(3));
4327 Ops.push_back(N->getOperand(4));
4328 Ops.push_back(Chain);
4330 case NVPTXISD::Suld3DV2I8Trap:
4331 Opc = NVPTX::SULD_3D_V2I8_TRAP;
4332 Ops.push_back(TexHandle);
4333 Ops.push_back(N->getOperand(2));
4334 Ops.push_back(N->getOperand(3));
4335 Ops.push_back(N->getOperand(4));
4336 Ops.push_back(Chain);
4338 case NVPTXISD::Suld3DV2I16Trap:
4339 Opc = NVPTX::SULD_3D_V2I16_TRAP;
4340 Ops.push_back(TexHandle);
4341 Ops.push_back(N->getOperand(2));
4342 Ops.push_back(N->getOperand(3));
4343 Ops.push_back(N->getOperand(4));
4344 Ops.push_back(Chain);
4346 case NVPTXISD::Suld3DV2I32Trap:
4347 Opc = NVPTX::SULD_3D_V2I32_TRAP;
4348 Ops.push_back(TexHandle);
4349 Ops.push_back(N->getOperand(2));
4350 Ops.push_back(N->getOperand(3));
4351 Ops.push_back(N->getOperand(4));
4352 Ops.push_back(Chain);
4354 case NVPTXISD::Suld3DV2I64Trap:
4355 Opc = NVPTX::SULD_3D_V2I64_TRAP;
4356 Ops.push_back(TexHandle);
4357 Ops.push_back(N->getOperand(2));
4358 Ops.push_back(N->getOperand(3));
4359 Ops.push_back(N->getOperand(4));
4360 Ops.push_back(Chain);
4362 case NVPTXISD::Suld3DV4I8Trap:
4363 Opc = NVPTX::SULD_3D_V4I8_TRAP;
4364 Ops.push_back(TexHandle);
4365 Ops.push_back(N->getOperand(2));
4366 Ops.push_back(N->getOperand(3));
4367 Ops.push_back(N->getOperand(4));
4368 Ops.push_back(Chain);
4370 case NVPTXISD::Suld3DV4I16Trap:
4371 Opc = NVPTX::SULD_3D_V4I16_TRAP;
4372 Ops.push_back(TexHandle);
4373 Ops.push_back(N->getOperand(2));
4374 Ops.push_back(N->getOperand(3));
4375 Ops.push_back(N->getOperand(4));
4376 Ops.push_back(Chain);
4378 case NVPTXISD::Suld3DV4I32Trap:
4379 Opc = NVPTX::SULD_3D_V4I32_TRAP;
4380 Ops.push_back(TexHandle);
4381 Ops.push_back(N->getOperand(2));
4382 Ops.push_back(N->getOperand(3));
4383 Ops.push_back(N->getOperand(4));
4384 Ops.push_back(Chain);
4386 case NVPTXISD::Suld1DI8Zero:
4387 Opc = NVPTX::SULD_1D_I8_ZERO;
4388 Ops.push_back(TexHandle);
4389 Ops.push_back(N->getOperand(2));
4390 Ops.push_back(Chain);
4392 case NVPTXISD::Suld1DI16Zero:
4393 Opc = NVPTX::SULD_1D_I16_ZERO;
4394 Ops.push_back(TexHandle);
4395 Ops.push_back(N->getOperand(2));
4396 Ops.push_back(Chain);
4398 case NVPTXISD::Suld1DI32Zero:
4399 Opc = NVPTX::SULD_1D_I32_ZERO;
4400 Ops.push_back(TexHandle);
4401 Ops.push_back(N->getOperand(2));
4402 Ops.push_back(Chain);
4404 case NVPTXISD::Suld1DI64Zero:
4405 Opc = NVPTX::SULD_1D_I64_ZERO;
4406 Ops.push_back(TexHandle);
4407 Ops.push_back(N->getOperand(2));
4408 Ops.push_back(Chain);
4410 case NVPTXISD::Suld1DV2I8Zero:
4411 Opc = NVPTX::SULD_1D_V2I8_ZERO;
4412 Ops.push_back(TexHandle);
4413 Ops.push_back(N->getOperand(2));
4414 Ops.push_back(Chain);
4416 case NVPTXISD::Suld1DV2I16Zero:
4417 Opc = NVPTX::SULD_1D_V2I16_ZERO;
4418 Ops.push_back(TexHandle);
4419 Ops.push_back(N->getOperand(2));
4420 Ops.push_back(Chain);
4422 case NVPTXISD::Suld1DV2I32Zero:
4423 Opc = NVPTX::SULD_1D_V2I32_ZERO;
4424 Ops.push_back(TexHandle);
4425 Ops.push_back(N->getOperand(2));
4426 Ops.push_back(Chain);
4428 case NVPTXISD::Suld1DV2I64Zero:
4429 Opc = NVPTX::SULD_1D_V2I64_ZERO;
4430 Ops.push_back(TexHandle);
4431 Ops.push_back(N->getOperand(2));
4432 Ops.push_back(Chain);
4434 case NVPTXISD::Suld1DV4I8Zero:
4435 Opc = NVPTX::SULD_1D_V4I8_ZERO;
4436 Ops.push_back(TexHandle);
4437 Ops.push_back(N->getOperand(2));
4438 Ops.push_back(Chain);
4440 case NVPTXISD::Suld1DV4I16Zero:
4441 Opc = NVPTX::SULD_1D_V4I16_ZERO;
4442 Ops.push_back(TexHandle);
4443 Ops.push_back(N->getOperand(2));
4444 Ops.push_back(Chain);
4446 case NVPTXISD::Suld1DV4I32Zero:
4447 Opc = NVPTX::SULD_1D_V4I32_ZERO;
4448 Ops.push_back(TexHandle);
4449 Ops.push_back(N->getOperand(2));
4450 Ops.push_back(Chain);
4452 case NVPTXISD::Suld1DArrayI8Zero:
4453 Opc = NVPTX::SULD_1D_ARRAY_I8_ZERO;
4454 Ops.push_back(TexHandle);
4455 Ops.push_back(N->getOperand(2));
4456 Ops.push_back(N->getOperand(3));
4457 Ops.push_back(Chain);
4459 case NVPTXISD::Suld1DArrayI16Zero:
4460 Opc = NVPTX::SULD_1D_ARRAY_I16_ZERO;
4461 Ops.push_back(TexHandle);
4462 Ops.push_back(N->getOperand(2));
4463 Ops.push_back(N->getOperand(3));
4464 Ops.push_back(Chain);
4466 case NVPTXISD::Suld1DArrayI32Zero:
4467 Opc = NVPTX::SULD_1D_ARRAY_I32_ZERO;
4468 Ops.push_back(TexHandle);
4469 Ops.push_back(N->getOperand(2));
4470 Ops.push_back(N->getOperand(3));
4471 Ops.push_back(Chain);
4473 case NVPTXISD::Suld1DArrayI64Zero:
4474 Opc = NVPTX::SULD_1D_ARRAY_I64_ZERO;
4475 Ops.push_back(TexHandle);
4476 Ops.push_back(N->getOperand(2));
4477 Ops.push_back(N->getOperand(3));
4478 Ops.push_back(Chain);
4480 case NVPTXISD::Suld1DArrayV2I8Zero:
4481 Opc = NVPTX::SULD_1D_ARRAY_V2I8_ZERO;
4482 Ops.push_back(TexHandle);
4483 Ops.push_back(N->getOperand(2));
4484 Ops.push_back(N->getOperand(3));
4485 Ops.push_back(Chain);
4487 case NVPTXISD::Suld1DArrayV2I16Zero:
4488 Opc = NVPTX::SULD_1D_ARRAY_V2I16_ZERO;
4489 Ops.push_back(TexHandle);
4490 Ops.push_back(N->getOperand(2));
4491 Ops.push_back(N->getOperand(3));
4492 Ops.push_back(Chain);
4494 case NVPTXISD::Suld1DArrayV2I32Zero:
4495 Opc = NVPTX::SULD_1D_ARRAY_V2I32_ZERO;
4496 Ops.push_back(TexHandle);
4497 Ops.push_back(N->getOperand(2));
4498 Ops.push_back(N->getOperand(3));
4499 Ops.push_back(Chain);
4501 case NVPTXISD::Suld1DArrayV2I64Zero:
4502 Opc = NVPTX::SULD_1D_ARRAY_V2I64_ZERO;
4503 Ops.push_back(TexHandle);
4504 Ops.push_back(N->getOperand(2));
4505 Ops.push_back(N->getOperand(3));
4506 Ops.push_back(Chain);
4508 case NVPTXISD::Suld1DArrayV4I8Zero:
4509 Opc = NVPTX::SULD_1D_ARRAY_V4I8_ZERO;
4510 Ops.push_back(TexHandle);
4511 Ops.push_back(N->getOperand(2));
4512 Ops.push_back(N->getOperand(3));
4513 Ops.push_back(Chain);
4515 case NVPTXISD::Suld1DArrayV4I16Zero:
4516 Opc = NVPTX::SULD_1D_ARRAY_V4I16_ZERO;
4517 Ops.push_back(TexHandle);
4518 Ops.push_back(N->getOperand(2));
4519 Ops.push_back(N->getOperand(3));
4520 Ops.push_back(Chain);
4522 case NVPTXISD::Suld1DArrayV4I32Zero:
4523 Opc = NVPTX::SULD_1D_ARRAY_V4I32_ZERO;
4524 Ops.push_back(TexHandle);
4525 Ops.push_back(N->getOperand(2));
4526 Ops.push_back(N->getOperand(3));
4527 Ops.push_back(Chain);
4529 case NVPTXISD::Suld2DI8Zero:
4530 Opc = NVPTX::SULD_2D_I8_ZERO;
4531 Ops.push_back(TexHandle);
4532 Ops.push_back(N->getOperand(2));
4533 Ops.push_back(N->getOperand(3));
4534 Ops.push_back(Chain);
4536 case NVPTXISD::Suld2DI16Zero:
4537 Opc = NVPTX::SULD_2D_I16_ZERO;
4538 Ops.push_back(TexHandle);
4539 Ops.push_back(N->getOperand(2));
4540 Ops.push_back(N->getOperand(3));
4541 Ops.push_back(Chain);
4543 case NVPTXISD::Suld2DI32Zero:
4544 Opc = NVPTX::SULD_2D_I32_ZERO;
4545 Ops.push_back(TexHandle);
4546 Ops.push_back(N->getOperand(2));
4547 Ops.push_back(N->getOperand(3));
4548 Ops.push_back(Chain);
4550 case NVPTXISD::Suld2DI64Zero:
4551 Opc = NVPTX::SULD_2D_I64_ZERO;
4552 Ops.push_back(TexHandle);
4553 Ops.push_back(N->getOperand(2));
4554 Ops.push_back(N->getOperand(3));
4555 Ops.push_back(Chain);
4557 case NVPTXISD::Suld2DV2I8Zero:
4558 Opc = NVPTX::SULD_2D_V2I8_ZERO;
4559 Ops.push_back(TexHandle);
4560 Ops.push_back(N->getOperand(2));
4561 Ops.push_back(N->getOperand(3));
4562 Ops.push_back(Chain);
4564 case NVPTXISD::Suld2DV2I16Zero:
4565 Opc = NVPTX::SULD_2D_V2I16_ZERO;
4566 Ops.push_back(TexHandle);
4567 Ops.push_back(N->getOperand(2));
4568 Ops.push_back(N->getOperand(3));
4569 Ops.push_back(Chain);
4571 case NVPTXISD::Suld2DV2I32Zero:
4572 Opc = NVPTX::SULD_2D_V2I32_ZERO;
4573 Ops.push_back(TexHandle);
4574 Ops.push_back(N->getOperand(2));
4575 Ops.push_back(N->getOperand(3));
4576 Ops.push_back(Chain);
4578 case NVPTXISD::Suld2DV2I64Zero:
4579 Opc = NVPTX::SULD_2D_V2I64_ZERO;
4580 Ops.push_back(TexHandle);
4581 Ops.push_back(N->getOperand(2));
4582 Ops.push_back(N->getOperand(3));
4583 Ops.push_back(Chain);
4585 case NVPTXISD::Suld2DV4I8Zero:
4586 Opc = NVPTX::SULD_2D_V4I8_ZERO;
4587 Ops.push_back(TexHandle);
4588 Ops.push_back(N->getOperand(2));
4589 Ops.push_back(N->getOperand(3));
4590 Ops.push_back(Chain);
4592 case NVPTXISD::Suld2DV4I16Zero:
4593 Opc = NVPTX::SULD_2D_V4I16_ZERO;
4594 Ops.push_back(TexHandle);
4595 Ops.push_back(N->getOperand(2));
4596 Ops.push_back(N->getOperand(3));
4597 Ops.push_back(Chain);
4599 case NVPTXISD::Suld2DV4I32Zero:
4600 Opc = NVPTX::SULD_2D_V4I32_ZERO;
4601 Ops.push_back(TexHandle);
4602 Ops.push_back(N->getOperand(2));
4603 Ops.push_back(N->getOperand(3));
4604 Ops.push_back(Chain);
4606 case NVPTXISD::Suld2DArrayI8Zero:
4607 Opc = NVPTX::SULD_2D_ARRAY_I8_ZERO;
4608 Ops.push_back(TexHandle);
4609 Ops.push_back(N->getOperand(2));
4610 Ops.push_back(N->getOperand(3));
4611 Ops.push_back(N->getOperand(4));
4612 Ops.push_back(Chain);
4614 case NVPTXISD::Suld2DArrayI16Zero:
4615 Opc = NVPTX::SULD_2D_ARRAY_I16_ZERO;
4616 Ops.push_back(TexHandle);
4617 Ops.push_back(N->getOperand(2));
4618 Ops.push_back(N->getOperand(3));
4619 Ops.push_back(N->getOperand(4));
4620 Ops.push_back(Chain);
4622 case NVPTXISD::Suld2DArrayI32Zero:
4623 Opc = NVPTX::SULD_2D_ARRAY_I32_ZERO;
4624 Ops.push_back(TexHandle);
4625 Ops.push_back(N->getOperand(2));
4626 Ops.push_back(N->getOperand(3));
4627 Ops.push_back(N->getOperand(4));
4628 Ops.push_back(Chain);
4630 case NVPTXISD::Suld2DArrayI64Zero:
4631 Opc = NVPTX::SULD_2D_ARRAY_I64_ZERO;
4632 Ops.push_back(TexHandle);
4633 Ops.push_back(N->getOperand(2));
4634 Ops.push_back(N->getOperand(3));
4635 Ops.push_back(N->getOperand(4));
4636 Ops.push_back(Chain);
4638 case NVPTXISD::Suld2DArrayV2I8Zero:
4639 Opc = NVPTX::SULD_2D_ARRAY_V2I8_ZERO;
4640 Ops.push_back(TexHandle);
4641 Ops.push_back(N->getOperand(2));
4642 Ops.push_back(N->getOperand(3));
4643 Ops.push_back(N->getOperand(4));
4644 Ops.push_back(Chain);
4646 case NVPTXISD::Suld2DArrayV2I16Zero:
4647 Opc = NVPTX::SULD_2D_ARRAY_V2I16_ZERO;
4648 Ops.push_back(TexHandle);
4649 Ops.push_back(N->getOperand(2));
4650 Ops.push_back(N->getOperand(3));
4651 Ops.push_back(N->getOperand(4));
4652 Ops.push_back(Chain);
4654 case NVPTXISD::Suld2DArrayV2I32Zero:
4655 Opc = NVPTX::SULD_2D_ARRAY_V2I32_ZERO;
4656 Ops.push_back(TexHandle);
4657 Ops.push_back(N->getOperand(2));
4658 Ops.push_back(N->getOperand(3));
4659 Ops.push_back(N->getOperand(4));
4660 Ops.push_back(Chain);
4662 case NVPTXISD::Suld2DArrayV2I64Zero:
4663 Opc = NVPTX::SULD_2D_ARRAY_V2I64_ZERO;
4664 Ops.push_back(TexHandle);
4665 Ops.push_back(N->getOperand(2));
4666 Ops.push_back(N->getOperand(3));
4667 Ops.push_back(N->getOperand(4));
4668 Ops.push_back(Chain);
4670 case NVPTXISD::Suld2DArrayV4I8Zero:
4671 Opc = NVPTX::SULD_2D_ARRAY_V4I8_ZERO;
4672 Ops.push_back(TexHandle);
4673 Ops.push_back(N->getOperand(2));
4674 Ops.push_back(N->getOperand(3));
4675 Ops.push_back(N->getOperand(4));
4676 Ops.push_back(Chain);
4678 case NVPTXISD::Suld2DArrayV4I16Zero:
4679 Opc = NVPTX::SULD_2D_ARRAY_V4I16_ZERO;
4680 Ops.push_back(TexHandle);
4681 Ops.push_back(N->getOperand(2));
4682 Ops.push_back(N->getOperand(3));
4683 Ops.push_back(N->getOperand(4));
4684 Ops.push_back(Chain);
4686 case NVPTXISD::Suld2DArrayV4I32Zero:
4687 Opc = NVPTX::SULD_2D_ARRAY_V4I32_ZERO;
4688 Ops.push_back(TexHandle);
4689 Ops.push_back(N->getOperand(2));
4690 Ops.push_back(N->getOperand(3));
4691 Ops.push_back(N->getOperand(4));
4692 Ops.push_back(Chain);
4694 case NVPTXISD::Suld3DI8Zero:
4695 Opc = NVPTX::SULD_3D_I8_ZERO;
4696 Ops.push_back(TexHandle);
4697 Ops.push_back(N->getOperand(2));
4698 Ops.push_back(N->getOperand(3));
4699 Ops.push_back(N->getOperand(4));
4700 Ops.push_back(Chain);
4702 case NVPTXISD::Suld3DI16Zero:
4703 Opc = NVPTX::SULD_3D_I16_ZERO;
4704 Ops.push_back(TexHandle);
4705 Ops.push_back(N->getOperand(2));
4706 Ops.push_back(N->getOperand(3));
4707 Ops.push_back(N->getOperand(4));
4708 Ops.push_back(Chain);
4710 case NVPTXISD::Suld3DI32Zero:
4711 Opc = NVPTX::SULD_3D_I32_ZERO;
4712 Ops.push_back(TexHandle);
4713 Ops.push_back(N->getOperand(2));
4714 Ops.push_back(N->getOperand(3));
4715 Ops.push_back(N->getOperand(4));
4716 Ops.push_back(Chain);
4718 case NVPTXISD::Suld3DI64Zero:
4719 Opc = NVPTX::SULD_3D_I64_ZERO;
4720 Ops.push_back(TexHandle);
4721 Ops.push_back(N->getOperand(2));
4722 Ops.push_back(N->getOperand(3));
4723 Ops.push_back(N->getOperand(4));
4724 Ops.push_back(Chain);
4726 case NVPTXISD::Suld3DV2I8Zero:
4727 Opc = NVPTX::SULD_3D_V2I8_ZERO;
4728 Ops.push_back(TexHandle);
4729 Ops.push_back(N->getOperand(2));
4730 Ops.push_back(N->getOperand(3));
4731 Ops.push_back(N->getOperand(4));
4732 Ops.push_back(Chain);
4734 case NVPTXISD::Suld3DV2I16Zero:
4735 Opc = NVPTX::SULD_3D_V2I16_ZERO;
4736 Ops.push_back(TexHandle);
4737 Ops.push_back(N->getOperand(2));
4738 Ops.push_back(N->getOperand(3));
4739 Ops.push_back(N->getOperand(4));
4740 Ops.push_back(Chain);
4742 case NVPTXISD::Suld3DV2I32Zero:
4743 Opc = NVPTX::SULD_3D_V2I32_ZERO;
4744 Ops.push_back(TexHandle);
4745 Ops.push_back(N->getOperand(2));
4746 Ops.push_back(N->getOperand(3));
4747 Ops.push_back(N->getOperand(4));
4748 Ops.push_back(Chain);
4750 case NVPTXISD::Suld3DV2I64Zero:
4751 Opc = NVPTX::SULD_3D_V2I64_ZERO;
4752 Ops.push_back(TexHandle);
4753 Ops.push_back(N->getOperand(2));
4754 Ops.push_back(N->getOperand(3));
4755 Ops.push_back(N->getOperand(4));
4756 Ops.push_back(Chain);
4758 case NVPTXISD::Suld3DV4I8Zero:
4759 Opc = NVPTX::SULD_3D_V4I8_ZERO;
4760 Ops.push_back(TexHandle);
4761 Ops.push_back(N->getOperand(2));
4762 Ops.push_back(N->getOperand(3));
4763 Ops.push_back(N->getOperand(4));
4764 Ops.push_back(Chain);
4766 case NVPTXISD::Suld3DV4I16Zero:
4767 Opc = NVPTX::SULD_3D_V4I16_ZERO;
4768 Ops.push_back(TexHandle);
4769 Ops.push_back(N->getOperand(2));
4770 Ops.push_back(N->getOperand(3));
4771 Ops.push_back(N->getOperand(4));
4772 Ops.push_back(Chain);
4774 case NVPTXISD::Suld3DV4I32Zero:
4775 Opc = NVPTX::SULD_3D_V4I32_ZERO;
4776 Ops.push_back(TexHandle);
4777 Ops.push_back(N->getOperand(2));
4778 Ops.push_back(N->getOperand(3));
4779 Ops.push_back(N->getOperand(4));
4780 Ops.push_back(Chain);
4783 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
4788 /// SelectBFE - Look for instruction sequences that can be made more efficient
4789 /// by using the 'bfe' (bit-field extract) PTX instruction
4790 SDNode *NVPTXDAGToDAGISel::SelectBFE(SDNode *N) {
4792 SDValue LHS = N->getOperand(0);
4793 SDValue RHS = N->getOperand(1);
4797 bool IsSigned = false;
4799 if (N->getOpcode() == ISD::AND) {
4800 // Canonicalize the operands
4801 // We want 'and %val, %mask'
4802 if (isa<ConstantSDNode>(LHS) && !isa<ConstantSDNode>(RHS)) {
4803 std::swap(LHS, RHS);
4806 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(RHS);
4808 // We need a constant mask on the RHS of the AND
4812 // Extract the mask bits
4813 uint64_t MaskVal = Mask->getZExtValue();
4814 if (!isMask_64(MaskVal)) {
4815 // We *could* handle shifted masks here, but doing so would require an
4816 // 'and' operation to fix up the low-order bits so we would trade
4817 // shr+and for bfe+and, which has the same throughput
4821 // How many bits are in our mask?
4822 uint64_t NumBits = countTrailingOnes(MaskVal);
4823 Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32);
4825 if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) {
4826 // We have a 'srl/and' pair, extract the effective start bit and length
4827 Val = LHS.getNode()->getOperand(0);
4828 Start = LHS.getNode()->getOperand(1);
4829 ConstantSDNode *StartConst = dyn_cast<ConstantSDNode>(Start);
4831 uint64_t StartVal = StartConst->getZExtValue();
4832 // How many "good" bits do we have left? "good" is defined here as bits
4833 // that exist in the original value, not shifted in.
4834 uint64_t GoodBits = Start.getValueType().getSizeInBits() - StartVal;
4835 if (NumBits > GoodBits) {
4836 // Do not handle the case where bits have been shifted in. In theory
4837 // we could handle this, but the cost is likely higher than just
4838 // emitting the srl/and pair.
4841 Start = CurDAG->getTargetConstant(StartVal, DL, MVT::i32);
4843 // Do not handle the case where the shift amount (can be zero if no srl
4844 // was found) is not constant. We could handle this case, but it would
4845 // require run-time logic that would be more expensive than just
4846 // emitting the srl/and pair.
4850 // Do not handle the case where the LHS of the and is not a shift. While
4851 // it would be trivial to handle this case, it would just transform
4852 // 'and' -> 'bfe', but 'and' has higher-throughput.
4855 } else if (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) {
4856 if (LHS->getOpcode() == ISD::AND) {
4857 ConstantSDNode *ShiftCnst = dyn_cast<ConstantSDNode>(RHS);
4859 // Shift amount must be constant
4863 uint64_t ShiftAmt = ShiftCnst->getZExtValue();
4865 SDValue AndLHS = LHS->getOperand(0);
4866 SDValue AndRHS = LHS->getOperand(1);
4868 // Canonicalize the AND to have the mask on the RHS
4869 if (isa<ConstantSDNode>(AndLHS)) {
4870 std::swap(AndLHS, AndRHS);
4873 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(AndRHS);
4875 // Mask must be constant
4879 uint64_t MaskVal = MaskCnst->getZExtValue();
4882 if (isMask_64(MaskVal)) {
4884 // The number of bits in the result bitfield will be the number of
4885 // trailing ones (the AND) minus the number of bits we shift off
4886 NumBits = countTrailingOnes(MaskVal) - ShiftAmt;
4887 } else if (isShiftedMask_64(MaskVal)) {
4888 NumZeros = countTrailingZeros(MaskVal);
4889 unsigned NumOnes = countTrailingOnes(MaskVal >> NumZeros);
4890 // The number of bits in the result bitfield will be the number of
4891 // trailing zeros plus the number of set bits in the mask minus the
4892 // number of bits we shift off
4893 NumBits = NumZeros + NumOnes - ShiftAmt;
4895 // This is not a mask we can handle
4899 if (ShiftAmt < NumZeros) {
4900 // Handling this case would require extra logic that would make this
4901 // transformation non-profitable
4906 Start = CurDAG->getTargetConstant(ShiftAmt, DL, MVT::i32);
4907 Len = CurDAG->getTargetConstant(NumBits, DL, MVT::i32);
4908 } else if (LHS->getOpcode() == ISD::SHL) {
4909 // Here, we have a pattern like:
4911 // (sra (shl val, NN), MM)
4913 // (srl (shl val, NN), MM)
4915 // If MM >= NN, we can efficiently optimize this with bfe
4916 Val = LHS->getOperand(0);
4918 SDValue ShlRHS = LHS->getOperand(1);
4919 ConstantSDNode *ShlCnst = dyn_cast<ConstantSDNode>(ShlRHS);
4921 // Shift amount must be constant
4924 uint64_t InnerShiftAmt = ShlCnst->getZExtValue();
4926 SDValue ShrRHS = RHS;
4927 ConstantSDNode *ShrCnst = dyn_cast<ConstantSDNode>(ShrRHS);
4929 // Shift amount must be constant
4932 uint64_t OuterShiftAmt = ShrCnst->getZExtValue();
4934 // To avoid extra codegen and be profitable, we need Outer >= Inner
4935 if (OuterShiftAmt < InnerShiftAmt) {
4939 // If the outer shift is more than the type size, we have no bitfield to
4940 // extract (since we also check that the inner shift is <= the outer shift
4941 // then this also implies that the inner shift is < the type size)
4942 if (OuterShiftAmt >= Val.getValueType().getSizeInBits()) {
4947 CurDAG->getTargetConstant(OuterShiftAmt - InnerShiftAmt, DL, MVT::i32);
4949 CurDAG->getTargetConstant(Val.getValueType().getSizeInBits() -
4950 OuterShiftAmt, DL, MVT::i32);
4952 if (N->getOpcode() == ISD::SRA) {
4953 // If we have a arithmetic right shift, we need to use the signed bfe
4968 // For the BFE operations we form here from "and" and "srl", always use the
4969 // unsigned variants.
4970 if (Val.getValueType() == MVT::i32) {
4972 Opc = NVPTX::BFE_S32rii;
4974 Opc = NVPTX::BFE_U32rii;
4976 } else if (Val.getValueType() == MVT::i64) {
4978 Opc = NVPTX::BFE_S64rii;
4980 Opc = NVPTX::BFE_U64rii;
4983 // We cannot handle this type
4991 return CurDAG->getMachineNode(Opc, DL, N->getVTList(), Ops);
4994 // SelectDirectAddr - Match a direct address for DAG.
4995 // A direct address could be a globaladdress or externalsymbol.
4996 bool NVPTXDAGToDAGISel::SelectDirectAddr(SDValue N, SDValue &Address) {
4997 // Return true if TGA or ES.
4998 if (N.getOpcode() == ISD::TargetGlobalAddress ||
4999 N.getOpcode() == ISD::TargetExternalSymbol) {
5003 if (N.getOpcode() == NVPTXISD::Wrapper) {
5004 Address = N.getOperand(0);
5007 if (N.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
5008 unsigned IID = cast<ConstantSDNode>(N.getOperand(0))->getZExtValue();
5009 if (IID == Intrinsic::nvvm_ptr_gen_to_param)
5010 if (N.getOperand(1).getOpcode() == NVPTXISD::MoveParam)
5011 return (SelectDirectAddr(N.getOperand(1).getOperand(0), Address));
5017 bool NVPTXDAGToDAGISel::SelectADDRsi_imp(
5018 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
5019 if (Addr.getOpcode() == ISD::ADD) {
5020 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
5021 SDValue base = Addr.getOperand(0);
5022 if (SelectDirectAddr(base, Base)) {
5023 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(OpNode),
5033 bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr,
5034 SDValue &Base, SDValue &Offset) {
5035 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32);
5039 bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr,
5040 SDValue &Base, SDValue &Offset) {
5041 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64);
5045 bool NVPTXDAGToDAGISel::SelectADDRri_imp(
5046 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
5047 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
5048 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
5049 Offset = CurDAG->getTargetConstant(0, SDLoc(OpNode), mvt);
5052 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
5053 Addr.getOpcode() == ISD::TargetGlobalAddress)
5054 return false; // direct calls.
5056 if (Addr.getOpcode() == ISD::ADD) {
5057 if (SelectDirectAddr(Addr.getOperand(0), Addr)) {
5060 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
5061 if (FrameIndexSDNode *FIN =
5062 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
5063 // Constant offset from frame ref.
5064 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
5066 Base = Addr.getOperand(0);
5067 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(OpNode),
5076 bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr,
5077 SDValue &Base, SDValue &Offset) {
5078 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32);
5082 bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr,
5083 SDValue &Base, SDValue &Offset) {
5084 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64);
5087 bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
5088 unsigned int spN) const {
5089 const Value *Src = nullptr;
5090 if (MemSDNode *mN = dyn_cast<MemSDNode>(N)) {
5091 if (spN == 0 && mN->getMemOperand()->getPseudoValue())
5093 Src = mN->getMemOperand()->getValue();
5097 if (auto *PT = dyn_cast<PointerType>(Src->getType()))
5098 return (PT->getAddressSpace() == spN);
5102 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
5103 /// inline asm expressions.
5104 bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
5105 const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
5107 switch (ConstraintID) {
5110 case InlineAsm::Constraint_m: // memory
5111 if (SelectDirectAddr(Op, Op0)) {
5112 OutOps.push_back(Op0);
5113 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
5116 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
5117 OutOps.push_back(Op0);
5118 OutOps.push_back(Op1);