1 //===-- NVPTXISelDAGToDAG.cpp - A dag to dag inst selector for NVPTX ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXISelDAGToDAG.h"
15 #include "llvm/IR/GlobalValue.h"
16 #include "llvm/IR/Instructions.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Target/TargetIntrinsicInfo.h"
25 #define DEBUG_TYPE "nvptx-isel"
28 FMAContractLevel("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
29 cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
30 " 1: do it 2: do it aggressively"),
33 static cl::opt<int> UsePrecDivF32(
34 "nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden,
35 cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
36 " IEEE Compliant F32 div.rnd if avaiable."),
40 UsePrecSqrtF32("nvptx-prec-sqrtf32", cl::Hidden,
41 cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
45 FtzEnabled("nvptx-f32ftz", cl::ZeroOrMore, cl::Hidden,
46 cl::desc("NVPTX Specific: Flush f32 subnormals to sign-preserving zero."),
50 /// createNVPTXISelDag - This pass converts a legalized DAG into a
51 /// NVPTX-specific DAG, ready for instruction scheduling.
52 FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
53 llvm::CodeGenOpt::Level OptLevel) {
54 return new NVPTXDAGToDAGISel(TM, OptLevel);
57 NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
58 CodeGenOpt::Level OptLevel)
59 : SelectionDAGISel(tm, OptLevel),
60 Subtarget(tm.getSubtarget<NVPTXSubtarget>()) {
62 doFMAF32 = (OptLevel > 0) && Subtarget.hasFMAF32() && (FMAContractLevel >= 1);
63 doFMAF64 = (OptLevel > 0) && Subtarget.hasFMAF64() && (FMAContractLevel >= 1);
65 (OptLevel > 0) && Subtarget.hasFMAF32() && (FMAContractLevel == 2);
67 (OptLevel > 0) && Subtarget.hasFMAF64() && (FMAContractLevel == 2);
69 allowFMA = (FMAContractLevel >= 1);
71 doMulWide = (OptLevel > 0);
74 int NVPTXDAGToDAGISel::getDivF32Level() const {
75 if (UsePrecDivF32.getNumOccurrences() > 0) {
76 // If nvptx-prec-div32=N is used on the command-line, always honor it
79 // Otherwise, use div.approx if fast math is enabled
80 if (TM.Options.UnsafeFPMath)
87 bool NVPTXDAGToDAGISel::usePrecSqrtF32() const {
88 if (UsePrecSqrtF32.getNumOccurrences() > 0) {
89 // If nvptx-prec-sqrtf32 is used on the command-line, always honor it
90 return UsePrecSqrtF32;
92 // Otherwise, use sqrt.approx if fast math is enabled
93 if (TM.Options.UnsafeFPMath)
100 bool NVPTXDAGToDAGISel::useF32FTZ() const {
101 if (FtzEnabled.getNumOccurrences() > 0) {
102 // If nvptx-f32ftz is used on the command-line, always honor it
105 const Function *F = MF->getFunction();
106 // Otherwise, check for an nvptx-f32ftz attribute on the function
107 if (F->hasFnAttribute("nvptx-f32ftz"))
108 return (F->getAttributes().getAttribute(AttributeSet::FunctionIndex,
110 .getValueAsString() == "true");
116 /// Select - Select instructions not customized! Used for
117 /// expanded, promoted and normal instructions.
118 SDNode *NVPTXDAGToDAGISel::Select(SDNode *N) {
120 if (N->isMachineOpcode()) {
122 return NULL; // Already selected.
125 SDNode *ResNode = NULL;
126 switch (N->getOpcode()) {
128 ResNode = SelectLoad(N);
131 ResNode = SelectStore(N);
133 case NVPTXISD::LoadV2:
134 case NVPTXISD::LoadV4:
135 ResNode = SelectLoadVector(N);
137 case NVPTXISD::LDGV2:
138 case NVPTXISD::LDGV4:
139 case NVPTXISD::LDUV2:
140 case NVPTXISD::LDUV4:
141 ResNode = SelectLDGLDUVector(N);
143 case NVPTXISD::StoreV2:
144 case NVPTXISD::StoreV4:
145 ResNode = SelectStoreVector(N);
147 case NVPTXISD::LoadParam:
148 case NVPTXISD::LoadParamV2:
149 case NVPTXISD::LoadParamV4:
150 ResNode = SelectLoadParam(N);
152 case NVPTXISD::StoreRetval:
153 case NVPTXISD::StoreRetvalV2:
154 case NVPTXISD::StoreRetvalV4:
155 ResNode = SelectStoreRetval(N);
157 case NVPTXISD::StoreParam:
158 case NVPTXISD::StoreParamV2:
159 case NVPTXISD::StoreParamV4:
160 case NVPTXISD::StoreParamS32:
161 case NVPTXISD::StoreParamU32:
162 ResNode = SelectStoreParam(N);
164 case ISD::INTRINSIC_WO_CHAIN:
165 ResNode = SelectIntrinsicNoChain(N);
167 case NVPTXISD::Tex1DFloatI32:
168 case NVPTXISD::Tex1DFloatFloat:
169 case NVPTXISD::Tex1DFloatFloatLevel:
170 case NVPTXISD::Tex1DFloatFloatGrad:
171 case NVPTXISD::Tex1DI32I32:
172 case NVPTXISD::Tex1DI32Float:
173 case NVPTXISD::Tex1DI32FloatLevel:
174 case NVPTXISD::Tex1DI32FloatGrad:
175 case NVPTXISD::Tex1DArrayFloatI32:
176 case NVPTXISD::Tex1DArrayFloatFloat:
177 case NVPTXISD::Tex1DArrayFloatFloatLevel:
178 case NVPTXISD::Tex1DArrayFloatFloatGrad:
179 case NVPTXISD::Tex1DArrayI32I32:
180 case NVPTXISD::Tex1DArrayI32Float:
181 case NVPTXISD::Tex1DArrayI32FloatLevel:
182 case NVPTXISD::Tex1DArrayI32FloatGrad:
183 case NVPTXISD::Tex2DFloatI32:
184 case NVPTXISD::Tex2DFloatFloat:
185 case NVPTXISD::Tex2DFloatFloatLevel:
186 case NVPTXISD::Tex2DFloatFloatGrad:
187 case NVPTXISD::Tex2DI32I32:
188 case NVPTXISD::Tex2DI32Float:
189 case NVPTXISD::Tex2DI32FloatLevel:
190 case NVPTXISD::Tex2DI32FloatGrad:
191 case NVPTXISD::Tex2DArrayFloatI32:
192 case NVPTXISD::Tex2DArrayFloatFloat:
193 case NVPTXISD::Tex2DArrayFloatFloatLevel:
194 case NVPTXISD::Tex2DArrayFloatFloatGrad:
195 case NVPTXISD::Tex2DArrayI32I32:
196 case NVPTXISD::Tex2DArrayI32Float:
197 case NVPTXISD::Tex2DArrayI32FloatLevel:
198 case NVPTXISD::Tex2DArrayI32FloatGrad:
199 case NVPTXISD::Tex3DFloatI32:
200 case NVPTXISD::Tex3DFloatFloat:
201 case NVPTXISD::Tex3DFloatFloatLevel:
202 case NVPTXISD::Tex3DFloatFloatGrad:
203 case NVPTXISD::Tex3DI32I32:
204 case NVPTXISD::Tex3DI32Float:
205 case NVPTXISD::Tex3DI32FloatLevel:
206 case NVPTXISD::Tex3DI32FloatGrad:
207 ResNode = SelectTextureIntrinsic(N);
209 case NVPTXISD::Suld1DI8Trap:
210 case NVPTXISD::Suld1DI16Trap:
211 case NVPTXISD::Suld1DI32Trap:
212 case NVPTXISD::Suld1DV2I8Trap:
213 case NVPTXISD::Suld1DV2I16Trap:
214 case NVPTXISD::Suld1DV2I32Trap:
215 case NVPTXISD::Suld1DV4I8Trap:
216 case NVPTXISD::Suld1DV4I16Trap:
217 case NVPTXISD::Suld1DV4I32Trap:
218 case NVPTXISD::Suld1DArrayI8Trap:
219 case NVPTXISD::Suld1DArrayI16Trap:
220 case NVPTXISD::Suld1DArrayI32Trap:
221 case NVPTXISD::Suld1DArrayV2I8Trap:
222 case NVPTXISD::Suld1DArrayV2I16Trap:
223 case NVPTXISD::Suld1DArrayV2I32Trap:
224 case NVPTXISD::Suld1DArrayV4I8Trap:
225 case NVPTXISD::Suld1DArrayV4I16Trap:
226 case NVPTXISD::Suld1DArrayV4I32Trap:
227 case NVPTXISD::Suld2DI8Trap:
228 case NVPTXISD::Suld2DI16Trap:
229 case NVPTXISD::Suld2DI32Trap:
230 case NVPTXISD::Suld2DV2I8Trap:
231 case NVPTXISD::Suld2DV2I16Trap:
232 case NVPTXISD::Suld2DV2I32Trap:
233 case NVPTXISD::Suld2DV4I8Trap:
234 case NVPTXISD::Suld2DV4I16Trap:
235 case NVPTXISD::Suld2DV4I32Trap:
236 case NVPTXISD::Suld2DArrayI8Trap:
237 case NVPTXISD::Suld2DArrayI16Trap:
238 case NVPTXISD::Suld2DArrayI32Trap:
239 case NVPTXISD::Suld2DArrayV2I8Trap:
240 case NVPTXISD::Suld2DArrayV2I16Trap:
241 case NVPTXISD::Suld2DArrayV2I32Trap:
242 case NVPTXISD::Suld2DArrayV4I8Trap:
243 case NVPTXISD::Suld2DArrayV4I16Trap:
244 case NVPTXISD::Suld2DArrayV4I32Trap:
245 case NVPTXISD::Suld3DI8Trap:
246 case NVPTXISD::Suld3DI16Trap:
247 case NVPTXISD::Suld3DI32Trap:
248 case NVPTXISD::Suld3DV2I8Trap:
249 case NVPTXISD::Suld3DV2I16Trap:
250 case NVPTXISD::Suld3DV2I32Trap:
251 case NVPTXISD::Suld3DV4I8Trap:
252 case NVPTXISD::Suld3DV4I16Trap:
253 case NVPTXISD::Suld3DV4I32Trap:
254 ResNode = SelectSurfaceIntrinsic(N);
256 case ISD::ADDRSPACECAST:
257 ResNode = SelectAddrSpaceCast(N);
264 return SelectCode(N);
267 static unsigned int getCodeAddrSpace(MemSDNode *N,
268 const NVPTXSubtarget &Subtarget) {
269 const Value *Src = N->getMemOperand()->getValue();
272 return NVPTX::PTXLdStInstCode::GENERIC;
274 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) {
275 switch (PT->getAddressSpace()) {
276 case llvm::ADDRESS_SPACE_LOCAL: return NVPTX::PTXLdStInstCode::LOCAL;
277 case llvm::ADDRESS_SPACE_GLOBAL: return NVPTX::PTXLdStInstCode::GLOBAL;
278 case llvm::ADDRESS_SPACE_SHARED: return NVPTX::PTXLdStInstCode::SHARED;
279 case llvm::ADDRESS_SPACE_GENERIC: return NVPTX::PTXLdStInstCode::GENERIC;
280 case llvm::ADDRESS_SPACE_PARAM: return NVPTX::PTXLdStInstCode::PARAM;
281 case llvm::ADDRESS_SPACE_CONST: return NVPTX::PTXLdStInstCode::CONSTANT;
285 return NVPTX::PTXLdStInstCode::GENERIC;
288 SDNode *NVPTXDAGToDAGISel::SelectIntrinsicNoChain(SDNode *N) {
289 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
293 case Intrinsic::nvvm_texsurf_handle_internal:
294 return SelectTexSurfHandle(N);
298 SDNode *NVPTXDAGToDAGISel::SelectTexSurfHandle(SDNode *N) {
299 // Op 0 is the intrinsic ID
300 SDValue Wrapper = N->getOperand(1);
301 SDValue GlobalVal = Wrapper.getOperand(0);
302 return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64,
306 SDNode *NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
307 SDValue Src = N->getOperand(0);
308 AddrSpaceCastSDNode *CastN = cast<AddrSpaceCastSDNode>(N);
309 unsigned SrcAddrSpace = CastN->getSrcAddressSpace();
310 unsigned DstAddrSpace = CastN->getDestAddressSpace();
312 assert(SrcAddrSpace != DstAddrSpace &&
313 "addrspacecast must be between different address spaces");
315 if (DstAddrSpace == ADDRESS_SPACE_GENERIC) {
316 // Specific to generic
318 switch (SrcAddrSpace) {
319 default: report_fatal_error("Bad address space in addrspacecast");
320 case ADDRESS_SPACE_GLOBAL:
321 Opc = Subtarget.is64Bit() ? NVPTX::cvta_global_yes_64
322 : NVPTX::cvta_global_yes;
324 case ADDRESS_SPACE_SHARED:
325 Opc = Subtarget.is64Bit() ? NVPTX::cvta_shared_yes_64
326 : NVPTX::cvta_shared_yes;
328 case ADDRESS_SPACE_CONST:
329 Opc = Subtarget.is64Bit() ? NVPTX::cvta_const_yes_64
330 : NVPTX::cvta_const_yes;
332 case ADDRESS_SPACE_LOCAL:
333 Opc = Subtarget.is64Bit() ? NVPTX::cvta_local_yes_64
334 : NVPTX::cvta_local_yes;
337 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
339 // Generic to specific
340 if (SrcAddrSpace != 0)
341 report_fatal_error("Cannot cast between two non-generic address spaces");
343 switch (DstAddrSpace) {
344 default: report_fatal_error("Bad address space in addrspacecast");
345 case ADDRESS_SPACE_GLOBAL:
346 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_global_yes_64
347 : NVPTX::cvta_to_global_yes;
349 case ADDRESS_SPACE_SHARED:
350 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_shared_yes_64
351 : NVPTX::cvta_to_shared_yes;
353 case ADDRESS_SPACE_CONST:
354 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_const_yes_64
355 : NVPTX::cvta_to_const_yes;
357 case ADDRESS_SPACE_LOCAL:
358 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_local_yes_64
359 : NVPTX::cvta_to_local_yes;
362 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
366 SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
368 LoadSDNode *LD = cast<LoadSDNode>(N);
369 EVT LoadedVT = LD->getMemoryVT();
370 SDNode *NVPTXLD = NULL;
372 // do not support pre/post inc/dec
376 if (!LoadedVT.isSimple())
379 // Address Space Setting
380 unsigned int codeAddrSpace = getCodeAddrSpace(LD, Subtarget);
383 // - .volatile is only availalble for .global and .shared
384 bool isVolatile = LD->isVolatile();
385 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
386 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
387 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
391 MVT SimpleVT = LoadedVT.getSimpleVT();
392 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
393 if (SimpleVT.isVector()) {
394 unsigned num = SimpleVT.getVectorNumElements();
396 vecType = NVPTX::PTXLdStInstCode::V2;
398 vecType = NVPTX::PTXLdStInstCode::V4;
403 // Type Setting: fromType + fromTypeWidth
405 // Sign : ISD::SEXTLOAD
406 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
408 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
409 MVT ScalarVT = SimpleVT.getScalarType();
410 // Read at least 8 bits (predicates are stored as 8-bit values)
411 unsigned fromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
412 unsigned int fromType;
413 if ((LD->getExtensionType() == ISD::SEXTLOAD))
414 fromType = NVPTX::PTXLdStInstCode::Signed;
415 else if (ScalarVT.isFloatingPoint())
416 fromType = NVPTX::PTXLdStInstCode::Float;
418 fromType = NVPTX::PTXLdStInstCode::Unsigned;
420 // Create the machine instruction DAG
421 SDValue Chain = N->getOperand(0);
422 SDValue N1 = N->getOperand(1);
424 SDValue Offset, Base;
426 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
428 if (SelectDirectAddr(N1, Addr)) {
431 Opcode = NVPTX::LD_i8_avar;
434 Opcode = NVPTX::LD_i16_avar;
437 Opcode = NVPTX::LD_i32_avar;
440 Opcode = NVPTX::LD_i64_avar;
443 Opcode = NVPTX::LD_f32_avar;
446 Opcode = NVPTX::LD_f64_avar;
451 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
452 getI32Imm(vecType), getI32Imm(fromType),
453 getI32Imm(fromTypeWidth), Addr, Chain };
454 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
455 } else if (Subtarget.is64Bit()
456 ? SelectADDRsi64(N1.getNode(), N1, Base, Offset)
457 : SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
460 Opcode = NVPTX::LD_i8_asi;
463 Opcode = NVPTX::LD_i16_asi;
466 Opcode = NVPTX::LD_i32_asi;
469 Opcode = NVPTX::LD_i64_asi;
472 Opcode = NVPTX::LD_f32_asi;
475 Opcode = NVPTX::LD_f64_asi;
480 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
481 getI32Imm(vecType), getI32Imm(fromType),
482 getI32Imm(fromTypeWidth), Base, Offset, Chain };
483 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
484 } else if (Subtarget.is64Bit()
485 ? SelectADDRri64(N1.getNode(), N1, Base, Offset)
486 : SelectADDRri(N1.getNode(), N1, Base, Offset)) {
487 if (Subtarget.is64Bit()) {
490 Opcode = NVPTX::LD_i8_ari_64;
493 Opcode = NVPTX::LD_i16_ari_64;
496 Opcode = NVPTX::LD_i32_ari_64;
499 Opcode = NVPTX::LD_i64_ari_64;
502 Opcode = NVPTX::LD_f32_ari_64;
505 Opcode = NVPTX::LD_f64_ari_64;
513 Opcode = NVPTX::LD_i8_ari;
516 Opcode = NVPTX::LD_i16_ari;
519 Opcode = NVPTX::LD_i32_ari;
522 Opcode = NVPTX::LD_i64_ari;
525 Opcode = NVPTX::LD_f32_ari;
528 Opcode = NVPTX::LD_f64_ari;
534 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
535 getI32Imm(vecType), getI32Imm(fromType),
536 getI32Imm(fromTypeWidth), Base, Offset, Chain };
537 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
539 if (Subtarget.is64Bit()) {
542 Opcode = NVPTX::LD_i8_areg_64;
545 Opcode = NVPTX::LD_i16_areg_64;
548 Opcode = NVPTX::LD_i32_areg_64;
551 Opcode = NVPTX::LD_i64_areg_64;
554 Opcode = NVPTX::LD_f32_areg_64;
557 Opcode = NVPTX::LD_f64_areg_64;
565 Opcode = NVPTX::LD_i8_areg;
568 Opcode = NVPTX::LD_i16_areg;
571 Opcode = NVPTX::LD_i32_areg;
574 Opcode = NVPTX::LD_i64_areg;
577 Opcode = NVPTX::LD_f32_areg;
580 Opcode = NVPTX::LD_f64_areg;
586 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
587 getI32Imm(vecType), getI32Imm(fromType),
588 getI32Imm(fromTypeWidth), N1, Chain };
589 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
592 if (NVPTXLD != NULL) {
593 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
594 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
595 cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
601 SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
603 SDValue Chain = N->getOperand(0);
604 SDValue Op1 = N->getOperand(1);
605 SDValue Addr, Offset, Base;
609 MemSDNode *MemSD = cast<MemSDNode>(N);
610 EVT LoadedVT = MemSD->getMemoryVT();
612 if (!LoadedVT.isSimple())
615 // Address Space Setting
616 unsigned int CodeAddrSpace = getCodeAddrSpace(MemSD, Subtarget);
619 // - .volatile is only availalble for .global and .shared
620 bool IsVolatile = MemSD->isVolatile();
621 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
622 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
623 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
627 MVT SimpleVT = LoadedVT.getSimpleVT();
629 // Type Setting: fromType + fromTypeWidth
631 // Sign : ISD::SEXTLOAD
632 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
634 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
635 MVT ScalarVT = SimpleVT.getScalarType();
636 // Read at least 8 bits (predicates are stored as 8-bit values)
637 unsigned FromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
638 unsigned int FromType;
639 // The last operand holds the original LoadSDNode::getExtensionType() value
640 unsigned ExtensionType = cast<ConstantSDNode>(
641 N->getOperand(N->getNumOperands() - 1))->getZExtValue();
642 if (ExtensionType == ISD::SEXTLOAD)
643 FromType = NVPTX::PTXLdStInstCode::Signed;
644 else if (ScalarVT.isFloatingPoint())
645 FromType = NVPTX::PTXLdStInstCode::Float;
647 FromType = NVPTX::PTXLdStInstCode::Unsigned;
651 switch (N->getOpcode()) {
652 case NVPTXISD::LoadV2:
653 VecType = NVPTX::PTXLdStInstCode::V2;
655 case NVPTXISD::LoadV4:
656 VecType = NVPTX::PTXLdStInstCode::V4;
662 EVT EltVT = N->getValueType(0);
664 if (SelectDirectAddr(Op1, Addr)) {
665 switch (N->getOpcode()) {
668 case NVPTXISD::LoadV2:
669 switch (EltVT.getSimpleVT().SimpleTy) {
673 Opcode = NVPTX::LDV_i8_v2_avar;
676 Opcode = NVPTX::LDV_i16_v2_avar;
679 Opcode = NVPTX::LDV_i32_v2_avar;
682 Opcode = NVPTX::LDV_i64_v2_avar;
685 Opcode = NVPTX::LDV_f32_v2_avar;
688 Opcode = NVPTX::LDV_f64_v2_avar;
692 case NVPTXISD::LoadV4:
693 switch (EltVT.getSimpleVT().SimpleTy) {
697 Opcode = NVPTX::LDV_i8_v4_avar;
700 Opcode = NVPTX::LDV_i16_v4_avar;
703 Opcode = NVPTX::LDV_i32_v4_avar;
706 Opcode = NVPTX::LDV_f32_v4_avar;
712 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
713 getI32Imm(VecType), getI32Imm(FromType),
714 getI32Imm(FromTypeWidth), Addr, Chain };
715 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
716 } else if (Subtarget.is64Bit()
717 ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset)
718 : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
719 switch (N->getOpcode()) {
722 case NVPTXISD::LoadV2:
723 switch (EltVT.getSimpleVT().SimpleTy) {
727 Opcode = NVPTX::LDV_i8_v2_asi;
730 Opcode = NVPTX::LDV_i16_v2_asi;
733 Opcode = NVPTX::LDV_i32_v2_asi;
736 Opcode = NVPTX::LDV_i64_v2_asi;
739 Opcode = NVPTX::LDV_f32_v2_asi;
742 Opcode = NVPTX::LDV_f64_v2_asi;
746 case NVPTXISD::LoadV4:
747 switch (EltVT.getSimpleVT().SimpleTy) {
751 Opcode = NVPTX::LDV_i8_v4_asi;
754 Opcode = NVPTX::LDV_i16_v4_asi;
757 Opcode = NVPTX::LDV_i32_v4_asi;
760 Opcode = NVPTX::LDV_f32_v4_asi;
766 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
767 getI32Imm(VecType), getI32Imm(FromType),
768 getI32Imm(FromTypeWidth), Base, Offset, Chain };
769 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
770 } else if (Subtarget.is64Bit()
771 ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
772 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
773 if (Subtarget.is64Bit()) {
774 switch (N->getOpcode()) {
777 case NVPTXISD::LoadV2:
778 switch (EltVT.getSimpleVT().SimpleTy) {
782 Opcode = NVPTX::LDV_i8_v2_ari_64;
785 Opcode = NVPTX::LDV_i16_v2_ari_64;
788 Opcode = NVPTX::LDV_i32_v2_ari_64;
791 Opcode = NVPTX::LDV_i64_v2_ari_64;
794 Opcode = NVPTX::LDV_f32_v2_ari_64;
797 Opcode = NVPTX::LDV_f64_v2_ari_64;
801 case NVPTXISD::LoadV4:
802 switch (EltVT.getSimpleVT().SimpleTy) {
806 Opcode = NVPTX::LDV_i8_v4_ari_64;
809 Opcode = NVPTX::LDV_i16_v4_ari_64;
812 Opcode = NVPTX::LDV_i32_v4_ari_64;
815 Opcode = NVPTX::LDV_f32_v4_ari_64;
821 switch (N->getOpcode()) {
824 case NVPTXISD::LoadV2:
825 switch (EltVT.getSimpleVT().SimpleTy) {
829 Opcode = NVPTX::LDV_i8_v2_ari;
832 Opcode = NVPTX::LDV_i16_v2_ari;
835 Opcode = NVPTX::LDV_i32_v2_ari;
838 Opcode = NVPTX::LDV_i64_v2_ari;
841 Opcode = NVPTX::LDV_f32_v2_ari;
844 Opcode = NVPTX::LDV_f64_v2_ari;
848 case NVPTXISD::LoadV4:
849 switch (EltVT.getSimpleVT().SimpleTy) {
853 Opcode = NVPTX::LDV_i8_v4_ari;
856 Opcode = NVPTX::LDV_i16_v4_ari;
859 Opcode = NVPTX::LDV_i32_v4_ari;
862 Opcode = NVPTX::LDV_f32_v4_ari;
869 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
870 getI32Imm(VecType), getI32Imm(FromType),
871 getI32Imm(FromTypeWidth), Base, Offset, Chain };
873 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
875 if (Subtarget.is64Bit()) {
876 switch (N->getOpcode()) {
879 case NVPTXISD::LoadV2:
880 switch (EltVT.getSimpleVT().SimpleTy) {
884 Opcode = NVPTX::LDV_i8_v2_areg_64;
887 Opcode = NVPTX::LDV_i16_v2_areg_64;
890 Opcode = NVPTX::LDV_i32_v2_areg_64;
893 Opcode = NVPTX::LDV_i64_v2_areg_64;
896 Opcode = NVPTX::LDV_f32_v2_areg_64;
899 Opcode = NVPTX::LDV_f64_v2_areg_64;
903 case NVPTXISD::LoadV4:
904 switch (EltVT.getSimpleVT().SimpleTy) {
908 Opcode = NVPTX::LDV_i8_v4_areg_64;
911 Opcode = NVPTX::LDV_i16_v4_areg_64;
914 Opcode = NVPTX::LDV_i32_v4_areg_64;
917 Opcode = NVPTX::LDV_f32_v4_areg_64;
923 switch (N->getOpcode()) {
926 case NVPTXISD::LoadV2:
927 switch (EltVT.getSimpleVT().SimpleTy) {
931 Opcode = NVPTX::LDV_i8_v2_areg;
934 Opcode = NVPTX::LDV_i16_v2_areg;
937 Opcode = NVPTX::LDV_i32_v2_areg;
940 Opcode = NVPTX::LDV_i64_v2_areg;
943 Opcode = NVPTX::LDV_f32_v2_areg;
946 Opcode = NVPTX::LDV_f64_v2_areg;
950 case NVPTXISD::LoadV4:
951 switch (EltVT.getSimpleVT().SimpleTy) {
955 Opcode = NVPTX::LDV_i8_v4_areg;
958 Opcode = NVPTX::LDV_i16_v4_areg;
961 Opcode = NVPTX::LDV_i32_v4_areg;
964 Opcode = NVPTX::LDV_f32_v4_areg;
971 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
972 getI32Imm(VecType), getI32Imm(FromType),
973 getI32Imm(FromTypeWidth), Op1, Chain };
974 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
977 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
978 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
979 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
984 SDNode *NVPTXDAGToDAGISel::SelectLDGLDUVector(SDNode *N) {
986 SDValue Chain = N->getOperand(0);
987 SDValue Op1 = N->getOperand(1);
991 MemSDNode *Mem = cast<MemSDNode>(N);
992 SDValue Base, Offset, Addr;
994 EVT EltVT = Mem->getMemoryVT().getVectorElementType();
996 if (SelectDirectAddr(Op1, Addr)) {
997 switch (N->getOpcode()) {
1000 case NVPTXISD::LDGV2:
1001 switch (EltVT.getSimpleVT().SimpleTy) {
1005 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_avar;
1008 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_avar;
1011 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_avar;
1014 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_avar;
1017 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_avar;
1020 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_avar;
1024 case NVPTXISD::LDUV2:
1025 switch (EltVT.getSimpleVT().SimpleTy) {
1029 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_avar;
1032 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_avar;
1035 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_avar;
1038 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_avar;
1041 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_avar;
1044 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_avar;
1048 case NVPTXISD::LDGV4:
1049 switch (EltVT.getSimpleVT().SimpleTy) {
1053 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_avar;
1056 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_avar;
1059 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_avar;
1062 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_avar;
1066 case NVPTXISD::LDUV4:
1067 switch (EltVT.getSimpleVT().SimpleTy) {
1071 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_avar;
1074 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_avar;
1077 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_avar;
1080 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_avar;
1086 SDValue Ops[] = { Addr, Chain };
1087 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
1088 ArrayRef<SDValue>(Ops, 2));
1089 } else if (Subtarget.is64Bit()
1090 ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1091 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1092 if (Subtarget.is64Bit()) {
1093 switch (N->getOpcode()) {
1096 case NVPTXISD::LDGV2:
1097 switch (EltVT.getSimpleVT().SimpleTy) {
1101 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari64;
1104 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari64;
1107 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari64;
1110 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari64;
1113 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari64;
1116 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari64;
1120 case NVPTXISD::LDUV2:
1121 switch (EltVT.getSimpleVT().SimpleTy) {
1125 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari64;
1128 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari64;
1131 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari64;
1134 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari64;
1137 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari64;
1140 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari64;
1144 case NVPTXISD::LDGV4:
1145 switch (EltVT.getSimpleVT().SimpleTy) {
1149 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari64;
1152 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari64;
1155 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari64;
1158 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari64;
1162 case NVPTXISD::LDUV4:
1163 switch (EltVT.getSimpleVT().SimpleTy) {
1167 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari64;
1170 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari64;
1173 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari64;
1176 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari64;
1182 switch (N->getOpcode()) {
1185 case NVPTXISD::LDGV2:
1186 switch (EltVT.getSimpleVT().SimpleTy) {
1190 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari32;
1193 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari32;
1196 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari32;
1199 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari32;
1202 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari32;
1205 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari32;
1209 case NVPTXISD::LDUV2:
1210 switch (EltVT.getSimpleVT().SimpleTy) {
1214 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari32;
1217 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari32;
1220 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari32;
1223 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari32;
1226 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari32;
1229 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari32;
1233 case NVPTXISD::LDGV4:
1234 switch (EltVT.getSimpleVT().SimpleTy) {
1238 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari32;
1241 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari32;
1244 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari32;
1247 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari32;
1251 case NVPTXISD::LDUV4:
1252 switch (EltVT.getSimpleVT().SimpleTy) {
1256 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari32;
1259 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari32;
1262 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari32;
1265 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari32;
1272 SDValue Ops[] = { Base, Offset, Chain };
1274 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
1275 ArrayRef<SDValue>(Ops, 3));
1277 if (Subtarget.is64Bit()) {
1278 switch (N->getOpcode()) {
1281 case NVPTXISD::LDGV2:
1282 switch (EltVT.getSimpleVT().SimpleTy) {
1286 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg64;
1289 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg64;
1292 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg64;
1295 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg64;
1298 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg64;
1301 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg64;
1305 case NVPTXISD::LDUV2:
1306 switch (EltVT.getSimpleVT().SimpleTy) {
1310 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg64;
1313 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg64;
1316 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg64;
1319 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg64;
1322 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg64;
1325 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg64;
1329 case NVPTXISD::LDGV4:
1330 switch (EltVT.getSimpleVT().SimpleTy) {
1334 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64;
1337 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg64;
1340 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg64;
1343 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg64;
1347 case NVPTXISD::LDUV4:
1348 switch (EltVT.getSimpleVT().SimpleTy) {
1352 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64;
1355 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg64;
1358 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg64;
1361 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg64;
1367 switch (N->getOpcode()) {
1370 case NVPTXISD::LDGV2:
1371 switch (EltVT.getSimpleVT().SimpleTy) {
1375 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg32;
1378 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg32;
1381 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg32;
1384 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg32;
1387 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg32;
1390 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg32;
1394 case NVPTXISD::LDUV2:
1395 switch (EltVT.getSimpleVT().SimpleTy) {
1399 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg32;
1402 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg32;
1405 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg32;
1408 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg32;
1411 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg32;
1414 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg32;
1418 case NVPTXISD::LDGV4:
1419 switch (EltVT.getSimpleVT().SimpleTy) {
1423 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32;
1426 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg32;
1429 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg32;
1432 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg32;
1436 case NVPTXISD::LDUV4:
1437 switch (EltVT.getSimpleVT().SimpleTy) {
1441 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32;
1444 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg32;
1447 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg32;
1450 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg32;
1457 SDValue Ops[] = { Op1, Chain };
1458 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
1459 ArrayRef<SDValue>(Ops, 2));
1462 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1463 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
1464 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1469 SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
1471 StoreSDNode *ST = cast<StoreSDNode>(N);
1472 EVT StoreVT = ST->getMemoryVT();
1473 SDNode *NVPTXST = NULL;
1475 // do not support pre/post inc/dec
1476 if (ST->isIndexed())
1479 if (!StoreVT.isSimple())
1482 // Address Space Setting
1483 unsigned int codeAddrSpace = getCodeAddrSpace(ST, Subtarget);
1486 // - .volatile is only availalble for .global and .shared
1487 bool isVolatile = ST->isVolatile();
1488 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
1489 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
1490 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
1494 MVT SimpleVT = StoreVT.getSimpleVT();
1495 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
1496 if (SimpleVT.isVector()) {
1497 unsigned num = SimpleVT.getVectorNumElements();
1499 vecType = NVPTX::PTXLdStInstCode::V2;
1501 vecType = NVPTX::PTXLdStInstCode::V4;
1506 // Type Setting: toType + toTypeWidth
1507 // - for integer type, always use 'u'
1509 MVT ScalarVT = SimpleVT.getScalarType();
1510 unsigned toTypeWidth = ScalarVT.getSizeInBits();
1511 unsigned int toType;
1512 if (ScalarVT.isFloatingPoint())
1513 toType = NVPTX::PTXLdStInstCode::Float;
1515 toType = NVPTX::PTXLdStInstCode::Unsigned;
1517 // Create the machine instruction DAG
1518 SDValue Chain = N->getOperand(0);
1519 SDValue N1 = N->getOperand(1);
1520 SDValue N2 = N->getOperand(2);
1522 SDValue Offset, Base;
1524 MVT::SimpleValueType SourceVT = N1.getNode()->getSimpleValueType(0).SimpleTy;
1526 if (SelectDirectAddr(N2, Addr)) {
1529 Opcode = NVPTX::ST_i8_avar;
1532 Opcode = NVPTX::ST_i16_avar;
1535 Opcode = NVPTX::ST_i32_avar;
1538 Opcode = NVPTX::ST_i64_avar;
1541 Opcode = NVPTX::ST_f32_avar;
1544 Opcode = NVPTX::ST_f64_avar;
1549 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
1550 getI32Imm(vecType), getI32Imm(toType),
1551 getI32Imm(toTypeWidth), Addr, Chain };
1552 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
1553 } else if (Subtarget.is64Bit()
1554 ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
1555 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
1558 Opcode = NVPTX::ST_i8_asi;
1561 Opcode = NVPTX::ST_i16_asi;
1564 Opcode = NVPTX::ST_i32_asi;
1567 Opcode = NVPTX::ST_i64_asi;
1570 Opcode = NVPTX::ST_f32_asi;
1573 Opcode = NVPTX::ST_f64_asi;
1578 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
1579 getI32Imm(vecType), getI32Imm(toType),
1580 getI32Imm(toTypeWidth), Base, Offset, Chain };
1581 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
1582 } else if (Subtarget.is64Bit()
1583 ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
1584 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
1585 if (Subtarget.is64Bit()) {
1588 Opcode = NVPTX::ST_i8_ari_64;
1591 Opcode = NVPTX::ST_i16_ari_64;
1594 Opcode = NVPTX::ST_i32_ari_64;
1597 Opcode = NVPTX::ST_i64_ari_64;
1600 Opcode = NVPTX::ST_f32_ari_64;
1603 Opcode = NVPTX::ST_f64_ari_64;
1611 Opcode = NVPTX::ST_i8_ari;
1614 Opcode = NVPTX::ST_i16_ari;
1617 Opcode = NVPTX::ST_i32_ari;
1620 Opcode = NVPTX::ST_i64_ari;
1623 Opcode = NVPTX::ST_f32_ari;
1626 Opcode = NVPTX::ST_f64_ari;
1632 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
1633 getI32Imm(vecType), getI32Imm(toType),
1634 getI32Imm(toTypeWidth), Base, Offset, Chain };
1635 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
1637 if (Subtarget.is64Bit()) {
1640 Opcode = NVPTX::ST_i8_areg_64;
1643 Opcode = NVPTX::ST_i16_areg_64;
1646 Opcode = NVPTX::ST_i32_areg_64;
1649 Opcode = NVPTX::ST_i64_areg_64;
1652 Opcode = NVPTX::ST_f32_areg_64;
1655 Opcode = NVPTX::ST_f64_areg_64;
1663 Opcode = NVPTX::ST_i8_areg;
1666 Opcode = NVPTX::ST_i16_areg;
1669 Opcode = NVPTX::ST_i32_areg;
1672 Opcode = NVPTX::ST_i64_areg;
1675 Opcode = NVPTX::ST_f32_areg;
1678 Opcode = NVPTX::ST_f64_areg;
1684 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
1685 getI32Imm(vecType), getI32Imm(toType),
1686 getI32Imm(toTypeWidth), N2, Chain };
1687 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
1690 if (NVPTXST != NULL) {
1691 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1692 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
1693 cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
1699 SDNode *NVPTXDAGToDAGISel::SelectStoreVector(SDNode *N) {
1700 SDValue Chain = N->getOperand(0);
1701 SDValue Op1 = N->getOperand(1);
1702 SDValue Addr, Offset, Base;
1706 EVT EltVT = Op1.getValueType();
1707 MemSDNode *MemSD = cast<MemSDNode>(N);
1708 EVT StoreVT = MemSD->getMemoryVT();
1710 // Address Space Setting
1711 unsigned CodeAddrSpace = getCodeAddrSpace(MemSD, Subtarget);
1713 if (CodeAddrSpace == NVPTX::PTXLdStInstCode::CONSTANT) {
1714 report_fatal_error("Cannot store to pointer that points to constant "
1719 // - .volatile is only availalble for .global and .shared
1720 bool IsVolatile = MemSD->isVolatile();
1721 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
1722 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
1723 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
1726 // Type Setting: toType + toTypeWidth
1727 // - for integer type, always use 'u'
1728 assert(StoreVT.isSimple() && "Store value is not simple");
1729 MVT ScalarVT = StoreVT.getSimpleVT().getScalarType();
1730 unsigned ToTypeWidth = ScalarVT.getSizeInBits();
1732 if (ScalarVT.isFloatingPoint())
1733 ToType = NVPTX::PTXLdStInstCode::Float;
1735 ToType = NVPTX::PTXLdStInstCode::Unsigned;
1737 SmallVector<SDValue, 12> StOps;
1741 switch (N->getOpcode()) {
1742 case NVPTXISD::StoreV2:
1743 VecType = NVPTX::PTXLdStInstCode::V2;
1744 StOps.push_back(N->getOperand(1));
1745 StOps.push_back(N->getOperand(2));
1746 N2 = N->getOperand(3);
1748 case NVPTXISD::StoreV4:
1749 VecType = NVPTX::PTXLdStInstCode::V4;
1750 StOps.push_back(N->getOperand(1));
1751 StOps.push_back(N->getOperand(2));
1752 StOps.push_back(N->getOperand(3));
1753 StOps.push_back(N->getOperand(4));
1754 N2 = N->getOperand(5);
1760 StOps.push_back(getI32Imm(IsVolatile));
1761 StOps.push_back(getI32Imm(CodeAddrSpace));
1762 StOps.push_back(getI32Imm(VecType));
1763 StOps.push_back(getI32Imm(ToType));
1764 StOps.push_back(getI32Imm(ToTypeWidth));
1766 if (SelectDirectAddr(N2, Addr)) {
1767 switch (N->getOpcode()) {
1770 case NVPTXISD::StoreV2:
1771 switch (EltVT.getSimpleVT().SimpleTy) {
1775 Opcode = NVPTX::STV_i8_v2_avar;
1778 Opcode = NVPTX::STV_i16_v2_avar;
1781 Opcode = NVPTX::STV_i32_v2_avar;
1784 Opcode = NVPTX::STV_i64_v2_avar;
1787 Opcode = NVPTX::STV_f32_v2_avar;
1790 Opcode = NVPTX::STV_f64_v2_avar;
1794 case NVPTXISD::StoreV4:
1795 switch (EltVT.getSimpleVT().SimpleTy) {
1799 Opcode = NVPTX::STV_i8_v4_avar;
1802 Opcode = NVPTX::STV_i16_v4_avar;
1805 Opcode = NVPTX::STV_i32_v4_avar;
1808 Opcode = NVPTX::STV_f32_v4_avar;
1813 StOps.push_back(Addr);
1814 } else if (Subtarget.is64Bit()
1815 ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
1816 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
1817 switch (N->getOpcode()) {
1820 case NVPTXISD::StoreV2:
1821 switch (EltVT.getSimpleVT().SimpleTy) {
1825 Opcode = NVPTX::STV_i8_v2_asi;
1828 Opcode = NVPTX::STV_i16_v2_asi;
1831 Opcode = NVPTX::STV_i32_v2_asi;
1834 Opcode = NVPTX::STV_i64_v2_asi;
1837 Opcode = NVPTX::STV_f32_v2_asi;
1840 Opcode = NVPTX::STV_f64_v2_asi;
1844 case NVPTXISD::StoreV4:
1845 switch (EltVT.getSimpleVT().SimpleTy) {
1849 Opcode = NVPTX::STV_i8_v4_asi;
1852 Opcode = NVPTX::STV_i16_v4_asi;
1855 Opcode = NVPTX::STV_i32_v4_asi;
1858 Opcode = NVPTX::STV_f32_v4_asi;
1863 StOps.push_back(Base);
1864 StOps.push_back(Offset);
1865 } else if (Subtarget.is64Bit()
1866 ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
1867 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
1868 if (Subtarget.is64Bit()) {
1869 switch (N->getOpcode()) {
1872 case NVPTXISD::StoreV2:
1873 switch (EltVT.getSimpleVT().SimpleTy) {
1877 Opcode = NVPTX::STV_i8_v2_ari_64;
1880 Opcode = NVPTX::STV_i16_v2_ari_64;
1883 Opcode = NVPTX::STV_i32_v2_ari_64;
1886 Opcode = NVPTX::STV_i64_v2_ari_64;
1889 Opcode = NVPTX::STV_f32_v2_ari_64;
1892 Opcode = NVPTX::STV_f64_v2_ari_64;
1896 case NVPTXISD::StoreV4:
1897 switch (EltVT.getSimpleVT().SimpleTy) {
1901 Opcode = NVPTX::STV_i8_v4_ari_64;
1904 Opcode = NVPTX::STV_i16_v4_ari_64;
1907 Opcode = NVPTX::STV_i32_v4_ari_64;
1910 Opcode = NVPTX::STV_f32_v4_ari_64;
1916 switch (N->getOpcode()) {
1919 case NVPTXISD::StoreV2:
1920 switch (EltVT.getSimpleVT().SimpleTy) {
1924 Opcode = NVPTX::STV_i8_v2_ari;
1927 Opcode = NVPTX::STV_i16_v2_ari;
1930 Opcode = NVPTX::STV_i32_v2_ari;
1933 Opcode = NVPTX::STV_i64_v2_ari;
1936 Opcode = NVPTX::STV_f32_v2_ari;
1939 Opcode = NVPTX::STV_f64_v2_ari;
1943 case NVPTXISD::StoreV4:
1944 switch (EltVT.getSimpleVT().SimpleTy) {
1948 Opcode = NVPTX::STV_i8_v4_ari;
1951 Opcode = NVPTX::STV_i16_v4_ari;
1954 Opcode = NVPTX::STV_i32_v4_ari;
1957 Opcode = NVPTX::STV_f32_v4_ari;
1963 StOps.push_back(Base);
1964 StOps.push_back(Offset);
1966 if (Subtarget.is64Bit()) {
1967 switch (N->getOpcode()) {
1970 case NVPTXISD::StoreV2:
1971 switch (EltVT.getSimpleVT().SimpleTy) {
1975 Opcode = NVPTX::STV_i8_v2_areg_64;
1978 Opcode = NVPTX::STV_i16_v2_areg_64;
1981 Opcode = NVPTX::STV_i32_v2_areg_64;
1984 Opcode = NVPTX::STV_i64_v2_areg_64;
1987 Opcode = NVPTX::STV_f32_v2_areg_64;
1990 Opcode = NVPTX::STV_f64_v2_areg_64;
1994 case NVPTXISD::StoreV4:
1995 switch (EltVT.getSimpleVT().SimpleTy) {
1999 Opcode = NVPTX::STV_i8_v4_areg_64;
2002 Opcode = NVPTX::STV_i16_v4_areg_64;
2005 Opcode = NVPTX::STV_i32_v4_areg_64;
2008 Opcode = NVPTX::STV_f32_v4_areg_64;
2014 switch (N->getOpcode()) {
2017 case NVPTXISD::StoreV2:
2018 switch (EltVT.getSimpleVT().SimpleTy) {
2022 Opcode = NVPTX::STV_i8_v2_areg;
2025 Opcode = NVPTX::STV_i16_v2_areg;
2028 Opcode = NVPTX::STV_i32_v2_areg;
2031 Opcode = NVPTX::STV_i64_v2_areg;
2034 Opcode = NVPTX::STV_f32_v2_areg;
2037 Opcode = NVPTX::STV_f64_v2_areg;
2041 case NVPTXISD::StoreV4:
2042 switch (EltVT.getSimpleVT().SimpleTy) {
2046 Opcode = NVPTX::STV_i8_v4_areg;
2049 Opcode = NVPTX::STV_i16_v4_areg;
2052 Opcode = NVPTX::STV_i32_v4_areg;
2055 Opcode = NVPTX::STV_f32_v4_areg;
2061 StOps.push_back(N2);
2064 StOps.push_back(Chain);
2066 ST = CurDAG->getMachineNode(Opcode, DL, MVT::Other, StOps);
2068 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2069 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2070 cast<MachineSDNode>(ST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2075 SDNode *NVPTXDAGToDAGISel::SelectLoadParam(SDNode *Node) {
2076 SDValue Chain = Node->getOperand(0);
2077 SDValue Offset = Node->getOperand(2);
2078 SDValue Flag = Node->getOperand(3);
2080 MemSDNode *Mem = cast<MemSDNode>(Node);
2083 switch (Node->getOpcode()) {
2086 case NVPTXISD::LoadParam:
2089 case NVPTXISD::LoadParamV2:
2092 case NVPTXISD::LoadParamV4:
2097 EVT EltVT = Node->getValueType(0);
2098 EVT MemVT = Mem->getMemoryVT();
2106 switch (MemVT.getSimpleVT().SimpleTy) {
2110 Opc = NVPTX::LoadParamMemI8;
2113 Opc = NVPTX::LoadParamMemI8;
2116 Opc = NVPTX::LoadParamMemI16;
2119 Opc = NVPTX::LoadParamMemI32;
2122 Opc = NVPTX::LoadParamMemI64;
2125 Opc = NVPTX::LoadParamMemF32;
2128 Opc = NVPTX::LoadParamMemF64;
2133 switch (MemVT.getSimpleVT().SimpleTy) {
2137 Opc = NVPTX::LoadParamMemV2I8;
2140 Opc = NVPTX::LoadParamMemV2I8;
2143 Opc = NVPTX::LoadParamMemV2I16;
2146 Opc = NVPTX::LoadParamMemV2I32;
2149 Opc = NVPTX::LoadParamMemV2I64;
2152 Opc = NVPTX::LoadParamMemV2F32;
2155 Opc = NVPTX::LoadParamMemV2F64;
2160 switch (MemVT.getSimpleVT().SimpleTy) {
2164 Opc = NVPTX::LoadParamMemV4I8;
2167 Opc = NVPTX::LoadParamMemV4I8;
2170 Opc = NVPTX::LoadParamMemV4I16;
2173 Opc = NVPTX::LoadParamMemV4I32;
2176 Opc = NVPTX::LoadParamMemV4F32;
2184 VTs = CurDAG->getVTList(EltVT, MVT::Other, MVT::Glue);
2185 } else if (VecSize == 2) {
2186 VTs = CurDAG->getVTList(EltVT, EltVT, MVT::Other, MVT::Glue);
2188 EVT EVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other, MVT::Glue };
2189 VTs = CurDAG->getVTList(EVTs);
2192 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2194 SmallVector<SDValue, 2> Ops;
2195 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2196 Ops.push_back(Chain);
2197 Ops.push_back(Flag);
2200 CurDAG->getMachineNode(Opc, DL, VTs, Ops);
2204 SDNode *NVPTXDAGToDAGISel::SelectStoreRetval(SDNode *N) {
2206 SDValue Chain = N->getOperand(0);
2207 SDValue Offset = N->getOperand(1);
2208 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2209 MemSDNode *Mem = cast<MemSDNode>(N);
2211 // How many elements do we have?
2212 unsigned NumElts = 1;
2213 switch (N->getOpcode()) {
2216 case NVPTXISD::StoreRetval:
2219 case NVPTXISD::StoreRetvalV2:
2222 case NVPTXISD::StoreRetvalV4:
2227 // Build vector of operands
2228 SmallVector<SDValue, 6> Ops;
2229 for (unsigned i = 0; i < NumElts; ++i)
2230 Ops.push_back(N->getOperand(i + 2));
2231 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2232 Ops.push_back(Chain);
2234 // Determine target opcode
2235 // If we have an i1, use an 8-bit store. The lowering code in
2236 // NVPTXISelLowering will have already emitted an upcast.
2237 unsigned Opcode = 0;
2242 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2246 Opcode = NVPTX::StoreRetvalI8;
2249 Opcode = NVPTX::StoreRetvalI8;
2252 Opcode = NVPTX::StoreRetvalI16;
2255 Opcode = NVPTX::StoreRetvalI32;
2258 Opcode = NVPTX::StoreRetvalI64;
2261 Opcode = NVPTX::StoreRetvalF32;
2264 Opcode = NVPTX::StoreRetvalF64;
2269 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2273 Opcode = NVPTX::StoreRetvalV2I8;
2276 Opcode = NVPTX::StoreRetvalV2I8;
2279 Opcode = NVPTX::StoreRetvalV2I16;
2282 Opcode = NVPTX::StoreRetvalV2I32;
2285 Opcode = NVPTX::StoreRetvalV2I64;
2288 Opcode = NVPTX::StoreRetvalV2F32;
2291 Opcode = NVPTX::StoreRetvalV2F64;
2296 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2300 Opcode = NVPTX::StoreRetvalV4I8;
2303 Opcode = NVPTX::StoreRetvalV4I8;
2306 Opcode = NVPTX::StoreRetvalV4I16;
2309 Opcode = NVPTX::StoreRetvalV4I32;
2312 Opcode = NVPTX::StoreRetvalV4F32;
2319 CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
2320 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2321 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2322 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
2327 SDNode *NVPTXDAGToDAGISel::SelectStoreParam(SDNode *N) {
2329 SDValue Chain = N->getOperand(0);
2330 SDValue Param = N->getOperand(1);
2331 unsigned ParamVal = cast<ConstantSDNode>(Param)->getZExtValue();
2332 SDValue Offset = N->getOperand(2);
2333 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2334 MemSDNode *Mem = cast<MemSDNode>(N);
2335 SDValue Flag = N->getOperand(N->getNumOperands() - 1);
2337 // How many elements do we have?
2338 unsigned NumElts = 1;
2339 switch (N->getOpcode()) {
2342 case NVPTXISD::StoreParamU32:
2343 case NVPTXISD::StoreParamS32:
2344 case NVPTXISD::StoreParam:
2347 case NVPTXISD::StoreParamV2:
2350 case NVPTXISD::StoreParamV4:
2355 // Build vector of operands
2356 SmallVector<SDValue, 8> Ops;
2357 for (unsigned i = 0; i < NumElts; ++i)
2358 Ops.push_back(N->getOperand(i + 3));
2359 Ops.push_back(CurDAG->getTargetConstant(ParamVal, MVT::i32));
2360 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2361 Ops.push_back(Chain);
2362 Ops.push_back(Flag);
2364 // Determine target opcode
2365 // If we have an i1, use an 8-bit store. The lowering code in
2366 // NVPTXISelLowering will have already emitted an upcast.
2367 unsigned Opcode = 0;
2368 switch (N->getOpcode()) {
2374 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2378 Opcode = NVPTX::StoreParamI8;
2381 Opcode = NVPTX::StoreParamI8;
2384 Opcode = NVPTX::StoreParamI16;
2387 Opcode = NVPTX::StoreParamI32;
2390 Opcode = NVPTX::StoreParamI64;
2393 Opcode = NVPTX::StoreParamF32;
2396 Opcode = NVPTX::StoreParamF64;
2401 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2405 Opcode = NVPTX::StoreParamV2I8;
2408 Opcode = NVPTX::StoreParamV2I8;
2411 Opcode = NVPTX::StoreParamV2I16;
2414 Opcode = NVPTX::StoreParamV2I32;
2417 Opcode = NVPTX::StoreParamV2I64;
2420 Opcode = NVPTX::StoreParamV2F32;
2423 Opcode = NVPTX::StoreParamV2F64;
2428 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2432 Opcode = NVPTX::StoreParamV4I8;
2435 Opcode = NVPTX::StoreParamV4I8;
2438 Opcode = NVPTX::StoreParamV4I16;
2441 Opcode = NVPTX::StoreParamV4I32;
2444 Opcode = NVPTX::StoreParamV4F32;
2450 // Special case: if we have a sign-extend/zero-extend node, insert the
2451 // conversion instruction first, and use that as the value operand to
2452 // the selected StoreParam node.
2453 case NVPTXISD::StoreParamU32: {
2454 Opcode = NVPTX::StoreParamI32;
2455 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
2457 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL,
2458 MVT::i32, Ops[0], CvtNone);
2459 Ops[0] = SDValue(Cvt, 0);
2462 case NVPTXISD::StoreParamS32: {
2463 Opcode = NVPTX::StoreParamI32;
2464 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
2466 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL,
2467 MVT::i32, Ops[0], CvtNone);
2468 Ops[0] = SDValue(Cvt, 0);
2473 SDVTList RetVTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2475 CurDAG->getMachineNode(Opcode, DL, RetVTs, Ops);
2476 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2477 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2478 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
2483 SDNode *NVPTXDAGToDAGISel::SelectTextureIntrinsic(SDNode *N) {
2484 SDValue Chain = N->getOperand(0);
2485 SDValue TexRef = N->getOperand(1);
2486 SDValue SampRef = N->getOperand(2);
2489 SmallVector<SDValue, 8> Ops;
2491 switch (N->getOpcode()) {
2492 default: return NULL;
2493 case NVPTXISD::Tex1DFloatI32:
2494 Opc = NVPTX::TEX_1D_F32_I32;
2496 case NVPTXISD::Tex1DFloatFloat:
2497 Opc = NVPTX::TEX_1D_F32_F32;
2499 case NVPTXISD::Tex1DFloatFloatLevel:
2500 Opc = NVPTX::TEX_1D_F32_F32_LEVEL;
2502 case NVPTXISD::Tex1DFloatFloatGrad:
2503 Opc = NVPTX::TEX_1D_F32_F32_GRAD;
2505 case NVPTXISD::Tex1DI32I32:
2506 Opc = NVPTX::TEX_1D_I32_I32;
2508 case NVPTXISD::Tex1DI32Float:
2509 Opc = NVPTX::TEX_1D_I32_F32;
2511 case NVPTXISD::Tex1DI32FloatLevel:
2512 Opc = NVPTX::TEX_1D_I32_F32_LEVEL;
2514 case NVPTXISD::Tex1DI32FloatGrad:
2515 Opc = NVPTX::TEX_1D_I32_F32_GRAD;
2517 case NVPTXISD::Tex1DArrayFloatI32:
2518 Opc = NVPTX::TEX_1D_ARRAY_F32_I32;
2520 case NVPTXISD::Tex1DArrayFloatFloat:
2521 Opc = NVPTX::TEX_1D_ARRAY_F32_F32;
2523 case NVPTXISD::Tex1DArrayFloatFloatLevel:
2524 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL;
2526 case NVPTXISD::Tex1DArrayFloatFloatGrad:
2527 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_GRAD;
2529 case NVPTXISD::Tex1DArrayI32I32:
2530 Opc = NVPTX::TEX_1D_ARRAY_I32_I32;
2532 case NVPTXISD::Tex1DArrayI32Float:
2533 Opc = NVPTX::TEX_1D_ARRAY_I32_F32;
2535 case NVPTXISD::Tex1DArrayI32FloatLevel:
2536 Opc = NVPTX::TEX_1D_ARRAY_I32_F32_LEVEL;
2538 case NVPTXISD::Tex1DArrayI32FloatGrad:
2539 Opc = NVPTX::TEX_1D_ARRAY_I32_F32_GRAD;
2541 case NVPTXISD::Tex2DFloatI32:
2542 Opc = NVPTX::TEX_2D_F32_I32;
2544 case NVPTXISD::Tex2DFloatFloat:
2545 Opc = NVPTX::TEX_2D_F32_F32;
2547 case NVPTXISD::Tex2DFloatFloatLevel:
2548 Opc = NVPTX::TEX_2D_F32_F32_LEVEL;
2550 case NVPTXISD::Tex2DFloatFloatGrad:
2551 Opc = NVPTX::TEX_2D_F32_F32_GRAD;
2553 case NVPTXISD::Tex2DI32I32:
2554 Opc = NVPTX::TEX_2D_I32_I32;
2556 case NVPTXISD::Tex2DI32Float:
2557 Opc = NVPTX::TEX_2D_I32_F32;
2559 case NVPTXISD::Tex2DI32FloatLevel:
2560 Opc = NVPTX::TEX_2D_I32_F32_LEVEL;
2562 case NVPTXISD::Tex2DI32FloatGrad:
2563 Opc = NVPTX::TEX_2D_I32_F32_GRAD;
2565 case NVPTXISD::Tex2DArrayFloatI32:
2566 Opc = NVPTX::TEX_2D_ARRAY_F32_I32;
2568 case NVPTXISD::Tex2DArrayFloatFloat:
2569 Opc = NVPTX::TEX_2D_ARRAY_F32_F32;
2571 case NVPTXISD::Tex2DArrayFloatFloatLevel:
2572 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL;
2574 case NVPTXISD::Tex2DArrayFloatFloatGrad:
2575 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_GRAD;
2577 case NVPTXISD::Tex2DArrayI32I32:
2578 Opc = NVPTX::TEX_2D_ARRAY_I32_I32;
2580 case NVPTXISD::Tex2DArrayI32Float:
2581 Opc = NVPTX::TEX_2D_ARRAY_I32_F32;
2583 case NVPTXISD::Tex2DArrayI32FloatLevel:
2584 Opc = NVPTX::TEX_2D_ARRAY_I32_F32_LEVEL;
2586 case NVPTXISD::Tex2DArrayI32FloatGrad:
2587 Opc = NVPTX::TEX_2D_ARRAY_I32_F32_GRAD;
2589 case NVPTXISD::Tex3DFloatI32:
2590 Opc = NVPTX::TEX_3D_F32_I32;
2592 case NVPTXISD::Tex3DFloatFloat:
2593 Opc = NVPTX::TEX_3D_F32_F32;
2595 case NVPTXISD::Tex3DFloatFloatLevel:
2596 Opc = NVPTX::TEX_3D_F32_F32_LEVEL;
2598 case NVPTXISD::Tex3DFloatFloatGrad:
2599 Opc = NVPTX::TEX_3D_F32_F32_GRAD;
2601 case NVPTXISD::Tex3DI32I32:
2602 Opc = NVPTX::TEX_3D_I32_I32;
2604 case NVPTXISD::Tex3DI32Float:
2605 Opc = NVPTX::TEX_3D_I32_F32;
2607 case NVPTXISD::Tex3DI32FloatLevel:
2608 Opc = NVPTX::TEX_3D_I32_F32_LEVEL;
2610 case NVPTXISD::Tex3DI32FloatGrad:
2611 Opc = NVPTX::TEX_3D_I32_F32_GRAD;
2615 Ops.push_back(TexRef);
2616 Ops.push_back(SampRef);
2618 // Copy over indices
2619 for (unsigned i = 3; i < N->getNumOperands(); ++i) {
2620 Ops.push_back(N->getOperand(i));
2623 Ops.push_back(Chain);
2624 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
2628 SDNode *NVPTXDAGToDAGISel::SelectSurfaceIntrinsic(SDNode *N) {
2629 SDValue Chain = N->getOperand(0);
2630 SDValue TexHandle = N->getOperand(1);
2633 SmallVector<SDValue, 8> Ops;
2634 switch (N->getOpcode()) {
2635 default: return NULL;
2636 case NVPTXISD::Suld1DI8Trap:
2637 Opc = NVPTX::SULD_1D_I8_TRAP;
2638 Ops.push_back(TexHandle);
2639 Ops.push_back(N->getOperand(2));
2640 Ops.push_back(Chain);
2642 case NVPTXISD::Suld1DI16Trap:
2643 Opc = NVPTX::SULD_1D_I16_TRAP;
2644 Ops.push_back(TexHandle);
2645 Ops.push_back(N->getOperand(2));
2646 Ops.push_back(Chain);
2648 case NVPTXISD::Suld1DI32Trap:
2649 Opc = NVPTX::SULD_1D_I32_TRAP;
2650 Ops.push_back(TexHandle);
2651 Ops.push_back(N->getOperand(2));
2652 Ops.push_back(Chain);
2654 case NVPTXISD::Suld1DV2I8Trap:
2655 Opc = NVPTX::SULD_1D_V2I8_TRAP;
2656 Ops.push_back(TexHandle);
2657 Ops.push_back(N->getOperand(2));
2658 Ops.push_back(Chain);
2660 case NVPTXISD::Suld1DV2I16Trap:
2661 Opc = NVPTX::SULD_1D_V2I16_TRAP;
2662 Ops.push_back(TexHandle);
2663 Ops.push_back(N->getOperand(2));
2664 Ops.push_back(Chain);
2666 case NVPTXISD::Suld1DV2I32Trap:
2667 Opc = NVPTX::SULD_1D_V2I32_TRAP;
2668 Ops.push_back(TexHandle);
2669 Ops.push_back(N->getOperand(2));
2670 Ops.push_back(Chain);
2672 case NVPTXISD::Suld1DV4I8Trap:
2673 Opc = NVPTX::SULD_1D_V4I8_TRAP;
2674 Ops.push_back(TexHandle);
2675 Ops.push_back(N->getOperand(2));
2676 Ops.push_back(Chain);
2678 case NVPTXISD::Suld1DV4I16Trap:
2679 Opc = NVPTX::SULD_1D_V4I16_TRAP;
2680 Ops.push_back(TexHandle);
2681 Ops.push_back(N->getOperand(2));
2682 Ops.push_back(Chain);
2684 case NVPTXISD::Suld1DV4I32Trap:
2685 Opc = NVPTX::SULD_1D_V4I32_TRAP;
2686 Ops.push_back(TexHandle);
2687 Ops.push_back(N->getOperand(2));
2688 Ops.push_back(Chain);
2690 case NVPTXISD::Suld1DArrayI8Trap:
2691 Opc = NVPTX::SULD_1D_ARRAY_I8_TRAP;
2692 Ops.push_back(TexHandle);
2693 Ops.push_back(N->getOperand(2));
2694 Ops.push_back(N->getOperand(3));
2695 Ops.push_back(Chain);
2697 case NVPTXISD::Suld1DArrayI16Trap:
2698 Opc = NVPTX::SULD_1D_ARRAY_I16_TRAP;
2699 Ops.push_back(TexHandle);
2700 Ops.push_back(N->getOperand(2));
2701 Ops.push_back(N->getOperand(3));
2702 Ops.push_back(Chain);
2704 case NVPTXISD::Suld1DArrayI32Trap:
2705 Opc = NVPTX::SULD_1D_ARRAY_I32_TRAP;
2706 Ops.push_back(TexHandle);
2707 Ops.push_back(N->getOperand(2));
2708 Ops.push_back(N->getOperand(3));
2709 Ops.push_back(Chain);
2711 case NVPTXISD::Suld1DArrayV2I8Trap:
2712 Opc = NVPTX::SULD_1D_ARRAY_V2I8_TRAP;
2713 Ops.push_back(TexHandle);
2714 Ops.push_back(N->getOperand(2));
2715 Ops.push_back(N->getOperand(3));
2716 Ops.push_back(Chain);
2718 case NVPTXISD::Suld1DArrayV2I16Trap:
2719 Opc = NVPTX::SULD_1D_ARRAY_V2I16_TRAP;
2720 Ops.push_back(TexHandle);
2721 Ops.push_back(N->getOperand(2));
2722 Ops.push_back(N->getOperand(3));
2723 Ops.push_back(Chain);
2725 case NVPTXISD::Suld1DArrayV2I32Trap:
2726 Opc = NVPTX::SULD_1D_ARRAY_V2I32_TRAP;
2727 Ops.push_back(TexHandle);
2728 Ops.push_back(N->getOperand(2));
2729 Ops.push_back(N->getOperand(3));
2730 Ops.push_back(Chain);
2732 case NVPTXISD::Suld1DArrayV4I8Trap:
2733 Opc = NVPTX::SULD_1D_ARRAY_V4I8_TRAP;
2734 Ops.push_back(TexHandle);
2735 Ops.push_back(N->getOperand(2));
2736 Ops.push_back(N->getOperand(3));
2737 Ops.push_back(Chain);
2739 case NVPTXISD::Suld1DArrayV4I16Trap:
2740 Opc = NVPTX::SULD_1D_ARRAY_V4I16_TRAP;
2741 Ops.push_back(TexHandle);
2742 Ops.push_back(N->getOperand(2));
2743 Ops.push_back(N->getOperand(3));
2744 Ops.push_back(Chain);
2746 case NVPTXISD::Suld1DArrayV4I32Trap:
2747 Opc = NVPTX::SULD_1D_ARRAY_V4I32_TRAP;
2748 Ops.push_back(TexHandle);
2749 Ops.push_back(N->getOperand(2));
2750 Ops.push_back(N->getOperand(3));
2751 Ops.push_back(Chain);
2753 case NVPTXISD::Suld2DI8Trap:
2754 Opc = NVPTX::SULD_2D_I8_TRAP;
2755 Ops.push_back(TexHandle);
2756 Ops.push_back(N->getOperand(2));
2757 Ops.push_back(N->getOperand(3));
2758 Ops.push_back(Chain);
2760 case NVPTXISD::Suld2DI16Trap:
2761 Opc = NVPTX::SULD_2D_I16_TRAP;
2762 Ops.push_back(TexHandle);
2763 Ops.push_back(N->getOperand(2));
2764 Ops.push_back(N->getOperand(3));
2765 Ops.push_back(Chain);
2767 case NVPTXISD::Suld2DI32Trap:
2768 Opc = NVPTX::SULD_2D_I32_TRAP;
2769 Ops.push_back(TexHandle);
2770 Ops.push_back(N->getOperand(2));
2771 Ops.push_back(N->getOperand(3));
2772 Ops.push_back(Chain);
2774 case NVPTXISD::Suld2DV2I8Trap:
2775 Opc = NVPTX::SULD_2D_V2I8_TRAP;
2776 Ops.push_back(TexHandle);
2777 Ops.push_back(N->getOperand(2));
2778 Ops.push_back(N->getOperand(3));
2779 Ops.push_back(Chain);
2781 case NVPTXISD::Suld2DV2I16Trap:
2782 Opc = NVPTX::SULD_2D_V2I16_TRAP;
2783 Ops.push_back(TexHandle);
2784 Ops.push_back(N->getOperand(2));
2785 Ops.push_back(N->getOperand(3));
2786 Ops.push_back(Chain);
2788 case NVPTXISD::Suld2DV2I32Trap:
2789 Opc = NVPTX::SULD_2D_V2I32_TRAP;
2790 Ops.push_back(TexHandle);
2791 Ops.push_back(N->getOperand(2));
2792 Ops.push_back(N->getOperand(3));
2793 Ops.push_back(Chain);
2795 case NVPTXISD::Suld2DV4I8Trap:
2796 Opc = NVPTX::SULD_2D_V4I8_TRAP;
2797 Ops.push_back(TexHandle);
2798 Ops.push_back(N->getOperand(2));
2799 Ops.push_back(N->getOperand(3));
2800 Ops.push_back(Chain);
2802 case NVPTXISD::Suld2DV4I16Trap:
2803 Opc = NVPTX::SULD_2D_V4I16_TRAP;
2804 Ops.push_back(TexHandle);
2805 Ops.push_back(N->getOperand(2));
2806 Ops.push_back(N->getOperand(3));
2807 Ops.push_back(Chain);
2809 case NVPTXISD::Suld2DV4I32Trap:
2810 Opc = NVPTX::SULD_2D_V4I32_TRAP;
2811 Ops.push_back(TexHandle);
2812 Ops.push_back(N->getOperand(2));
2813 Ops.push_back(N->getOperand(3));
2814 Ops.push_back(Chain);
2816 case NVPTXISD::Suld2DArrayI8Trap:
2817 Opc = NVPTX::SULD_2D_ARRAY_I8_TRAP;
2818 Ops.push_back(TexHandle);
2819 Ops.push_back(N->getOperand(2));
2820 Ops.push_back(N->getOperand(3));
2821 Ops.push_back(N->getOperand(4));
2822 Ops.push_back(Chain);
2824 case NVPTXISD::Suld2DArrayI16Trap:
2825 Opc = NVPTX::SULD_2D_ARRAY_I16_TRAP;
2826 Ops.push_back(TexHandle);
2827 Ops.push_back(N->getOperand(2));
2828 Ops.push_back(N->getOperand(3));
2829 Ops.push_back(N->getOperand(4));
2830 Ops.push_back(Chain);
2832 case NVPTXISD::Suld2DArrayI32Trap:
2833 Opc = NVPTX::SULD_2D_ARRAY_I32_TRAP;
2834 Ops.push_back(TexHandle);
2835 Ops.push_back(N->getOperand(2));
2836 Ops.push_back(N->getOperand(3));
2837 Ops.push_back(N->getOperand(4));
2838 Ops.push_back(Chain);
2840 case NVPTXISD::Suld2DArrayV2I8Trap:
2841 Opc = NVPTX::SULD_2D_ARRAY_V2I8_TRAP;
2842 Ops.push_back(TexHandle);
2843 Ops.push_back(N->getOperand(2));
2844 Ops.push_back(N->getOperand(3));
2845 Ops.push_back(N->getOperand(4));
2846 Ops.push_back(Chain);
2848 case NVPTXISD::Suld2DArrayV2I16Trap:
2849 Opc = NVPTX::SULD_2D_ARRAY_V2I16_TRAP;
2850 Ops.push_back(TexHandle);
2851 Ops.push_back(N->getOperand(2));
2852 Ops.push_back(N->getOperand(3));
2853 Ops.push_back(N->getOperand(4));
2854 Ops.push_back(Chain);
2856 case NVPTXISD::Suld2DArrayV2I32Trap:
2857 Opc = NVPTX::SULD_2D_ARRAY_V2I32_TRAP;
2858 Ops.push_back(TexHandle);
2859 Ops.push_back(N->getOperand(2));
2860 Ops.push_back(N->getOperand(3));
2861 Ops.push_back(N->getOperand(4));
2862 Ops.push_back(Chain);
2864 case NVPTXISD::Suld2DArrayV4I8Trap:
2865 Opc = NVPTX::SULD_2D_ARRAY_V4I8_TRAP;
2866 Ops.push_back(TexHandle);
2867 Ops.push_back(N->getOperand(2));
2868 Ops.push_back(N->getOperand(3));
2869 Ops.push_back(N->getOperand(4));
2870 Ops.push_back(Chain);
2872 case NVPTXISD::Suld2DArrayV4I16Trap:
2873 Opc = NVPTX::SULD_2D_ARRAY_V4I16_TRAP;
2874 Ops.push_back(TexHandle);
2875 Ops.push_back(N->getOperand(2));
2876 Ops.push_back(N->getOperand(3));
2877 Ops.push_back(N->getOperand(4));
2878 Ops.push_back(Chain);
2880 case NVPTXISD::Suld2DArrayV4I32Trap:
2881 Opc = NVPTX::SULD_2D_ARRAY_V4I32_TRAP;
2882 Ops.push_back(TexHandle);
2883 Ops.push_back(N->getOperand(2));
2884 Ops.push_back(N->getOperand(3));
2885 Ops.push_back(N->getOperand(4));
2886 Ops.push_back(Chain);
2888 case NVPTXISD::Suld3DI8Trap:
2889 Opc = NVPTX::SULD_3D_I8_TRAP;
2890 Ops.push_back(TexHandle);
2891 Ops.push_back(N->getOperand(2));
2892 Ops.push_back(N->getOperand(3));
2893 Ops.push_back(N->getOperand(4));
2894 Ops.push_back(Chain);
2896 case NVPTXISD::Suld3DI16Trap:
2897 Opc = NVPTX::SULD_3D_I16_TRAP;
2898 Ops.push_back(TexHandle);
2899 Ops.push_back(N->getOperand(2));
2900 Ops.push_back(N->getOperand(3));
2901 Ops.push_back(N->getOperand(4));
2902 Ops.push_back(Chain);
2904 case NVPTXISD::Suld3DI32Trap:
2905 Opc = NVPTX::SULD_3D_I32_TRAP;
2906 Ops.push_back(TexHandle);
2907 Ops.push_back(N->getOperand(2));
2908 Ops.push_back(N->getOperand(3));
2909 Ops.push_back(N->getOperand(4));
2910 Ops.push_back(Chain);
2912 case NVPTXISD::Suld3DV2I8Trap:
2913 Opc = NVPTX::SULD_3D_V2I8_TRAP;
2914 Ops.push_back(TexHandle);
2915 Ops.push_back(N->getOperand(2));
2916 Ops.push_back(N->getOperand(3));
2917 Ops.push_back(N->getOperand(4));
2918 Ops.push_back(Chain);
2920 case NVPTXISD::Suld3DV2I16Trap:
2921 Opc = NVPTX::SULD_3D_V2I16_TRAP;
2922 Ops.push_back(TexHandle);
2923 Ops.push_back(N->getOperand(2));
2924 Ops.push_back(N->getOperand(3));
2925 Ops.push_back(N->getOperand(4));
2926 Ops.push_back(Chain);
2928 case NVPTXISD::Suld3DV2I32Trap:
2929 Opc = NVPTX::SULD_3D_V2I32_TRAP;
2930 Ops.push_back(TexHandle);
2931 Ops.push_back(N->getOperand(2));
2932 Ops.push_back(N->getOperand(3));
2933 Ops.push_back(N->getOperand(4));
2934 Ops.push_back(Chain);
2936 case NVPTXISD::Suld3DV4I8Trap:
2937 Opc = NVPTX::SULD_3D_V4I8_TRAP;
2938 Ops.push_back(TexHandle);
2939 Ops.push_back(N->getOperand(2));
2940 Ops.push_back(N->getOperand(3));
2941 Ops.push_back(N->getOperand(4));
2942 Ops.push_back(Chain);
2944 case NVPTXISD::Suld3DV4I16Trap:
2945 Opc = NVPTX::SULD_3D_V4I16_TRAP;
2946 Ops.push_back(TexHandle);
2947 Ops.push_back(N->getOperand(2));
2948 Ops.push_back(N->getOperand(3));
2949 Ops.push_back(N->getOperand(4));
2950 Ops.push_back(Chain);
2952 case NVPTXISD::Suld3DV4I32Trap:
2953 Opc = NVPTX::SULD_3D_V4I32_TRAP;
2954 Ops.push_back(TexHandle);
2955 Ops.push_back(N->getOperand(2));
2956 Ops.push_back(N->getOperand(3));
2957 Ops.push_back(N->getOperand(4));
2958 Ops.push_back(Chain);
2961 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
2965 // SelectDirectAddr - Match a direct address for DAG.
2966 // A direct address could be a globaladdress or externalsymbol.
2967 bool NVPTXDAGToDAGISel::SelectDirectAddr(SDValue N, SDValue &Address) {
2968 // Return true if TGA or ES.
2969 if (N.getOpcode() == ISD::TargetGlobalAddress ||
2970 N.getOpcode() == ISD::TargetExternalSymbol) {
2974 if (N.getOpcode() == NVPTXISD::Wrapper) {
2975 Address = N.getOperand(0);
2978 if (N.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
2979 unsigned IID = cast<ConstantSDNode>(N.getOperand(0))->getZExtValue();
2980 if (IID == Intrinsic::nvvm_ptr_gen_to_param)
2981 if (N.getOperand(1).getOpcode() == NVPTXISD::MoveParam)
2982 return (SelectDirectAddr(N.getOperand(1).getOperand(0), Address));
2988 bool NVPTXDAGToDAGISel::SelectADDRsi_imp(
2989 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
2990 if (Addr.getOpcode() == ISD::ADD) {
2991 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
2992 SDValue base = Addr.getOperand(0);
2993 if (SelectDirectAddr(base, Base)) {
2994 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
3003 bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr,
3004 SDValue &Base, SDValue &Offset) {
3005 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32);
3009 bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr,
3010 SDValue &Base, SDValue &Offset) {
3011 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64);
3015 bool NVPTXDAGToDAGISel::SelectADDRri_imp(
3016 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
3017 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
3018 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
3019 Offset = CurDAG->getTargetConstant(0, mvt);
3022 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
3023 Addr.getOpcode() == ISD::TargetGlobalAddress)
3024 return false; // direct calls.
3026 if (Addr.getOpcode() == ISD::ADD) {
3027 if (SelectDirectAddr(Addr.getOperand(0), Addr)) {
3030 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
3031 if (FrameIndexSDNode *FIN =
3032 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
3033 // Constant offset from frame ref.
3034 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
3036 Base = Addr.getOperand(0);
3037 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
3045 bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr,
3046 SDValue &Base, SDValue &Offset) {
3047 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32);
3051 bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr,
3052 SDValue &Base, SDValue &Offset) {
3053 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64);
3056 bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
3057 unsigned int spN) const {
3058 const Value *Src = NULL;
3059 // Even though MemIntrinsicSDNode is a subclas of MemSDNode,
3060 // the classof() for MemSDNode does not include MemIntrinsicSDNode
3061 // (See SelectionDAGNodes.h). So we need to check for both.
3062 if (MemSDNode *mN = dyn_cast<MemSDNode>(N)) {
3063 if (spN == 0 && mN->getMemOperand()->getPseudoValue())
3065 Src = mN->getMemOperand()->getValue();
3066 } else if (MemSDNode *mN = dyn_cast<MemIntrinsicSDNode>(N)) {
3067 if (spN == 0 && mN->getMemOperand()->getPseudoValue())
3069 Src = mN->getMemOperand()->getValue();
3073 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
3074 return (PT->getAddressSpace() == spN);
3078 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
3079 /// inline asm expressions.
3080 bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
3081 const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
3083 switch (ConstraintCode) {
3087 if (SelectDirectAddr(Op, Op0)) {
3088 OutOps.push_back(Op0);
3089 OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
3092 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
3093 OutOps.push_back(Op0);
3094 OutOps.push_back(Op1);