1 //===-- NVPTXISelDAGToDAG.cpp - A dag to dag inst selector for NVPTX ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "nvptx-isel"
15 #include "NVPTXISelDAGToDAG.h"
16 #include "llvm/IR/GlobalValue.h"
17 #include "llvm/IR/Instructions.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetIntrinsicInfo.h"
27 FMAContractLevel("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
28 cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
29 " 1: do it 2: do it aggressively"),
32 static cl::opt<int> UsePrecDivF32(
33 "nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden,
34 cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
35 " IEEE Compliant F32 div.rnd if avaiable."),
39 UsePrecSqrtF32("nvptx-prec-sqrtf32", cl::Hidden,
40 cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
44 FtzEnabled("nvptx-f32ftz", cl::ZeroOrMore, cl::Hidden,
45 cl::desc("NVPTX Specific: Flush f32 subnormals to sign-preserving zero."),
49 /// createNVPTXISelDag - This pass converts a legalized DAG into a
50 /// NVPTX-specific DAG, ready for instruction scheduling.
51 FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
52 llvm::CodeGenOpt::Level OptLevel) {
53 return new NVPTXDAGToDAGISel(TM, OptLevel);
56 NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
57 CodeGenOpt::Level OptLevel)
58 : SelectionDAGISel(tm, OptLevel),
59 Subtarget(tm.getSubtarget<NVPTXSubtarget>()) {
61 doFMAF32 = (OptLevel > 0) && Subtarget.hasFMAF32() && (FMAContractLevel >= 1);
62 doFMAF64 = (OptLevel > 0) && Subtarget.hasFMAF64() && (FMAContractLevel >= 1);
64 (OptLevel > 0) && Subtarget.hasFMAF32() && (FMAContractLevel == 2);
66 (OptLevel > 0) && Subtarget.hasFMAF64() && (FMAContractLevel == 2);
68 allowFMA = (FMAContractLevel >= 1);
70 doMulWide = (OptLevel > 0);
73 int NVPTXDAGToDAGISel::getDivF32Level() const {
74 if (UsePrecDivF32.getNumOccurrences() > 0) {
75 // If nvptx-prec-div32=N is used on the command-line, always honor it
78 // Otherwise, use div.approx if fast math is enabled
79 if (TM.Options.UnsafeFPMath)
86 bool NVPTXDAGToDAGISel::usePrecSqrtF32() const {
87 if (UsePrecSqrtF32.getNumOccurrences() > 0) {
88 // If nvptx-prec-sqrtf32 is used on the command-line, always honor it
89 return UsePrecSqrtF32;
91 // Otherwise, use sqrt.approx if fast math is enabled
92 if (TM.Options.UnsafeFPMath)
99 bool NVPTXDAGToDAGISel::useF32FTZ() const {
100 if (FtzEnabled.getNumOccurrences() > 0) {
101 // If nvptx-f32ftz is used on the command-line, always honor it
104 const Function *F = MF->getFunction();
105 // Otherwise, check for an nvptx-f32ftz attribute on the function
106 if (F->hasFnAttribute("nvptx-f32ftz"))
107 return (F->getAttributes().getAttribute(AttributeSet::FunctionIndex,
109 .getValueAsString() == "true");
115 /// Select - Select instructions not customized! Used for
116 /// expanded, promoted and normal instructions.
117 SDNode *NVPTXDAGToDAGISel::Select(SDNode *N) {
119 if (N->isMachineOpcode()) {
121 return NULL; // Already selected.
124 SDNode *ResNode = NULL;
125 switch (N->getOpcode()) {
127 ResNode = SelectLoad(N);
130 ResNode = SelectStore(N);
132 case NVPTXISD::LoadV2:
133 case NVPTXISD::LoadV4:
134 ResNode = SelectLoadVector(N);
136 case NVPTXISD::LDGV2:
137 case NVPTXISD::LDGV4:
138 case NVPTXISD::LDUV2:
139 case NVPTXISD::LDUV4:
140 ResNode = SelectLDGLDUVector(N);
142 case NVPTXISD::StoreV2:
143 case NVPTXISD::StoreV4:
144 ResNode = SelectStoreVector(N);
146 case NVPTXISD::LoadParam:
147 case NVPTXISD::LoadParamV2:
148 case NVPTXISD::LoadParamV4:
149 ResNode = SelectLoadParam(N);
151 case NVPTXISD::StoreRetval:
152 case NVPTXISD::StoreRetvalV2:
153 case NVPTXISD::StoreRetvalV4:
154 ResNode = SelectStoreRetval(N);
156 case NVPTXISD::StoreParam:
157 case NVPTXISD::StoreParamV2:
158 case NVPTXISD::StoreParamV4:
159 case NVPTXISD::StoreParamS32:
160 case NVPTXISD::StoreParamU32:
161 ResNode = SelectStoreParam(N);
163 case ISD::INTRINSIC_WO_CHAIN:
164 ResNode = SelectIntrinsicNoChain(N);
166 case NVPTXISD::Tex1DFloatI32:
167 case NVPTXISD::Tex1DFloatFloat:
168 case NVPTXISD::Tex1DFloatFloatLevel:
169 case NVPTXISD::Tex1DFloatFloatGrad:
170 case NVPTXISD::Tex1DI32I32:
171 case NVPTXISD::Tex1DI32Float:
172 case NVPTXISD::Tex1DI32FloatLevel:
173 case NVPTXISD::Tex1DI32FloatGrad:
174 case NVPTXISD::Tex1DArrayFloatI32:
175 case NVPTXISD::Tex1DArrayFloatFloat:
176 case NVPTXISD::Tex1DArrayFloatFloatLevel:
177 case NVPTXISD::Tex1DArrayFloatFloatGrad:
178 case NVPTXISD::Tex1DArrayI32I32:
179 case NVPTXISD::Tex1DArrayI32Float:
180 case NVPTXISD::Tex1DArrayI32FloatLevel:
181 case NVPTXISD::Tex1DArrayI32FloatGrad:
182 case NVPTXISD::Tex2DFloatI32:
183 case NVPTXISD::Tex2DFloatFloat:
184 case NVPTXISD::Tex2DFloatFloatLevel:
185 case NVPTXISD::Tex2DFloatFloatGrad:
186 case NVPTXISD::Tex2DI32I32:
187 case NVPTXISD::Tex2DI32Float:
188 case NVPTXISD::Tex2DI32FloatLevel:
189 case NVPTXISD::Tex2DI32FloatGrad:
190 case NVPTXISD::Tex2DArrayFloatI32:
191 case NVPTXISD::Tex2DArrayFloatFloat:
192 case NVPTXISD::Tex2DArrayFloatFloatLevel:
193 case NVPTXISD::Tex2DArrayFloatFloatGrad:
194 case NVPTXISD::Tex2DArrayI32I32:
195 case NVPTXISD::Tex2DArrayI32Float:
196 case NVPTXISD::Tex2DArrayI32FloatLevel:
197 case NVPTXISD::Tex2DArrayI32FloatGrad:
198 case NVPTXISD::Tex3DFloatI32:
199 case NVPTXISD::Tex3DFloatFloat:
200 case NVPTXISD::Tex3DFloatFloatLevel:
201 case NVPTXISD::Tex3DFloatFloatGrad:
202 case NVPTXISD::Tex3DI32I32:
203 case NVPTXISD::Tex3DI32Float:
204 case NVPTXISD::Tex3DI32FloatLevel:
205 case NVPTXISD::Tex3DI32FloatGrad:
206 ResNode = SelectTextureIntrinsic(N);
208 case NVPTXISD::Suld1DI8Trap:
209 case NVPTXISD::Suld1DI16Trap:
210 case NVPTXISD::Suld1DI32Trap:
211 case NVPTXISD::Suld1DV2I8Trap:
212 case NVPTXISD::Suld1DV2I16Trap:
213 case NVPTXISD::Suld1DV2I32Trap:
214 case NVPTXISD::Suld1DV4I8Trap:
215 case NVPTXISD::Suld1DV4I16Trap:
216 case NVPTXISD::Suld1DV4I32Trap:
217 case NVPTXISD::Suld1DArrayI8Trap:
218 case NVPTXISD::Suld1DArrayI16Trap:
219 case NVPTXISD::Suld1DArrayI32Trap:
220 case NVPTXISD::Suld1DArrayV2I8Trap:
221 case NVPTXISD::Suld1DArrayV2I16Trap:
222 case NVPTXISD::Suld1DArrayV2I32Trap:
223 case NVPTXISD::Suld1DArrayV4I8Trap:
224 case NVPTXISD::Suld1DArrayV4I16Trap:
225 case NVPTXISD::Suld1DArrayV4I32Trap:
226 case NVPTXISD::Suld2DI8Trap:
227 case NVPTXISD::Suld2DI16Trap:
228 case NVPTXISD::Suld2DI32Trap:
229 case NVPTXISD::Suld2DV2I8Trap:
230 case NVPTXISD::Suld2DV2I16Trap:
231 case NVPTXISD::Suld2DV2I32Trap:
232 case NVPTXISD::Suld2DV4I8Trap:
233 case NVPTXISD::Suld2DV4I16Trap:
234 case NVPTXISD::Suld2DV4I32Trap:
235 case NVPTXISD::Suld2DArrayI8Trap:
236 case NVPTXISD::Suld2DArrayI16Trap:
237 case NVPTXISD::Suld2DArrayI32Trap:
238 case NVPTXISD::Suld2DArrayV2I8Trap:
239 case NVPTXISD::Suld2DArrayV2I16Trap:
240 case NVPTXISD::Suld2DArrayV2I32Trap:
241 case NVPTXISD::Suld2DArrayV4I8Trap:
242 case NVPTXISD::Suld2DArrayV4I16Trap:
243 case NVPTXISD::Suld2DArrayV4I32Trap:
244 case NVPTXISD::Suld3DI8Trap:
245 case NVPTXISD::Suld3DI16Trap:
246 case NVPTXISD::Suld3DI32Trap:
247 case NVPTXISD::Suld3DV2I8Trap:
248 case NVPTXISD::Suld3DV2I16Trap:
249 case NVPTXISD::Suld3DV2I32Trap:
250 case NVPTXISD::Suld3DV4I8Trap:
251 case NVPTXISD::Suld3DV4I16Trap:
252 case NVPTXISD::Suld3DV4I32Trap:
253 ResNode = SelectSurfaceIntrinsic(N);
255 case ISD::ADDRSPACECAST:
256 ResNode = SelectAddrSpaceCast(N);
263 return SelectCode(N);
266 static unsigned int getCodeAddrSpace(MemSDNode *N,
267 const NVPTXSubtarget &Subtarget) {
268 const Value *Src = N->getMemOperand()->getValue();
271 return NVPTX::PTXLdStInstCode::GENERIC;
273 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) {
274 switch (PT->getAddressSpace()) {
275 case llvm::ADDRESS_SPACE_LOCAL: return NVPTX::PTXLdStInstCode::LOCAL;
276 case llvm::ADDRESS_SPACE_GLOBAL: return NVPTX::PTXLdStInstCode::GLOBAL;
277 case llvm::ADDRESS_SPACE_SHARED: return NVPTX::PTXLdStInstCode::SHARED;
278 case llvm::ADDRESS_SPACE_GENERIC: return NVPTX::PTXLdStInstCode::GENERIC;
279 case llvm::ADDRESS_SPACE_PARAM: return NVPTX::PTXLdStInstCode::PARAM;
280 case llvm::ADDRESS_SPACE_CONST: return NVPTX::PTXLdStInstCode::CONSTANT;
284 return NVPTX::PTXLdStInstCode::GENERIC;
287 SDNode *NVPTXDAGToDAGISel::SelectIntrinsicNoChain(SDNode *N) {
288 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
292 case Intrinsic::nvvm_texsurf_handle_internal:
293 return SelectTexSurfHandle(N);
297 SDNode *NVPTXDAGToDAGISel::SelectTexSurfHandle(SDNode *N) {
298 // Op 0 is the intrinsic ID
299 SDValue Wrapper = N->getOperand(1);
300 SDValue GlobalVal = Wrapper.getOperand(0);
301 return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64,
305 SDNode *NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
306 SDValue Src = N->getOperand(0);
307 AddrSpaceCastSDNode *CastN = cast<AddrSpaceCastSDNode>(N);
308 unsigned SrcAddrSpace = CastN->getSrcAddressSpace();
309 unsigned DstAddrSpace = CastN->getDestAddressSpace();
311 assert(SrcAddrSpace != DstAddrSpace &&
312 "addrspacecast must be between different address spaces");
314 if (DstAddrSpace == ADDRESS_SPACE_GENERIC) {
315 // Specific to generic
317 switch (SrcAddrSpace) {
318 default: report_fatal_error("Bad address space in addrspacecast");
319 case ADDRESS_SPACE_GLOBAL:
320 Opc = Subtarget.is64Bit() ? NVPTX::cvta_global_yes_64
321 : NVPTX::cvta_global_yes;
323 case ADDRESS_SPACE_SHARED:
324 Opc = Subtarget.is64Bit() ? NVPTX::cvta_shared_yes_64
325 : NVPTX::cvta_shared_yes;
327 case ADDRESS_SPACE_CONST:
328 Opc = Subtarget.is64Bit() ? NVPTX::cvta_const_yes_64
329 : NVPTX::cvta_const_yes;
331 case ADDRESS_SPACE_LOCAL:
332 Opc = Subtarget.is64Bit() ? NVPTX::cvta_local_yes_64
333 : NVPTX::cvta_local_yes;
336 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
338 // Generic to specific
339 if (SrcAddrSpace != 0)
340 report_fatal_error("Cannot cast between two non-generic address spaces");
342 switch (DstAddrSpace) {
343 default: report_fatal_error("Bad address space in addrspacecast");
344 case ADDRESS_SPACE_GLOBAL:
345 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_global_yes_64
346 : NVPTX::cvta_to_global_yes;
348 case ADDRESS_SPACE_SHARED:
349 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_shared_yes_64
350 : NVPTX::cvta_to_shared_yes;
352 case ADDRESS_SPACE_CONST:
353 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_const_yes_64
354 : NVPTX::cvta_to_const_yes;
356 case ADDRESS_SPACE_LOCAL:
357 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_local_yes_64
358 : NVPTX::cvta_to_local_yes;
361 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
365 SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
367 LoadSDNode *LD = cast<LoadSDNode>(N);
368 EVT LoadedVT = LD->getMemoryVT();
369 SDNode *NVPTXLD = NULL;
371 // do not support pre/post inc/dec
375 if (!LoadedVT.isSimple())
378 // Address Space Setting
379 unsigned int codeAddrSpace = getCodeAddrSpace(LD, Subtarget);
382 // - .volatile is only availalble for .global and .shared
383 bool isVolatile = LD->isVolatile();
384 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
385 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
386 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
390 MVT SimpleVT = LoadedVT.getSimpleVT();
391 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
392 if (SimpleVT.isVector()) {
393 unsigned num = SimpleVT.getVectorNumElements();
395 vecType = NVPTX::PTXLdStInstCode::V2;
397 vecType = NVPTX::PTXLdStInstCode::V4;
402 // Type Setting: fromType + fromTypeWidth
404 // Sign : ISD::SEXTLOAD
405 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
407 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
408 MVT ScalarVT = SimpleVT.getScalarType();
409 // Read at least 8 bits (predicates are stored as 8-bit values)
410 unsigned fromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
411 unsigned int fromType;
412 if ((LD->getExtensionType() == ISD::SEXTLOAD))
413 fromType = NVPTX::PTXLdStInstCode::Signed;
414 else if (ScalarVT.isFloatingPoint())
415 fromType = NVPTX::PTXLdStInstCode::Float;
417 fromType = NVPTX::PTXLdStInstCode::Unsigned;
419 // Create the machine instruction DAG
420 SDValue Chain = N->getOperand(0);
421 SDValue N1 = N->getOperand(1);
423 SDValue Offset, Base;
425 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
427 if (SelectDirectAddr(N1, Addr)) {
430 Opcode = NVPTX::LD_i8_avar;
433 Opcode = NVPTX::LD_i16_avar;
436 Opcode = NVPTX::LD_i32_avar;
439 Opcode = NVPTX::LD_i64_avar;
442 Opcode = NVPTX::LD_f32_avar;
445 Opcode = NVPTX::LD_f64_avar;
450 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
451 getI32Imm(vecType), getI32Imm(fromType),
452 getI32Imm(fromTypeWidth), Addr, Chain };
453 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
454 } else if (Subtarget.is64Bit()
455 ? SelectADDRsi64(N1.getNode(), N1, Base, Offset)
456 : SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
459 Opcode = NVPTX::LD_i8_asi;
462 Opcode = NVPTX::LD_i16_asi;
465 Opcode = NVPTX::LD_i32_asi;
468 Opcode = NVPTX::LD_i64_asi;
471 Opcode = NVPTX::LD_f32_asi;
474 Opcode = NVPTX::LD_f64_asi;
479 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
480 getI32Imm(vecType), getI32Imm(fromType),
481 getI32Imm(fromTypeWidth), Base, Offset, Chain };
482 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
483 } else if (Subtarget.is64Bit()
484 ? SelectADDRri64(N1.getNode(), N1, Base, Offset)
485 : SelectADDRri(N1.getNode(), N1, Base, Offset)) {
486 if (Subtarget.is64Bit()) {
489 Opcode = NVPTX::LD_i8_ari_64;
492 Opcode = NVPTX::LD_i16_ari_64;
495 Opcode = NVPTX::LD_i32_ari_64;
498 Opcode = NVPTX::LD_i64_ari_64;
501 Opcode = NVPTX::LD_f32_ari_64;
504 Opcode = NVPTX::LD_f64_ari_64;
512 Opcode = NVPTX::LD_i8_ari;
515 Opcode = NVPTX::LD_i16_ari;
518 Opcode = NVPTX::LD_i32_ari;
521 Opcode = NVPTX::LD_i64_ari;
524 Opcode = NVPTX::LD_f32_ari;
527 Opcode = NVPTX::LD_f64_ari;
533 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
534 getI32Imm(vecType), getI32Imm(fromType),
535 getI32Imm(fromTypeWidth), Base, Offset, Chain };
536 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
538 if (Subtarget.is64Bit()) {
541 Opcode = NVPTX::LD_i8_areg_64;
544 Opcode = NVPTX::LD_i16_areg_64;
547 Opcode = NVPTX::LD_i32_areg_64;
550 Opcode = NVPTX::LD_i64_areg_64;
553 Opcode = NVPTX::LD_f32_areg_64;
556 Opcode = NVPTX::LD_f64_areg_64;
564 Opcode = NVPTX::LD_i8_areg;
567 Opcode = NVPTX::LD_i16_areg;
570 Opcode = NVPTX::LD_i32_areg;
573 Opcode = NVPTX::LD_i64_areg;
576 Opcode = NVPTX::LD_f32_areg;
579 Opcode = NVPTX::LD_f64_areg;
585 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
586 getI32Imm(vecType), getI32Imm(fromType),
587 getI32Imm(fromTypeWidth), N1, Chain };
588 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
591 if (NVPTXLD != NULL) {
592 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
593 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
594 cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
600 SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
602 SDValue Chain = N->getOperand(0);
603 SDValue Op1 = N->getOperand(1);
604 SDValue Addr, Offset, Base;
608 MemSDNode *MemSD = cast<MemSDNode>(N);
609 EVT LoadedVT = MemSD->getMemoryVT();
611 if (!LoadedVT.isSimple())
614 // Address Space Setting
615 unsigned int CodeAddrSpace = getCodeAddrSpace(MemSD, Subtarget);
618 // - .volatile is only availalble for .global and .shared
619 bool IsVolatile = MemSD->isVolatile();
620 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
621 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
622 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
626 MVT SimpleVT = LoadedVT.getSimpleVT();
628 // Type Setting: fromType + fromTypeWidth
630 // Sign : ISD::SEXTLOAD
631 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
633 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
634 MVT ScalarVT = SimpleVT.getScalarType();
635 // Read at least 8 bits (predicates are stored as 8-bit values)
636 unsigned FromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
637 unsigned int FromType;
638 // The last operand holds the original LoadSDNode::getExtensionType() value
639 unsigned ExtensionType = cast<ConstantSDNode>(
640 N->getOperand(N->getNumOperands() - 1))->getZExtValue();
641 if (ExtensionType == ISD::SEXTLOAD)
642 FromType = NVPTX::PTXLdStInstCode::Signed;
643 else if (ScalarVT.isFloatingPoint())
644 FromType = NVPTX::PTXLdStInstCode::Float;
646 FromType = NVPTX::PTXLdStInstCode::Unsigned;
650 switch (N->getOpcode()) {
651 case NVPTXISD::LoadV2:
652 VecType = NVPTX::PTXLdStInstCode::V2;
654 case NVPTXISD::LoadV4:
655 VecType = NVPTX::PTXLdStInstCode::V4;
661 EVT EltVT = N->getValueType(0);
663 if (SelectDirectAddr(Op1, Addr)) {
664 switch (N->getOpcode()) {
667 case NVPTXISD::LoadV2:
668 switch (EltVT.getSimpleVT().SimpleTy) {
672 Opcode = NVPTX::LDV_i8_v2_avar;
675 Opcode = NVPTX::LDV_i16_v2_avar;
678 Opcode = NVPTX::LDV_i32_v2_avar;
681 Opcode = NVPTX::LDV_i64_v2_avar;
684 Opcode = NVPTX::LDV_f32_v2_avar;
687 Opcode = NVPTX::LDV_f64_v2_avar;
691 case NVPTXISD::LoadV4:
692 switch (EltVT.getSimpleVT().SimpleTy) {
696 Opcode = NVPTX::LDV_i8_v4_avar;
699 Opcode = NVPTX::LDV_i16_v4_avar;
702 Opcode = NVPTX::LDV_i32_v4_avar;
705 Opcode = NVPTX::LDV_f32_v4_avar;
711 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
712 getI32Imm(VecType), getI32Imm(FromType),
713 getI32Imm(FromTypeWidth), Addr, Chain };
714 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
715 } else if (Subtarget.is64Bit()
716 ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset)
717 : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
718 switch (N->getOpcode()) {
721 case NVPTXISD::LoadV2:
722 switch (EltVT.getSimpleVT().SimpleTy) {
726 Opcode = NVPTX::LDV_i8_v2_asi;
729 Opcode = NVPTX::LDV_i16_v2_asi;
732 Opcode = NVPTX::LDV_i32_v2_asi;
735 Opcode = NVPTX::LDV_i64_v2_asi;
738 Opcode = NVPTX::LDV_f32_v2_asi;
741 Opcode = NVPTX::LDV_f64_v2_asi;
745 case NVPTXISD::LoadV4:
746 switch (EltVT.getSimpleVT().SimpleTy) {
750 Opcode = NVPTX::LDV_i8_v4_asi;
753 Opcode = NVPTX::LDV_i16_v4_asi;
756 Opcode = NVPTX::LDV_i32_v4_asi;
759 Opcode = NVPTX::LDV_f32_v4_asi;
765 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
766 getI32Imm(VecType), getI32Imm(FromType),
767 getI32Imm(FromTypeWidth), Base, Offset, Chain };
768 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
769 } else if (Subtarget.is64Bit()
770 ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
771 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
772 if (Subtarget.is64Bit()) {
773 switch (N->getOpcode()) {
776 case NVPTXISD::LoadV2:
777 switch (EltVT.getSimpleVT().SimpleTy) {
781 Opcode = NVPTX::LDV_i8_v2_ari_64;
784 Opcode = NVPTX::LDV_i16_v2_ari_64;
787 Opcode = NVPTX::LDV_i32_v2_ari_64;
790 Opcode = NVPTX::LDV_i64_v2_ari_64;
793 Opcode = NVPTX::LDV_f32_v2_ari_64;
796 Opcode = NVPTX::LDV_f64_v2_ari_64;
800 case NVPTXISD::LoadV4:
801 switch (EltVT.getSimpleVT().SimpleTy) {
805 Opcode = NVPTX::LDV_i8_v4_ari_64;
808 Opcode = NVPTX::LDV_i16_v4_ari_64;
811 Opcode = NVPTX::LDV_i32_v4_ari_64;
814 Opcode = NVPTX::LDV_f32_v4_ari_64;
820 switch (N->getOpcode()) {
823 case NVPTXISD::LoadV2:
824 switch (EltVT.getSimpleVT().SimpleTy) {
828 Opcode = NVPTX::LDV_i8_v2_ari;
831 Opcode = NVPTX::LDV_i16_v2_ari;
834 Opcode = NVPTX::LDV_i32_v2_ari;
837 Opcode = NVPTX::LDV_i64_v2_ari;
840 Opcode = NVPTX::LDV_f32_v2_ari;
843 Opcode = NVPTX::LDV_f64_v2_ari;
847 case NVPTXISD::LoadV4:
848 switch (EltVT.getSimpleVT().SimpleTy) {
852 Opcode = NVPTX::LDV_i8_v4_ari;
855 Opcode = NVPTX::LDV_i16_v4_ari;
858 Opcode = NVPTX::LDV_i32_v4_ari;
861 Opcode = NVPTX::LDV_f32_v4_ari;
868 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
869 getI32Imm(VecType), getI32Imm(FromType),
870 getI32Imm(FromTypeWidth), Base, Offset, Chain };
872 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
874 if (Subtarget.is64Bit()) {
875 switch (N->getOpcode()) {
878 case NVPTXISD::LoadV2:
879 switch (EltVT.getSimpleVT().SimpleTy) {
883 Opcode = NVPTX::LDV_i8_v2_areg_64;
886 Opcode = NVPTX::LDV_i16_v2_areg_64;
889 Opcode = NVPTX::LDV_i32_v2_areg_64;
892 Opcode = NVPTX::LDV_i64_v2_areg_64;
895 Opcode = NVPTX::LDV_f32_v2_areg_64;
898 Opcode = NVPTX::LDV_f64_v2_areg_64;
902 case NVPTXISD::LoadV4:
903 switch (EltVT.getSimpleVT().SimpleTy) {
907 Opcode = NVPTX::LDV_i8_v4_areg_64;
910 Opcode = NVPTX::LDV_i16_v4_areg_64;
913 Opcode = NVPTX::LDV_i32_v4_areg_64;
916 Opcode = NVPTX::LDV_f32_v4_areg_64;
922 switch (N->getOpcode()) {
925 case NVPTXISD::LoadV2:
926 switch (EltVT.getSimpleVT().SimpleTy) {
930 Opcode = NVPTX::LDV_i8_v2_areg;
933 Opcode = NVPTX::LDV_i16_v2_areg;
936 Opcode = NVPTX::LDV_i32_v2_areg;
939 Opcode = NVPTX::LDV_i64_v2_areg;
942 Opcode = NVPTX::LDV_f32_v2_areg;
945 Opcode = NVPTX::LDV_f64_v2_areg;
949 case NVPTXISD::LoadV4:
950 switch (EltVT.getSimpleVT().SimpleTy) {
954 Opcode = NVPTX::LDV_i8_v4_areg;
957 Opcode = NVPTX::LDV_i16_v4_areg;
960 Opcode = NVPTX::LDV_i32_v4_areg;
963 Opcode = NVPTX::LDV_f32_v4_areg;
970 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
971 getI32Imm(VecType), getI32Imm(FromType),
972 getI32Imm(FromTypeWidth), Op1, Chain };
973 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
976 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
977 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
978 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
983 SDNode *NVPTXDAGToDAGISel::SelectLDGLDUVector(SDNode *N) {
985 SDValue Chain = N->getOperand(0);
986 SDValue Op1 = N->getOperand(1);
990 MemSDNode *Mem = cast<MemSDNode>(N);
991 SDValue Base, Offset, Addr;
993 EVT EltVT = Mem->getMemoryVT().getVectorElementType();
995 if (SelectDirectAddr(Op1, Addr)) {
996 switch (N->getOpcode()) {
999 case NVPTXISD::LDGV2:
1000 switch (EltVT.getSimpleVT().SimpleTy) {
1004 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_avar;
1007 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_avar;
1010 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_avar;
1013 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_avar;
1016 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_avar;
1019 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_avar;
1023 case NVPTXISD::LDUV2:
1024 switch (EltVT.getSimpleVT().SimpleTy) {
1028 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_avar;
1031 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_avar;
1034 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_avar;
1037 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_avar;
1040 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_avar;
1043 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_avar;
1047 case NVPTXISD::LDGV4:
1048 switch (EltVT.getSimpleVT().SimpleTy) {
1052 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_avar;
1055 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_avar;
1058 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_avar;
1061 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_avar;
1065 case NVPTXISD::LDUV4:
1066 switch (EltVT.getSimpleVT().SimpleTy) {
1070 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_avar;
1073 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_avar;
1076 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_avar;
1079 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_avar;
1085 SDValue Ops[] = { Addr, Chain };
1086 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
1087 ArrayRef<SDValue>(Ops, 2));
1088 } else if (Subtarget.is64Bit()
1089 ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1090 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1091 if (Subtarget.is64Bit()) {
1092 switch (N->getOpcode()) {
1095 case NVPTXISD::LDGV2:
1096 switch (EltVT.getSimpleVT().SimpleTy) {
1100 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari64;
1103 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari64;
1106 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari64;
1109 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari64;
1112 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari64;
1115 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari64;
1119 case NVPTXISD::LDUV2:
1120 switch (EltVT.getSimpleVT().SimpleTy) {
1124 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari64;
1127 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari64;
1130 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari64;
1133 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari64;
1136 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari64;
1139 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari64;
1143 case NVPTXISD::LDGV4:
1144 switch (EltVT.getSimpleVT().SimpleTy) {
1148 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari64;
1151 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari64;
1154 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari64;
1157 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari64;
1161 case NVPTXISD::LDUV4:
1162 switch (EltVT.getSimpleVT().SimpleTy) {
1166 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari64;
1169 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari64;
1172 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari64;
1175 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari64;
1181 switch (N->getOpcode()) {
1184 case NVPTXISD::LDGV2:
1185 switch (EltVT.getSimpleVT().SimpleTy) {
1189 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari32;
1192 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari32;
1195 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari32;
1198 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari32;
1201 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari32;
1204 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari32;
1208 case NVPTXISD::LDUV2:
1209 switch (EltVT.getSimpleVT().SimpleTy) {
1213 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari32;
1216 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari32;
1219 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari32;
1222 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari32;
1225 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari32;
1228 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari32;
1232 case NVPTXISD::LDGV4:
1233 switch (EltVT.getSimpleVT().SimpleTy) {
1237 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari32;
1240 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari32;
1243 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari32;
1246 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari32;
1250 case NVPTXISD::LDUV4:
1251 switch (EltVT.getSimpleVT().SimpleTy) {
1255 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari32;
1258 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari32;
1261 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari32;
1264 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari32;
1271 SDValue Ops[] = { Base, Offset, Chain };
1273 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
1274 ArrayRef<SDValue>(Ops, 3));
1276 if (Subtarget.is64Bit()) {
1277 switch (N->getOpcode()) {
1280 case NVPTXISD::LDGV2:
1281 switch (EltVT.getSimpleVT().SimpleTy) {
1285 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg64;
1288 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg64;
1291 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg64;
1294 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg64;
1297 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg64;
1300 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg64;
1304 case NVPTXISD::LDUV2:
1305 switch (EltVT.getSimpleVT().SimpleTy) {
1309 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg64;
1312 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg64;
1315 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg64;
1318 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg64;
1321 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg64;
1324 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg64;
1328 case NVPTXISD::LDGV4:
1329 switch (EltVT.getSimpleVT().SimpleTy) {
1333 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64;
1336 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg64;
1339 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg64;
1342 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg64;
1346 case NVPTXISD::LDUV4:
1347 switch (EltVT.getSimpleVT().SimpleTy) {
1351 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64;
1354 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg64;
1357 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg64;
1360 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg64;
1366 switch (N->getOpcode()) {
1369 case NVPTXISD::LDGV2:
1370 switch (EltVT.getSimpleVT().SimpleTy) {
1374 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg32;
1377 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg32;
1380 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg32;
1383 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg32;
1386 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg32;
1389 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg32;
1393 case NVPTXISD::LDUV2:
1394 switch (EltVT.getSimpleVT().SimpleTy) {
1398 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg32;
1401 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg32;
1404 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg32;
1407 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg32;
1410 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg32;
1413 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg32;
1417 case NVPTXISD::LDGV4:
1418 switch (EltVT.getSimpleVT().SimpleTy) {
1422 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32;
1425 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg32;
1428 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg32;
1431 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg32;
1435 case NVPTXISD::LDUV4:
1436 switch (EltVT.getSimpleVT().SimpleTy) {
1440 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32;
1443 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg32;
1446 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg32;
1449 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg32;
1456 SDValue Ops[] = { Op1, Chain };
1457 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
1458 ArrayRef<SDValue>(Ops, 2));
1461 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1462 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
1463 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1468 SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
1470 StoreSDNode *ST = cast<StoreSDNode>(N);
1471 EVT StoreVT = ST->getMemoryVT();
1472 SDNode *NVPTXST = NULL;
1474 // do not support pre/post inc/dec
1475 if (ST->isIndexed())
1478 if (!StoreVT.isSimple())
1481 // Address Space Setting
1482 unsigned int codeAddrSpace = getCodeAddrSpace(ST, Subtarget);
1485 // - .volatile is only availalble for .global and .shared
1486 bool isVolatile = ST->isVolatile();
1487 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
1488 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
1489 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
1493 MVT SimpleVT = StoreVT.getSimpleVT();
1494 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
1495 if (SimpleVT.isVector()) {
1496 unsigned num = SimpleVT.getVectorNumElements();
1498 vecType = NVPTX::PTXLdStInstCode::V2;
1500 vecType = NVPTX::PTXLdStInstCode::V4;
1505 // Type Setting: toType + toTypeWidth
1506 // - for integer type, always use 'u'
1508 MVT ScalarVT = SimpleVT.getScalarType();
1509 unsigned toTypeWidth = ScalarVT.getSizeInBits();
1510 unsigned int toType;
1511 if (ScalarVT.isFloatingPoint())
1512 toType = NVPTX::PTXLdStInstCode::Float;
1514 toType = NVPTX::PTXLdStInstCode::Unsigned;
1516 // Create the machine instruction DAG
1517 SDValue Chain = N->getOperand(0);
1518 SDValue N1 = N->getOperand(1);
1519 SDValue N2 = N->getOperand(2);
1521 SDValue Offset, Base;
1523 MVT::SimpleValueType SourceVT = N1.getNode()->getSimpleValueType(0).SimpleTy;
1525 if (SelectDirectAddr(N2, Addr)) {
1528 Opcode = NVPTX::ST_i8_avar;
1531 Opcode = NVPTX::ST_i16_avar;
1534 Opcode = NVPTX::ST_i32_avar;
1537 Opcode = NVPTX::ST_i64_avar;
1540 Opcode = NVPTX::ST_f32_avar;
1543 Opcode = NVPTX::ST_f64_avar;
1548 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
1549 getI32Imm(vecType), getI32Imm(toType),
1550 getI32Imm(toTypeWidth), Addr, Chain };
1551 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
1552 } else if (Subtarget.is64Bit()
1553 ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
1554 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
1557 Opcode = NVPTX::ST_i8_asi;
1560 Opcode = NVPTX::ST_i16_asi;
1563 Opcode = NVPTX::ST_i32_asi;
1566 Opcode = NVPTX::ST_i64_asi;
1569 Opcode = NVPTX::ST_f32_asi;
1572 Opcode = NVPTX::ST_f64_asi;
1577 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
1578 getI32Imm(vecType), getI32Imm(toType),
1579 getI32Imm(toTypeWidth), Base, Offset, Chain };
1580 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
1581 } else if (Subtarget.is64Bit()
1582 ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
1583 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
1584 if (Subtarget.is64Bit()) {
1587 Opcode = NVPTX::ST_i8_ari_64;
1590 Opcode = NVPTX::ST_i16_ari_64;
1593 Opcode = NVPTX::ST_i32_ari_64;
1596 Opcode = NVPTX::ST_i64_ari_64;
1599 Opcode = NVPTX::ST_f32_ari_64;
1602 Opcode = NVPTX::ST_f64_ari_64;
1610 Opcode = NVPTX::ST_i8_ari;
1613 Opcode = NVPTX::ST_i16_ari;
1616 Opcode = NVPTX::ST_i32_ari;
1619 Opcode = NVPTX::ST_i64_ari;
1622 Opcode = NVPTX::ST_f32_ari;
1625 Opcode = NVPTX::ST_f64_ari;
1631 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
1632 getI32Imm(vecType), getI32Imm(toType),
1633 getI32Imm(toTypeWidth), Base, Offset, Chain };
1634 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
1636 if (Subtarget.is64Bit()) {
1639 Opcode = NVPTX::ST_i8_areg_64;
1642 Opcode = NVPTX::ST_i16_areg_64;
1645 Opcode = NVPTX::ST_i32_areg_64;
1648 Opcode = NVPTX::ST_i64_areg_64;
1651 Opcode = NVPTX::ST_f32_areg_64;
1654 Opcode = NVPTX::ST_f64_areg_64;
1662 Opcode = NVPTX::ST_i8_areg;
1665 Opcode = NVPTX::ST_i16_areg;
1668 Opcode = NVPTX::ST_i32_areg;
1671 Opcode = NVPTX::ST_i64_areg;
1674 Opcode = NVPTX::ST_f32_areg;
1677 Opcode = NVPTX::ST_f64_areg;
1683 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
1684 getI32Imm(vecType), getI32Imm(toType),
1685 getI32Imm(toTypeWidth), N2, Chain };
1686 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
1689 if (NVPTXST != NULL) {
1690 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1691 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
1692 cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
1698 SDNode *NVPTXDAGToDAGISel::SelectStoreVector(SDNode *N) {
1699 SDValue Chain = N->getOperand(0);
1700 SDValue Op1 = N->getOperand(1);
1701 SDValue Addr, Offset, Base;
1705 EVT EltVT = Op1.getValueType();
1706 MemSDNode *MemSD = cast<MemSDNode>(N);
1707 EVT StoreVT = MemSD->getMemoryVT();
1709 // Address Space Setting
1710 unsigned CodeAddrSpace = getCodeAddrSpace(MemSD, Subtarget);
1712 if (CodeAddrSpace == NVPTX::PTXLdStInstCode::CONSTANT) {
1713 report_fatal_error("Cannot store to pointer that points to constant "
1718 // - .volatile is only availalble for .global and .shared
1719 bool IsVolatile = MemSD->isVolatile();
1720 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
1721 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
1722 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
1725 // Type Setting: toType + toTypeWidth
1726 // - for integer type, always use 'u'
1727 assert(StoreVT.isSimple() && "Store value is not simple");
1728 MVT ScalarVT = StoreVT.getSimpleVT().getScalarType();
1729 unsigned ToTypeWidth = ScalarVT.getSizeInBits();
1731 if (ScalarVT.isFloatingPoint())
1732 ToType = NVPTX::PTXLdStInstCode::Float;
1734 ToType = NVPTX::PTXLdStInstCode::Unsigned;
1736 SmallVector<SDValue, 12> StOps;
1740 switch (N->getOpcode()) {
1741 case NVPTXISD::StoreV2:
1742 VecType = NVPTX::PTXLdStInstCode::V2;
1743 StOps.push_back(N->getOperand(1));
1744 StOps.push_back(N->getOperand(2));
1745 N2 = N->getOperand(3);
1747 case NVPTXISD::StoreV4:
1748 VecType = NVPTX::PTXLdStInstCode::V4;
1749 StOps.push_back(N->getOperand(1));
1750 StOps.push_back(N->getOperand(2));
1751 StOps.push_back(N->getOperand(3));
1752 StOps.push_back(N->getOperand(4));
1753 N2 = N->getOperand(5);
1759 StOps.push_back(getI32Imm(IsVolatile));
1760 StOps.push_back(getI32Imm(CodeAddrSpace));
1761 StOps.push_back(getI32Imm(VecType));
1762 StOps.push_back(getI32Imm(ToType));
1763 StOps.push_back(getI32Imm(ToTypeWidth));
1765 if (SelectDirectAddr(N2, Addr)) {
1766 switch (N->getOpcode()) {
1769 case NVPTXISD::StoreV2:
1770 switch (EltVT.getSimpleVT().SimpleTy) {
1774 Opcode = NVPTX::STV_i8_v2_avar;
1777 Opcode = NVPTX::STV_i16_v2_avar;
1780 Opcode = NVPTX::STV_i32_v2_avar;
1783 Opcode = NVPTX::STV_i64_v2_avar;
1786 Opcode = NVPTX::STV_f32_v2_avar;
1789 Opcode = NVPTX::STV_f64_v2_avar;
1793 case NVPTXISD::StoreV4:
1794 switch (EltVT.getSimpleVT().SimpleTy) {
1798 Opcode = NVPTX::STV_i8_v4_avar;
1801 Opcode = NVPTX::STV_i16_v4_avar;
1804 Opcode = NVPTX::STV_i32_v4_avar;
1807 Opcode = NVPTX::STV_f32_v4_avar;
1812 StOps.push_back(Addr);
1813 } else if (Subtarget.is64Bit()
1814 ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
1815 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
1816 switch (N->getOpcode()) {
1819 case NVPTXISD::StoreV2:
1820 switch (EltVT.getSimpleVT().SimpleTy) {
1824 Opcode = NVPTX::STV_i8_v2_asi;
1827 Opcode = NVPTX::STV_i16_v2_asi;
1830 Opcode = NVPTX::STV_i32_v2_asi;
1833 Opcode = NVPTX::STV_i64_v2_asi;
1836 Opcode = NVPTX::STV_f32_v2_asi;
1839 Opcode = NVPTX::STV_f64_v2_asi;
1843 case NVPTXISD::StoreV4:
1844 switch (EltVT.getSimpleVT().SimpleTy) {
1848 Opcode = NVPTX::STV_i8_v4_asi;
1851 Opcode = NVPTX::STV_i16_v4_asi;
1854 Opcode = NVPTX::STV_i32_v4_asi;
1857 Opcode = NVPTX::STV_f32_v4_asi;
1862 StOps.push_back(Base);
1863 StOps.push_back(Offset);
1864 } else if (Subtarget.is64Bit()
1865 ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
1866 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
1867 if (Subtarget.is64Bit()) {
1868 switch (N->getOpcode()) {
1871 case NVPTXISD::StoreV2:
1872 switch (EltVT.getSimpleVT().SimpleTy) {
1876 Opcode = NVPTX::STV_i8_v2_ari_64;
1879 Opcode = NVPTX::STV_i16_v2_ari_64;
1882 Opcode = NVPTX::STV_i32_v2_ari_64;
1885 Opcode = NVPTX::STV_i64_v2_ari_64;
1888 Opcode = NVPTX::STV_f32_v2_ari_64;
1891 Opcode = NVPTX::STV_f64_v2_ari_64;
1895 case NVPTXISD::StoreV4:
1896 switch (EltVT.getSimpleVT().SimpleTy) {
1900 Opcode = NVPTX::STV_i8_v4_ari_64;
1903 Opcode = NVPTX::STV_i16_v4_ari_64;
1906 Opcode = NVPTX::STV_i32_v4_ari_64;
1909 Opcode = NVPTX::STV_f32_v4_ari_64;
1915 switch (N->getOpcode()) {
1918 case NVPTXISD::StoreV2:
1919 switch (EltVT.getSimpleVT().SimpleTy) {
1923 Opcode = NVPTX::STV_i8_v2_ari;
1926 Opcode = NVPTX::STV_i16_v2_ari;
1929 Opcode = NVPTX::STV_i32_v2_ari;
1932 Opcode = NVPTX::STV_i64_v2_ari;
1935 Opcode = NVPTX::STV_f32_v2_ari;
1938 Opcode = NVPTX::STV_f64_v2_ari;
1942 case NVPTXISD::StoreV4:
1943 switch (EltVT.getSimpleVT().SimpleTy) {
1947 Opcode = NVPTX::STV_i8_v4_ari;
1950 Opcode = NVPTX::STV_i16_v4_ari;
1953 Opcode = NVPTX::STV_i32_v4_ari;
1956 Opcode = NVPTX::STV_f32_v4_ari;
1962 StOps.push_back(Base);
1963 StOps.push_back(Offset);
1965 if (Subtarget.is64Bit()) {
1966 switch (N->getOpcode()) {
1969 case NVPTXISD::StoreV2:
1970 switch (EltVT.getSimpleVT().SimpleTy) {
1974 Opcode = NVPTX::STV_i8_v2_areg_64;
1977 Opcode = NVPTX::STV_i16_v2_areg_64;
1980 Opcode = NVPTX::STV_i32_v2_areg_64;
1983 Opcode = NVPTX::STV_i64_v2_areg_64;
1986 Opcode = NVPTX::STV_f32_v2_areg_64;
1989 Opcode = NVPTX::STV_f64_v2_areg_64;
1993 case NVPTXISD::StoreV4:
1994 switch (EltVT.getSimpleVT().SimpleTy) {
1998 Opcode = NVPTX::STV_i8_v4_areg_64;
2001 Opcode = NVPTX::STV_i16_v4_areg_64;
2004 Opcode = NVPTX::STV_i32_v4_areg_64;
2007 Opcode = NVPTX::STV_f32_v4_areg_64;
2013 switch (N->getOpcode()) {
2016 case NVPTXISD::StoreV2:
2017 switch (EltVT.getSimpleVT().SimpleTy) {
2021 Opcode = NVPTX::STV_i8_v2_areg;
2024 Opcode = NVPTX::STV_i16_v2_areg;
2027 Opcode = NVPTX::STV_i32_v2_areg;
2030 Opcode = NVPTX::STV_i64_v2_areg;
2033 Opcode = NVPTX::STV_f32_v2_areg;
2036 Opcode = NVPTX::STV_f64_v2_areg;
2040 case NVPTXISD::StoreV4:
2041 switch (EltVT.getSimpleVT().SimpleTy) {
2045 Opcode = NVPTX::STV_i8_v4_areg;
2048 Opcode = NVPTX::STV_i16_v4_areg;
2051 Opcode = NVPTX::STV_i32_v4_areg;
2054 Opcode = NVPTX::STV_f32_v4_areg;
2060 StOps.push_back(N2);
2063 StOps.push_back(Chain);
2065 ST = CurDAG->getMachineNode(Opcode, DL, MVT::Other, StOps);
2067 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2068 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2069 cast<MachineSDNode>(ST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2074 SDNode *NVPTXDAGToDAGISel::SelectLoadParam(SDNode *Node) {
2075 SDValue Chain = Node->getOperand(0);
2076 SDValue Offset = Node->getOperand(2);
2077 SDValue Flag = Node->getOperand(3);
2079 MemSDNode *Mem = cast<MemSDNode>(Node);
2082 switch (Node->getOpcode()) {
2085 case NVPTXISD::LoadParam:
2088 case NVPTXISD::LoadParamV2:
2091 case NVPTXISD::LoadParamV4:
2096 EVT EltVT = Node->getValueType(0);
2097 EVT MemVT = Mem->getMemoryVT();
2105 switch (MemVT.getSimpleVT().SimpleTy) {
2109 Opc = NVPTX::LoadParamMemI8;
2112 Opc = NVPTX::LoadParamMemI8;
2115 Opc = NVPTX::LoadParamMemI16;
2118 Opc = NVPTX::LoadParamMemI32;
2121 Opc = NVPTX::LoadParamMemI64;
2124 Opc = NVPTX::LoadParamMemF32;
2127 Opc = NVPTX::LoadParamMemF64;
2132 switch (MemVT.getSimpleVT().SimpleTy) {
2136 Opc = NVPTX::LoadParamMemV2I8;
2139 Opc = NVPTX::LoadParamMemV2I8;
2142 Opc = NVPTX::LoadParamMemV2I16;
2145 Opc = NVPTX::LoadParamMemV2I32;
2148 Opc = NVPTX::LoadParamMemV2I64;
2151 Opc = NVPTX::LoadParamMemV2F32;
2154 Opc = NVPTX::LoadParamMemV2F64;
2159 switch (MemVT.getSimpleVT().SimpleTy) {
2163 Opc = NVPTX::LoadParamMemV4I8;
2166 Opc = NVPTX::LoadParamMemV4I8;
2169 Opc = NVPTX::LoadParamMemV4I16;
2172 Opc = NVPTX::LoadParamMemV4I32;
2175 Opc = NVPTX::LoadParamMemV4F32;
2183 VTs = CurDAG->getVTList(EltVT, MVT::Other, MVT::Glue);
2184 } else if (VecSize == 2) {
2185 VTs = CurDAG->getVTList(EltVT, EltVT, MVT::Other, MVT::Glue);
2187 EVT EVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other, MVT::Glue };
2188 VTs = CurDAG->getVTList(EVTs);
2191 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2193 SmallVector<SDValue, 2> Ops;
2194 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2195 Ops.push_back(Chain);
2196 Ops.push_back(Flag);
2199 CurDAG->getMachineNode(Opc, DL, VTs, Ops);
2203 SDNode *NVPTXDAGToDAGISel::SelectStoreRetval(SDNode *N) {
2205 SDValue Chain = N->getOperand(0);
2206 SDValue Offset = N->getOperand(1);
2207 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2208 MemSDNode *Mem = cast<MemSDNode>(N);
2210 // How many elements do we have?
2211 unsigned NumElts = 1;
2212 switch (N->getOpcode()) {
2215 case NVPTXISD::StoreRetval:
2218 case NVPTXISD::StoreRetvalV2:
2221 case NVPTXISD::StoreRetvalV4:
2226 // Build vector of operands
2227 SmallVector<SDValue, 6> Ops;
2228 for (unsigned i = 0; i < NumElts; ++i)
2229 Ops.push_back(N->getOperand(i + 2));
2230 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2231 Ops.push_back(Chain);
2233 // Determine target opcode
2234 // If we have an i1, use an 8-bit store. The lowering code in
2235 // NVPTXISelLowering will have already emitted an upcast.
2236 unsigned Opcode = 0;
2241 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2245 Opcode = NVPTX::StoreRetvalI8;
2248 Opcode = NVPTX::StoreRetvalI8;
2251 Opcode = NVPTX::StoreRetvalI16;
2254 Opcode = NVPTX::StoreRetvalI32;
2257 Opcode = NVPTX::StoreRetvalI64;
2260 Opcode = NVPTX::StoreRetvalF32;
2263 Opcode = NVPTX::StoreRetvalF64;
2268 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2272 Opcode = NVPTX::StoreRetvalV2I8;
2275 Opcode = NVPTX::StoreRetvalV2I8;
2278 Opcode = NVPTX::StoreRetvalV2I16;
2281 Opcode = NVPTX::StoreRetvalV2I32;
2284 Opcode = NVPTX::StoreRetvalV2I64;
2287 Opcode = NVPTX::StoreRetvalV2F32;
2290 Opcode = NVPTX::StoreRetvalV2F64;
2295 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2299 Opcode = NVPTX::StoreRetvalV4I8;
2302 Opcode = NVPTX::StoreRetvalV4I8;
2305 Opcode = NVPTX::StoreRetvalV4I16;
2308 Opcode = NVPTX::StoreRetvalV4I32;
2311 Opcode = NVPTX::StoreRetvalV4F32;
2318 CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
2319 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2320 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2321 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
2326 SDNode *NVPTXDAGToDAGISel::SelectStoreParam(SDNode *N) {
2328 SDValue Chain = N->getOperand(0);
2329 SDValue Param = N->getOperand(1);
2330 unsigned ParamVal = cast<ConstantSDNode>(Param)->getZExtValue();
2331 SDValue Offset = N->getOperand(2);
2332 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2333 MemSDNode *Mem = cast<MemSDNode>(N);
2334 SDValue Flag = N->getOperand(N->getNumOperands() - 1);
2336 // How many elements do we have?
2337 unsigned NumElts = 1;
2338 switch (N->getOpcode()) {
2341 case NVPTXISD::StoreParamU32:
2342 case NVPTXISD::StoreParamS32:
2343 case NVPTXISD::StoreParam:
2346 case NVPTXISD::StoreParamV2:
2349 case NVPTXISD::StoreParamV4:
2354 // Build vector of operands
2355 SmallVector<SDValue, 8> Ops;
2356 for (unsigned i = 0; i < NumElts; ++i)
2357 Ops.push_back(N->getOperand(i + 3));
2358 Ops.push_back(CurDAG->getTargetConstant(ParamVal, MVT::i32));
2359 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2360 Ops.push_back(Chain);
2361 Ops.push_back(Flag);
2363 // Determine target opcode
2364 // If we have an i1, use an 8-bit store. The lowering code in
2365 // NVPTXISelLowering will have already emitted an upcast.
2366 unsigned Opcode = 0;
2367 switch (N->getOpcode()) {
2373 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2377 Opcode = NVPTX::StoreParamI8;
2380 Opcode = NVPTX::StoreParamI8;
2383 Opcode = NVPTX::StoreParamI16;
2386 Opcode = NVPTX::StoreParamI32;
2389 Opcode = NVPTX::StoreParamI64;
2392 Opcode = NVPTX::StoreParamF32;
2395 Opcode = NVPTX::StoreParamF64;
2400 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2404 Opcode = NVPTX::StoreParamV2I8;
2407 Opcode = NVPTX::StoreParamV2I8;
2410 Opcode = NVPTX::StoreParamV2I16;
2413 Opcode = NVPTX::StoreParamV2I32;
2416 Opcode = NVPTX::StoreParamV2I64;
2419 Opcode = NVPTX::StoreParamV2F32;
2422 Opcode = NVPTX::StoreParamV2F64;
2427 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2431 Opcode = NVPTX::StoreParamV4I8;
2434 Opcode = NVPTX::StoreParamV4I8;
2437 Opcode = NVPTX::StoreParamV4I16;
2440 Opcode = NVPTX::StoreParamV4I32;
2443 Opcode = NVPTX::StoreParamV4F32;
2449 // Special case: if we have a sign-extend/zero-extend node, insert the
2450 // conversion instruction first, and use that as the value operand to
2451 // the selected StoreParam node.
2452 case NVPTXISD::StoreParamU32: {
2453 Opcode = NVPTX::StoreParamI32;
2454 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
2456 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL,
2457 MVT::i32, Ops[0], CvtNone);
2458 Ops[0] = SDValue(Cvt, 0);
2461 case NVPTXISD::StoreParamS32: {
2462 Opcode = NVPTX::StoreParamI32;
2463 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
2465 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL,
2466 MVT::i32, Ops[0], CvtNone);
2467 Ops[0] = SDValue(Cvt, 0);
2472 SDVTList RetVTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2474 CurDAG->getMachineNode(Opcode, DL, RetVTs, Ops);
2475 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2476 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2477 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
2482 SDNode *NVPTXDAGToDAGISel::SelectTextureIntrinsic(SDNode *N) {
2483 SDValue Chain = N->getOperand(0);
2484 SDValue TexRef = N->getOperand(1);
2485 SDValue SampRef = N->getOperand(2);
2488 SmallVector<SDValue, 8> Ops;
2490 switch (N->getOpcode()) {
2491 default: return NULL;
2492 case NVPTXISD::Tex1DFloatI32:
2493 Opc = NVPTX::TEX_1D_F32_I32;
2495 case NVPTXISD::Tex1DFloatFloat:
2496 Opc = NVPTX::TEX_1D_F32_F32;
2498 case NVPTXISD::Tex1DFloatFloatLevel:
2499 Opc = NVPTX::TEX_1D_F32_F32_LEVEL;
2501 case NVPTXISD::Tex1DFloatFloatGrad:
2502 Opc = NVPTX::TEX_1D_F32_F32_GRAD;
2504 case NVPTXISD::Tex1DI32I32:
2505 Opc = NVPTX::TEX_1D_I32_I32;
2507 case NVPTXISD::Tex1DI32Float:
2508 Opc = NVPTX::TEX_1D_I32_F32;
2510 case NVPTXISD::Tex1DI32FloatLevel:
2511 Opc = NVPTX::TEX_1D_I32_F32_LEVEL;
2513 case NVPTXISD::Tex1DI32FloatGrad:
2514 Opc = NVPTX::TEX_1D_I32_F32_GRAD;
2516 case NVPTXISD::Tex1DArrayFloatI32:
2517 Opc = NVPTX::TEX_1D_ARRAY_F32_I32;
2519 case NVPTXISD::Tex1DArrayFloatFloat:
2520 Opc = NVPTX::TEX_1D_ARRAY_F32_F32;
2522 case NVPTXISD::Tex1DArrayFloatFloatLevel:
2523 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL;
2525 case NVPTXISD::Tex1DArrayFloatFloatGrad:
2526 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_GRAD;
2528 case NVPTXISD::Tex1DArrayI32I32:
2529 Opc = NVPTX::TEX_1D_ARRAY_I32_I32;
2531 case NVPTXISD::Tex1DArrayI32Float:
2532 Opc = NVPTX::TEX_1D_ARRAY_I32_F32;
2534 case NVPTXISD::Tex1DArrayI32FloatLevel:
2535 Opc = NVPTX::TEX_1D_ARRAY_I32_F32_LEVEL;
2537 case NVPTXISD::Tex1DArrayI32FloatGrad:
2538 Opc = NVPTX::TEX_1D_ARRAY_I32_F32_GRAD;
2540 case NVPTXISD::Tex2DFloatI32:
2541 Opc = NVPTX::TEX_2D_F32_I32;
2543 case NVPTXISD::Tex2DFloatFloat:
2544 Opc = NVPTX::TEX_2D_F32_F32;
2546 case NVPTXISD::Tex2DFloatFloatLevel:
2547 Opc = NVPTX::TEX_2D_F32_F32_LEVEL;
2549 case NVPTXISD::Tex2DFloatFloatGrad:
2550 Opc = NVPTX::TEX_2D_F32_F32_GRAD;
2552 case NVPTXISD::Tex2DI32I32:
2553 Opc = NVPTX::TEX_2D_I32_I32;
2555 case NVPTXISD::Tex2DI32Float:
2556 Opc = NVPTX::TEX_2D_I32_F32;
2558 case NVPTXISD::Tex2DI32FloatLevel:
2559 Opc = NVPTX::TEX_2D_I32_F32_LEVEL;
2561 case NVPTXISD::Tex2DI32FloatGrad:
2562 Opc = NVPTX::TEX_2D_I32_F32_GRAD;
2564 case NVPTXISD::Tex2DArrayFloatI32:
2565 Opc = NVPTX::TEX_2D_ARRAY_F32_I32;
2567 case NVPTXISD::Tex2DArrayFloatFloat:
2568 Opc = NVPTX::TEX_2D_ARRAY_F32_F32;
2570 case NVPTXISD::Tex2DArrayFloatFloatLevel:
2571 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL;
2573 case NVPTXISD::Tex2DArrayFloatFloatGrad:
2574 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_GRAD;
2576 case NVPTXISD::Tex2DArrayI32I32:
2577 Opc = NVPTX::TEX_2D_ARRAY_I32_I32;
2579 case NVPTXISD::Tex2DArrayI32Float:
2580 Opc = NVPTX::TEX_2D_ARRAY_I32_F32;
2582 case NVPTXISD::Tex2DArrayI32FloatLevel:
2583 Opc = NVPTX::TEX_2D_ARRAY_I32_F32_LEVEL;
2585 case NVPTXISD::Tex2DArrayI32FloatGrad:
2586 Opc = NVPTX::TEX_2D_ARRAY_I32_F32_GRAD;
2588 case NVPTXISD::Tex3DFloatI32:
2589 Opc = NVPTX::TEX_3D_F32_I32;
2591 case NVPTXISD::Tex3DFloatFloat:
2592 Opc = NVPTX::TEX_3D_F32_F32;
2594 case NVPTXISD::Tex3DFloatFloatLevel:
2595 Opc = NVPTX::TEX_3D_F32_F32_LEVEL;
2597 case NVPTXISD::Tex3DFloatFloatGrad:
2598 Opc = NVPTX::TEX_3D_F32_F32_GRAD;
2600 case NVPTXISD::Tex3DI32I32:
2601 Opc = NVPTX::TEX_3D_I32_I32;
2603 case NVPTXISD::Tex3DI32Float:
2604 Opc = NVPTX::TEX_3D_I32_F32;
2606 case NVPTXISD::Tex3DI32FloatLevel:
2607 Opc = NVPTX::TEX_3D_I32_F32_LEVEL;
2609 case NVPTXISD::Tex3DI32FloatGrad:
2610 Opc = NVPTX::TEX_3D_I32_F32_GRAD;
2614 Ops.push_back(TexRef);
2615 Ops.push_back(SampRef);
2617 // Copy over indices
2618 for (unsigned i = 3; i < N->getNumOperands(); ++i) {
2619 Ops.push_back(N->getOperand(i));
2622 Ops.push_back(Chain);
2623 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
2627 SDNode *NVPTXDAGToDAGISel::SelectSurfaceIntrinsic(SDNode *N) {
2628 SDValue Chain = N->getOperand(0);
2629 SDValue TexHandle = N->getOperand(1);
2632 SmallVector<SDValue, 8> Ops;
2633 switch (N->getOpcode()) {
2634 default: return NULL;
2635 case NVPTXISD::Suld1DI8Trap:
2636 Opc = NVPTX::SULD_1D_I8_TRAP;
2637 Ops.push_back(TexHandle);
2638 Ops.push_back(N->getOperand(2));
2639 Ops.push_back(Chain);
2641 case NVPTXISD::Suld1DI16Trap:
2642 Opc = NVPTX::SULD_1D_I16_TRAP;
2643 Ops.push_back(TexHandle);
2644 Ops.push_back(N->getOperand(2));
2645 Ops.push_back(Chain);
2647 case NVPTXISD::Suld1DI32Trap:
2648 Opc = NVPTX::SULD_1D_I32_TRAP;
2649 Ops.push_back(TexHandle);
2650 Ops.push_back(N->getOperand(2));
2651 Ops.push_back(Chain);
2653 case NVPTXISD::Suld1DV2I8Trap:
2654 Opc = NVPTX::SULD_1D_V2I8_TRAP;
2655 Ops.push_back(TexHandle);
2656 Ops.push_back(N->getOperand(2));
2657 Ops.push_back(Chain);
2659 case NVPTXISD::Suld1DV2I16Trap:
2660 Opc = NVPTX::SULD_1D_V2I16_TRAP;
2661 Ops.push_back(TexHandle);
2662 Ops.push_back(N->getOperand(2));
2663 Ops.push_back(Chain);
2665 case NVPTXISD::Suld1DV2I32Trap:
2666 Opc = NVPTX::SULD_1D_V2I32_TRAP;
2667 Ops.push_back(TexHandle);
2668 Ops.push_back(N->getOperand(2));
2669 Ops.push_back(Chain);
2671 case NVPTXISD::Suld1DV4I8Trap:
2672 Opc = NVPTX::SULD_1D_V4I8_TRAP;
2673 Ops.push_back(TexHandle);
2674 Ops.push_back(N->getOperand(2));
2675 Ops.push_back(Chain);
2677 case NVPTXISD::Suld1DV4I16Trap:
2678 Opc = NVPTX::SULD_1D_V4I16_TRAP;
2679 Ops.push_back(TexHandle);
2680 Ops.push_back(N->getOperand(2));
2681 Ops.push_back(Chain);
2683 case NVPTXISD::Suld1DV4I32Trap:
2684 Opc = NVPTX::SULD_1D_V4I32_TRAP;
2685 Ops.push_back(TexHandle);
2686 Ops.push_back(N->getOperand(2));
2687 Ops.push_back(Chain);
2689 case NVPTXISD::Suld1DArrayI8Trap:
2690 Opc = NVPTX::SULD_1D_ARRAY_I8_TRAP;
2691 Ops.push_back(TexHandle);
2692 Ops.push_back(N->getOperand(2));
2693 Ops.push_back(N->getOperand(3));
2694 Ops.push_back(Chain);
2696 case NVPTXISD::Suld1DArrayI16Trap:
2697 Opc = NVPTX::SULD_1D_ARRAY_I16_TRAP;
2698 Ops.push_back(TexHandle);
2699 Ops.push_back(N->getOperand(2));
2700 Ops.push_back(N->getOperand(3));
2701 Ops.push_back(Chain);
2703 case NVPTXISD::Suld1DArrayI32Trap:
2704 Opc = NVPTX::SULD_1D_ARRAY_I32_TRAP;
2705 Ops.push_back(TexHandle);
2706 Ops.push_back(N->getOperand(2));
2707 Ops.push_back(N->getOperand(3));
2708 Ops.push_back(Chain);
2710 case NVPTXISD::Suld1DArrayV2I8Trap:
2711 Opc = NVPTX::SULD_1D_ARRAY_V2I8_TRAP;
2712 Ops.push_back(TexHandle);
2713 Ops.push_back(N->getOperand(2));
2714 Ops.push_back(N->getOperand(3));
2715 Ops.push_back(Chain);
2717 case NVPTXISD::Suld1DArrayV2I16Trap:
2718 Opc = NVPTX::SULD_1D_ARRAY_V2I16_TRAP;
2719 Ops.push_back(TexHandle);
2720 Ops.push_back(N->getOperand(2));
2721 Ops.push_back(N->getOperand(3));
2722 Ops.push_back(Chain);
2724 case NVPTXISD::Suld1DArrayV2I32Trap:
2725 Opc = NVPTX::SULD_1D_ARRAY_V2I32_TRAP;
2726 Ops.push_back(TexHandle);
2727 Ops.push_back(N->getOperand(2));
2728 Ops.push_back(N->getOperand(3));
2729 Ops.push_back(Chain);
2731 case NVPTXISD::Suld1DArrayV4I8Trap:
2732 Opc = NVPTX::SULD_1D_ARRAY_V4I8_TRAP;
2733 Ops.push_back(TexHandle);
2734 Ops.push_back(N->getOperand(2));
2735 Ops.push_back(N->getOperand(3));
2736 Ops.push_back(Chain);
2738 case NVPTXISD::Suld1DArrayV4I16Trap:
2739 Opc = NVPTX::SULD_1D_ARRAY_V4I16_TRAP;
2740 Ops.push_back(TexHandle);
2741 Ops.push_back(N->getOperand(2));
2742 Ops.push_back(N->getOperand(3));
2743 Ops.push_back(Chain);
2745 case NVPTXISD::Suld1DArrayV4I32Trap:
2746 Opc = NVPTX::SULD_1D_ARRAY_V4I32_TRAP;
2747 Ops.push_back(TexHandle);
2748 Ops.push_back(N->getOperand(2));
2749 Ops.push_back(N->getOperand(3));
2750 Ops.push_back(Chain);
2752 case NVPTXISD::Suld2DI8Trap:
2753 Opc = NVPTX::SULD_2D_I8_TRAP;
2754 Ops.push_back(TexHandle);
2755 Ops.push_back(N->getOperand(2));
2756 Ops.push_back(N->getOperand(3));
2757 Ops.push_back(Chain);
2759 case NVPTXISD::Suld2DI16Trap:
2760 Opc = NVPTX::SULD_2D_I16_TRAP;
2761 Ops.push_back(TexHandle);
2762 Ops.push_back(N->getOperand(2));
2763 Ops.push_back(N->getOperand(3));
2764 Ops.push_back(Chain);
2766 case NVPTXISD::Suld2DI32Trap:
2767 Opc = NVPTX::SULD_2D_I32_TRAP;
2768 Ops.push_back(TexHandle);
2769 Ops.push_back(N->getOperand(2));
2770 Ops.push_back(N->getOperand(3));
2771 Ops.push_back(Chain);
2773 case NVPTXISD::Suld2DV2I8Trap:
2774 Opc = NVPTX::SULD_2D_V2I8_TRAP;
2775 Ops.push_back(TexHandle);
2776 Ops.push_back(N->getOperand(2));
2777 Ops.push_back(N->getOperand(3));
2778 Ops.push_back(Chain);
2780 case NVPTXISD::Suld2DV2I16Trap:
2781 Opc = NVPTX::SULD_2D_V2I16_TRAP;
2782 Ops.push_back(TexHandle);
2783 Ops.push_back(N->getOperand(2));
2784 Ops.push_back(N->getOperand(3));
2785 Ops.push_back(Chain);
2787 case NVPTXISD::Suld2DV2I32Trap:
2788 Opc = NVPTX::SULD_2D_V2I32_TRAP;
2789 Ops.push_back(TexHandle);
2790 Ops.push_back(N->getOperand(2));
2791 Ops.push_back(N->getOperand(3));
2792 Ops.push_back(Chain);
2794 case NVPTXISD::Suld2DV4I8Trap:
2795 Opc = NVPTX::SULD_2D_V4I8_TRAP;
2796 Ops.push_back(TexHandle);
2797 Ops.push_back(N->getOperand(2));
2798 Ops.push_back(N->getOperand(3));
2799 Ops.push_back(Chain);
2801 case NVPTXISD::Suld2DV4I16Trap:
2802 Opc = NVPTX::SULD_2D_V4I16_TRAP;
2803 Ops.push_back(TexHandle);
2804 Ops.push_back(N->getOperand(2));
2805 Ops.push_back(N->getOperand(3));
2806 Ops.push_back(Chain);
2808 case NVPTXISD::Suld2DV4I32Trap:
2809 Opc = NVPTX::SULD_2D_V4I32_TRAP;
2810 Ops.push_back(TexHandle);
2811 Ops.push_back(N->getOperand(2));
2812 Ops.push_back(N->getOperand(3));
2813 Ops.push_back(Chain);
2815 case NVPTXISD::Suld2DArrayI8Trap:
2816 Opc = NVPTX::SULD_2D_ARRAY_I8_TRAP;
2817 Ops.push_back(TexHandle);
2818 Ops.push_back(N->getOperand(2));
2819 Ops.push_back(N->getOperand(3));
2820 Ops.push_back(N->getOperand(4));
2821 Ops.push_back(Chain);
2823 case NVPTXISD::Suld2DArrayI16Trap:
2824 Opc = NVPTX::SULD_2D_ARRAY_I16_TRAP;
2825 Ops.push_back(TexHandle);
2826 Ops.push_back(N->getOperand(2));
2827 Ops.push_back(N->getOperand(3));
2828 Ops.push_back(N->getOperand(4));
2829 Ops.push_back(Chain);
2831 case NVPTXISD::Suld2DArrayI32Trap:
2832 Opc = NVPTX::SULD_2D_ARRAY_I32_TRAP;
2833 Ops.push_back(TexHandle);
2834 Ops.push_back(N->getOperand(2));
2835 Ops.push_back(N->getOperand(3));
2836 Ops.push_back(N->getOperand(4));
2837 Ops.push_back(Chain);
2839 case NVPTXISD::Suld2DArrayV2I8Trap:
2840 Opc = NVPTX::SULD_2D_ARRAY_V2I8_TRAP;
2841 Ops.push_back(TexHandle);
2842 Ops.push_back(N->getOperand(2));
2843 Ops.push_back(N->getOperand(3));
2844 Ops.push_back(N->getOperand(4));
2845 Ops.push_back(Chain);
2847 case NVPTXISD::Suld2DArrayV2I16Trap:
2848 Opc = NVPTX::SULD_2D_ARRAY_V2I16_TRAP;
2849 Ops.push_back(TexHandle);
2850 Ops.push_back(N->getOperand(2));
2851 Ops.push_back(N->getOperand(3));
2852 Ops.push_back(N->getOperand(4));
2853 Ops.push_back(Chain);
2855 case NVPTXISD::Suld2DArrayV2I32Trap:
2856 Opc = NVPTX::SULD_2D_ARRAY_V2I32_TRAP;
2857 Ops.push_back(TexHandle);
2858 Ops.push_back(N->getOperand(2));
2859 Ops.push_back(N->getOperand(3));
2860 Ops.push_back(N->getOperand(4));
2861 Ops.push_back(Chain);
2863 case NVPTXISD::Suld2DArrayV4I8Trap:
2864 Opc = NVPTX::SULD_2D_ARRAY_V4I8_TRAP;
2865 Ops.push_back(TexHandle);
2866 Ops.push_back(N->getOperand(2));
2867 Ops.push_back(N->getOperand(3));
2868 Ops.push_back(N->getOperand(4));
2869 Ops.push_back(Chain);
2871 case NVPTXISD::Suld2DArrayV4I16Trap:
2872 Opc = NVPTX::SULD_2D_ARRAY_V4I16_TRAP;
2873 Ops.push_back(TexHandle);
2874 Ops.push_back(N->getOperand(2));
2875 Ops.push_back(N->getOperand(3));
2876 Ops.push_back(N->getOperand(4));
2877 Ops.push_back(Chain);
2879 case NVPTXISD::Suld2DArrayV4I32Trap:
2880 Opc = NVPTX::SULD_2D_ARRAY_V4I32_TRAP;
2881 Ops.push_back(TexHandle);
2882 Ops.push_back(N->getOperand(2));
2883 Ops.push_back(N->getOperand(3));
2884 Ops.push_back(N->getOperand(4));
2885 Ops.push_back(Chain);
2887 case NVPTXISD::Suld3DI8Trap:
2888 Opc = NVPTX::SULD_3D_I8_TRAP;
2889 Ops.push_back(TexHandle);
2890 Ops.push_back(N->getOperand(2));
2891 Ops.push_back(N->getOperand(3));
2892 Ops.push_back(N->getOperand(4));
2893 Ops.push_back(Chain);
2895 case NVPTXISD::Suld3DI16Trap:
2896 Opc = NVPTX::SULD_3D_I16_TRAP;
2897 Ops.push_back(TexHandle);
2898 Ops.push_back(N->getOperand(2));
2899 Ops.push_back(N->getOperand(3));
2900 Ops.push_back(N->getOperand(4));
2901 Ops.push_back(Chain);
2903 case NVPTXISD::Suld3DI32Trap:
2904 Opc = NVPTX::SULD_3D_I32_TRAP;
2905 Ops.push_back(TexHandle);
2906 Ops.push_back(N->getOperand(2));
2907 Ops.push_back(N->getOperand(3));
2908 Ops.push_back(N->getOperand(4));
2909 Ops.push_back(Chain);
2911 case NVPTXISD::Suld3DV2I8Trap:
2912 Opc = NVPTX::SULD_3D_V2I8_TRAP;
2913 Ops.push_back(TexHandle);
2914 Ops.push_back(N->getOperand(2));
2915 Ops.push_back(N->getOperand(3));
2916 Ops.push_back(N->getOperand(4));
2917 Ops.push_back(Chain);
2919 case NVPTXISD::Suld3DV2I16Trap:
2920 Opc = NVPTX::SULD_3D_V2I16_TRAP;
2921 Ops.push_back(TexHandle);
2922 Ops.push_back(N->getOperand(2));
2923 Ops.push_back(N->getOperand(3));
2924 Ops.push_back(N->getOperand(4));
2925 Ops.push_back(Chain);
2927 case NVPTXISD::Suld3DV2I32Trap:
2928 Opc = NVPTX::SULD_3D_V2I32_TRAP;
2929 Ops.push_back(TexHandle);
2930 Ops.push_back(N->getOperand(2));
2931 Ops.push_back(N->getOperand(3));
2932 Ops.push_back(N->getOperand(4));
2933 Ops.push_back(Chain);
2935 case NVPTXISD::Suld3DV4I8Trap:
2936 Opc = NVPTX::SULD_3D_V4I8_TRAP;
2937 Ops.push_back(TexHandle);
2938 Ops.push_back(N->getOperand(2));
2939 Ops.push_back(N->getOperand(3));
2940 Ops.push_back(N->getOperand(4));
2941 Ops.push_back(Chain);
2943 case NVPTXISD::Suld3DV4I16Trap:
2944 Opc = NVPTX::SULD_3D_V4I16_TRAP;
2945 Ops.push_back(TexHandle);
2946 Ops.push_back(N->getOperand(2));
2947 Ops.push_back(N->getOperand(3));
2948 Ops.push_back(N->getOperand(4));
2949 Ops.push_back(Chain);
2951 case NVPTXISD::Suld3DV4I32Trap:
2952 Opc = NVPTX::SULD_3D_V4I32_TRAP;
2953 Ops.push_back(TexHandle);
2954 Ops.push_back(N->getOperand(2));
2955 Ops.push_back(N->getOperand(3));
2956 Ops.push_back(N->getOperand(4));
2957 Ops.push_back(Chain);
2960 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
2964 // SelectDirectAddr - Match a direct address for DAG.
2965 // A direct address could be a globaladdress or externalsymbol.
2966 bool NVPTXDAGToDAGISel::SelectDirectAddr(SDValue N, SDValue &Address) {
2967 // Return true if TGA or ES.
2968 if (N.getOpcode() == ISD::TargetGlobalAddress ||
2969 N.getOpcode() == ISD::TargetExternalSymbol) {
2973 if (N.getOpcode() == NVPTXISD::Wrapper) {
2974 Address = N.getOperand(0);
2977 if (N.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
2978 unsigned IID = cast<ConstantSDNode>(N.getOperand(0))->getZExtValue();
2979 if (IID == Intrinsic::nvvm_ptr_gen_to_param)
2980 if (N.getOperand(1).getOpcode() == NVPTXISD::MoveParam)
2981 return (SelectDirectAddr(N.getOperand(1).getOperand(0), Address));
2987 bool NVPTXDAGToDAGISel::SelectADDRsi_imp(
2988 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
2989 if (Addr.getOpcode() == ISD::ADD) {
2990 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
2991 SDValue base = Addr.getOperand(0);
2992 if (SelectDirectAddr(base, Base)) {
2993 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
3002 bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr,
3003 SDValue &Base, SDValue &Offset) {
3004 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32);
3008 bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr,
3009 SDValue &Base, SDValue &Offset) {
3010 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64);
3014 bool NVPTXDAGToDAGISel::SelectADDRri_imp(
3015 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
3016 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
3017 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
3018 Offset = CurDAG->getTargetConstant(0, mvt);
3021 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
3022 Addr.getOpcode() == ISD::TargetGlobalAddress)
3023 return false; // direct calls.
3025 if (Addr.getOpcode() == ISD::ADD) {
3026 if (SelectDirectAddr(Addr.getOperand(0), Addr)) {
3029 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
3030 if (FrameIndexSDNode *FIN =
3031 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
3032 // Constant offset from frame ref.
3033 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
3035 Base = Addr.getOperand(0);
3036 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
3044 bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr,
3045 SDValue &Base, SDValue &Offset) {
3046 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32);
3050 bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr,
3051 SDValue &Base, SDValue &Offset) {
3052 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64);
3055 bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
3056 unsigned int spN) const {
3057 const Value *Src = NULL;
3058 // Even though MemIntrinsicSDNode is a subclas of MemSDNode,
3059 // the classof() for MemSDNode does not include MemIntrinsicSDNode
3060 // (See SelectionDAGNodes.h). So we need to check for both.
3061 if (MemSDNode *mN = dyn_cast<MemSDNode>(N)) {
3062 if (spN == 0 && mN->getMemOperand()->getPseudoValue())
3064 Src = mN->getMemOperand()->getValue();
3065 } else if (MemSDNode *mN = dyn_cast<MemIntrinsicSDNode>(N)) {
3066 if (spN == 0 && mN->getMemOperand()->getPseudoValue())
3068 Src = mN->getMemOperand()->getValue();
3072 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
3073 return (PT->getAddressSpace() == spN);
3077 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
3078 /// inline asm expressions.
3079 bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
3080 const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
3082 switch (ConstraintCode) {
3086 if (SelectDirectAddr(Op, Op0)) {
3087 OutOps.push_back(Op0);
3088 OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
3091 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
3092 OutOps.push_back(Op0);
3093 OutOps.push_back(Op1);