1 //===-- NVPTXISelDAGToDAG.cpp - A dag to dag inst selector for NVPTX ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXISelDAGToDAG.h"
15 #include "llvm/IR/GlobalValue.h"
16 #include "llvm/IR/Instructions.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Target/TargetIntrinsicInfo.h"
24 #define DEBUG_TYPE "nvptx-isel"
29 FMAContractLevel("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
30 cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
31 " 1: do it 2: do it aggressively"),
34 static cl::opt<int> UsePrecDivF32(
35 "nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden,
36 cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
37 " IEEE Compliant F32 div.rnd if avaiable."),
41 UsePrecSqrtF32("nvptx-prec-sqrtf32", cl::Hidden,
42 cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
46 FtzEnabled("nvptx-f32ftz", cl::ZeroOrMore, cl::Hidden,
47 cl::desc("NVPTX Specific: Flush f32 subnormals to sign-preserving zero."),
51 /// createNVPTXISelDag - This pass converts a legalized DAG into a
52 /// NVPTX-specific DAG, ready for instruction scheduling.
53 FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
54 llvm::CodeGenOpt::Level OptLevel) {
55 return new NVPTXDAGToDAGISel(TM, OptLevel);
58 NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
59 CodeGenOpt::Level OptLevel)
60 : SelectionDAGISel(tm, OptLevel),
61 Subtarget(tm.getSubtarget<NVPTXSubtarget>()) {
63 doFMAF32 = (OptLevel > 0) && Subtarget.hasFMAF32() && (FMAContractLevel >= 1);
64 doFMAF64 = (OptLevel > 0) && Subtarget.hasFMAF64() && (FMAContractLevel >= 1);
66 (OptLevel > 0) && Subtarget.hasFMAF32() && (FMAContractLevel == 2);
68 (OptLevel > 0) && Subtarget.hasFMAF64() && (FMAContractLevel == 2);
70 allowFMA = (FMAContractLevel >= 1);
72 doMulWide = (OptLevel > 0);
75 int NVPTXDAGToDAGISel::getDivF32Level() const {
76 if (UsePrecDivF32.getNumOccurrences() > 0) {
77 // If nvptx-prec-div32=N is used on the command-line, always honor it
80 // Otherwise, use div.approx if fast math is enabled
81 if (TM.Options.UnsafeFPMath)
88 bool NVPTXDAGToDAGISel::usePrecSqrtF32() const {
89 if (UsePrecSqrtF32.getNumOccurrences() > 0) {
90 // If nvptx-prec-sqrtf32 is used on the command-line, always honor it
91 return UsePrecSqrtF32;
93 // Otherwise, use sqrt.approx if fast math is enabled
94 if (TM.Options.UnsafeFPMath)
101 bool NVPTXDAGToDAGISel::useF32FTZ() const {
102 if (FtzEnabled.getNumOccurrences() > 0) {
103 // If nvptx-f32ftz is used on the command-line, always honor it
106 const Function *F = MF->getFunction();
107 // Otherwise, check for an nvptx-f32ftz attribute on the function
108 if (F->hasFnAttribute("nvptx-f32ftz"))
109 return (F->getAttributes().getAttribute(AttributeSet::FunctionIndex,
111 .getValueAsString() == "true");
117 /// Select - Select instructions not customized! Used for
118 /// expanded, promoted and normal instructions.
119 SDNode *NVPTXDAGToDAGISel::Select(SDNode *N) {
121 if (N->isMachineOpcode()) {
123 return NULL; // Already selected.
126 SDNode *ResNode = NULL;
127 switch (N->getOpcode()) {
129 ResNode = SelectLoad(N);
132 ResNode = SelectStore(N);
134 case NVPTXISD::LoadV2:
135 case NVPTXISD::LoadV4:
136 ResNode = SelectLoadVector(N);
138 case NVPTXISD::LDGV2:
139 case NVPTXISD::LDGV4:
140 case NVPTXISD::LDUV2:
141 case NVPTXISD::LDUV4:
142 ResNode = SelectLDGLDUVector(N);
144 case NVPTXISD::StoreV2:
145 case NVPTXISD::StoreV4:
146 ResNode = SelectStoreVector(N);
148 case NVPTXISD::LoadParam:
149 case NVPTXISD::LoadParamV2:
150 case NVPTXISD::LoadParamV4:
151 ResNode = SelectLoadParam(N);
153 case NVPTXISD::StoreRetval:
154 case NVPTXISD::StoreRetvalV2:
155 case NVPTXISD::StoreRetvalV4:
156 ResNode = SelectStoreRetval(N);
158 case NVPTXISD::StoreParam:
159 case NVPTXISD::StoreParamV2:
160 case NVPTXISD::StoreParamV4:
161 case NVPTXISD::StoreParamS32:
162 case NVPTXISD::StoreParamU32:
163 ResNode = SelectStoreParam(N);
165 case ISD::INTRINSIC_WO_CHAIN:
166 ResNode = SelectIntrinsicNoChain(N);
168 case NVPTXISD::Tex1DFloatI32:
169 case NVPTXISD::Tex1DFloatFloat:
170 case NVPTXISD::Tex1DFloatFloatLevel:
171 case NVPTXISD::Tex1DFloatFloatGrad:
172 case NVPTXISD::Tex1DI32I32:
173 case NVPTXISD::Tex1DI32Float:
174 case NVPTXISD::Tex1DI32FloatLevel:
175 case NVPTXISD::Tex1DI32FloatGrad:
176 case NVPTXISD::Tex1DArrayFloatI32:
177 case NVPTXISD::Tex1DArrayFloatFloat:
178 case NVPTXISD::Tex1DArrayFloatFloatLevel:
179 case NVPTXISD::Tex1DArrayFloatFloatGrad:
180 case NVPTXISD::Tex1DArrayI32I32:
181 case NVPTXISD::Tex1DArrayI32Float:
182 case NVPTXISD::Tex1DArrayI32FloatLevel:
183 case NVPTXISD::Tex1DArrayI32FloatGrad:
184 case NVPTXISD::Tex2DFloatI32:
185 case NVPTXISD::Tex2DFloatFloat:
186 case NVPTXISD::Tex2DFloatFloatLevel:
187 case NVPTXISD::Tex2DFloatFloatGrad:
188 case NVPTXISD::Tex2DI32I32:
189 case NVPTXISD::Tex2DI32Float:
190 case NVPTXISD::Tex2DI32FloatLevel:
191 case NVPTXISD::Tex2DI32FloatGrad:
192 case NVPTXISD::Tex2DArrayFloatI32:
193 case NVPTXISD::Tex2DArrayFloatFloat:
194 case NVPTXISD::Tex2DArrayFloatFloatLevel:
195 case NVPTXISD::Tex2DArrayFloatFloatGrad:
196 case NVPTXISD::Tex2DArrayI32I32:
197 case NVPTXISD::Tex2DArrayI32Float:
198 case NVPTXISD::Tex2DArrayI32FloatLevel:
199 case NVPTXISD::Tex2DArrayI32FloatGrad:
200 case NVPTXISD::Tex3DFloatI32:
201 case NVPTXISD::Tex3DFloatFloat:
202 case NVPTXISD::Tex3DFloatFloatLevel:
203 case NVPTXISD::Tex3DFloatFloatGrad:
204 case NVPTXISD::Tex3DI32I32:
205 case NVPTXISD::Tex3DI32Float:
206 case NVPTXISD::Tex3DI32FloatLevel:
207 case NVPTXISD::Tex3DI32FloatGrad:
208 ResNode = SelectTextureIntrinsic(N);
210 case NVPTXISD::Suld1DI8Trap:
211 case NVPTXISD::Suld1DI16Trap:
212 case NVPTXISD::Suld1DI32Trap:
213 case NVPTXISD::Suld1DV2I8Trap:
214 case NVPTXISD::Suld1DV2I16Trap:
215 case NVPTXISD::Suld1DV2I32Trap:
216 case NVPTXISD::Suld1DV4I8Trap:
217 case NVPTXISD::Suld1DV4I16Trap:
218 case NVPTXISD::Suld1DV4I32Trap:
219 case NVPTXISD::Suld1DArrayI8Trap:
220 case NVPTXISD::Suld1DArrayI16Trap:
221 case NVPTXISD::Suld1DArrayI32Trap:
222 case NVPTXISD::Suld1DArrayV2I8Trap:
223 case NVPTXISD::Suld1DArrayV2I16Trap:
224 case NVPTXISD::Suld1DArrayV2I32Trap:
225 case NVPTXISD::Suld1DArrayV4I8Trap:
226 case NVPTXISD::Suld1DArrayV4I16Trap:
227 case NVPTXISD::Suld1DArrayV4I32Trap:
228 case NVPTXISD::Suld2DI8Trap:
229 case NVPTXISD::Suld2DI16Trap:
230 case NVPTXISD::Suld2DI32Trap:
231 case NVPTXISD::Suld2DV2I8Trap:
232 case NVPTXISD::Suld2DV2I16Trap:
233 case NVPTXISD::Suld2DV2I32Trap:
234 case NVPTXISD::Suld2DV4I8Trap:
235 case NVPTXISD::Suld2DV4I16Trap:
236 case NVPTXISD::Suld2DV4I32Trap:
237 case NVPTXISD::Suld2DArrayI8Trap:
238 case NVPTXISD::Suld2DArrayI16Trap:
239 case NVPTXISD::Suld2DArrayI32Trap:
240 case NVPTXISD::Suld2DArrayV2I8Trap:
241 case NVPTXISD::Suld2DArrayV2I16Trap:
242 case NVPTXISD::Suld2DArrayV2I32Trap:
243 case NVPTXISD::Suld2DArrayV4I8Trap:
244 case NVPTXISD::Suld2DArrayV4I16Trap:
245 case NVPTXISD::Suld2DArrayV4I32Trap:
246 case NVPTXISD::Suld3DI8Trap:
247 case NVPTXISD::Suld3DI16Trap:
248 case NVPTXISD::Suld3DI32Trap:
249 case NVPTXISD::Suld3DV2I8Trap:
250 case NVPTXISD::Suld3DV2I16Trap:
251 case NVPTXISD::Suld3DV2I32Trap:
252 case NVPTXISD::Suld3DV4I8Trap:
253 case NVPTXISD::Suld3DV4I16Trap:
254 case NVPTXISD::Suld3DV4I32Trap:
255 ResNode = SelectSurfaceIntrinsic(N);
257 case ISD::ADDRSPACECAST:
258 ResNode = SelectAddrSpaceCast(N);
265 return SelectCode(N);
268 static unsigned int getCodeAddrSpace(MemSDNode *N,
269 const NVPTXSubtarget &Subtarget) {
270 const Value *Src = N->getSrcValue();
273 return NVPTX::PTXLdStInstCode::GENERIC;
275 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) {
276 switch (PT->getAddressSpace()) {
277 case llvm::ADDRESS_SPACE_LOCAL: return NVPTX::PTXLdStInstCode::LOCAL;
278 case llvm::ADDRESS_SPACE_GLOBAL: return NVPTX::PTXLdStInstCode::GLOBAL;
279 case llvm::ADDRESS_SPACE_SHARED: return NVPTX::PTXLdStInstCode::SHARED;
280 case llvm::ADDRESS_SPACE_GENERIC: return NVPTX::PTXLdStInstCode::GENERIC;
281 case llvm::ADDRESS_SPACE_PARAM: return NVPTX::PTXLdStInstCode::PARAM;
282 case llvm::ADDRESS_SPACE_CONST: return NVPTX::PTXLdStInstCode::CONSTANT;
286 return NVPTX::PTXLdStInstCode::GENERIC;
289 SDNode *NVPTXDAGToDAGISel::SelectIntrinsicNoChain(SDNode *N) {
290 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
294 case Intrinsic::nvvm_texsurf_handle_internal:
295 return SelectTexSurfHandle(N);
299 SDNode *NVPTXDAGToDAGISel::SelectTexSurfHandle(SDNode *N) {
300 // Op 0 is the intrinsic ID
301 SDValue Wrapper = N->getOperand(1);
302 SDValue GlobalVal = Wrapper.getOperand(0);
303 return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64,
307 SDNode *NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
308 SDValue Src = N->getOperand(0);
309 AddrSpaceCastSDNode *CastN = cast<AddrSpaceCastSDNode>(N);
310 unsigned SrcAddrSpace = CastN->getSrcAddressSpace();
311 unsigned DstAddrSpace = CastN->getDestAddressSpace();
313 assert(SrcAddrSpace != DstAddrSpace &&
314 "addrspacecast must be between different address spaces");
316 if (DstAddrSpace == ADDRESS_SPACE_GENERIC) {
317 // Specific to generic
319 switch (SrcAddrSpace) {
320 default: report_fatal_error("Bad address space in addrspacecast");
321 case ADDRESS_SPACE_GLOBAL:
322 Opc = Subtarget.is64Bit() ? NVPTX::cvta_global_yes_64
323 : NVPTX::cvta_global_yes;
325 case ADDRESS_SPACE_SHARED:
326 Opc = Subtarget.is64Bit() ? NVPTX::cvta_shared_yes_64
327 : NVPTX::cvta_shared_yes;
329 case ADDRESS_SPACE_CONST:
330 Opc = Subtarget.is64Bit() ? NVPTX::cvta_const_yes_64
331 : NVPTX::cvta_const_yes;
333 case ADDRESS_SPACE_LOCAL:
334 Opc = Subtarget.is64Bit() ? NVPTX::cvta_local_yes_64
335 : NVPTX::cvta_local_yes;
338 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
340 // Generic to specific
341 if (SrcAddrSpace != 0)
342 report_fatal_error("Cannot cast between two non-generic address spaces");
344 switch (DstAddrSpace) {
345 default: report_fatal_error("Bad address space in addrspacecast");
346 case ADDRESS_SPACE_GLOBAL:
347 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_global_yes_64
348 : NVPTX::cvta_to_global_yes;
350 case ADDRESS_SPACE_SHARED:
351 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_shared_yes_64
352 : NVPTX::cvta_to_shared_yes;
354 case ADDRESS_SPACE_CONST:
355 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_const_yes_64
356 : NVPTX::cvta_to_const_yes;
358 case ADDRESS_SPACE_LOCAL:
359 Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_local_yes_64
360 : NVPTX::cvta_to_local_yes;
363 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
367 SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
369 LoadSDNode *LD = cast<LoadSDNode>(N);
370 EVT LoadedVT = LD->getMemoryVT();
371 SDNode *NVPTXLD = NULL;
373 // do not support pre/post inc/dec
377 if (!LoadedVT.isSimple())
380 // Address Space Setting
381 unsigned int codeAddrSpace = getCodeAddrSpace(LD, Subtarget);
384 // - .volatile is only availalble for .global and .shared
385 bool isVolatile = LD->isVolatile();
386 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
387 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
388 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
392 MVT SimpleVT = LoadedVT.getSimpleVT();
393 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
394 if (SimpleVT.isVector()) {
395 unsigned num = SimpleVT.getVectorNumElements();
397 vecType = NVPTX::PTXLdStInstCode::V2;
399 vecType = NVPTX::PTXLdStInstCode::V4;
404 // Type Setting: fromType + fromTypeWidth
406 // Sign : ISD::SEXTLOAD
407 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
409 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
410 MVT ScalarVT = SimpleVT.getScalarType();
411 // Read at least 8 bits (predicates are stored as 8-bit values)
412 unsigned fromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
413 unsigned int fromType;
414 if ((LD->getExtensionType() == ISD::SEXTLOAD))
415 fromType = NVPTX::PTXLdStInstCode::Signed;
416 else if (ScalarVT.isFloatingPoint())
417 fromType = NVPTX::PTXLdStInstCode::Float;
419 fromType = NVPTX::PTXLdStInstCode::Unsigned;
421 // Create the machine instruction DAG
422 SDValue Chain = N->getOperand(0);
423 SDValue N1 = N->getOperand(1);
425 SDValue Offset, Base;
427 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
429 if (SelectDirectAddr(N1, Addr)) {
432 Opcode = NVPTX::LD_i8_avar;
435 Opcode = NVPTX::LD_i16_avar;
438 Opcode = NVPTX::LD_i32_avar;
441 Opcode = NVPTX::LD_i64_avar;
444 Opcode = NVPTX::LD_f32_avar;
447 Opcode = NVPTX::LD_f64_avar;
452 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
453 getI32Imm(vecType), getI32Imm(fromType),
454 getI32Imm(fromTypeWidth), Addr, Chain };
455 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
456 } else if (Subtarget.is64Bit()
457 ? SelectADDRsi64(N1.getNode(), N1, Base, Offset)
458 : SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
461 Opcode = NVPTX::LD_i8_asi;
464 Opcode = NVPTX::LD_i16_asi;
467 Opcode = NVPTX::LD_i32_asi;
470 Opcode = NVPTX::LD_i64_asi;
473 Opcode = NVPTX::LD_f32_asi;
476 Opcode = NVPTX::LD_f64_asi;
481 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
482 getI32Imm(vecType), getI32Imm(fromType),
483 getI32Imm(fromTypeWidth), Base, Offset, Chain };
484 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
485 } else if (Subtarget.is64Bit()
486 ? SelectADDRri64(N1.getNode(), N1, Base, Offset)
487 : SelectADDRri(N1.getNode(), N1, Base, Offset)) {
488 if (Subtarget.is64Bit()) {
491 Opcode = NVPTX::LD_i8_ari_64;
494 Opcode = NVPTX::LD_i16_ari_64;
497 Opcode = NVPTX::LD_i32_ari_64;
500 Opcode = NVPTX::LD_i64_ari_64;
503 Opcode = NVPTX::LD_f32_ari_64;
506 Opcode = NVPTX::LD_f64_ari_64;
514 Opcode = NVPTX::LD_i8_ari;
517 Opcode = NVPTX::LD_i16_ari;
520 Opcode = NVPTX::LD_i32_ari;
523 Opcode = NVPTX::LD_i64_ari;
526 Opcode = NVPTX::LD_f32_ari;
529 Opcode = NVPTX::LD_f64_ari;
535 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
536 getI32Imm(vecType), getI32Imm(fromType),
537 getI32Imm(fromTypeWidth), Base, Offset, Chain };
538 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
540 if (Subtarget.is64Bit()) {
543 Opcode = NVPTX::LD_i8_areg_64;
546 Opcode = NVPTX::LD_i16_areg_64;
549 Opcode = NVPTX::LD_i32_areg_64;
552 Opcode = NVPTX::LD_i64_areg_64;
555 Opcode = NVPTX::LD_f32_areg_64;
558 Opcode = NVPTX::LD_f64_areg_64;
566 Opcode = NVPTX::LD_i8_areg;
569 Opcode = NVPTX::LD_i16_areg;
572 Opcode = NVPTX::LD_i32_areg;
575 Opcode = NVPTX::LD_i64_areg;
578 Opcode = NVPTX::LD_f32_areg;
581 Opcode = NVPTX::LD_f64_areg;
587 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
588 getI32Imm(vecType), getI32Imm(fromType),
589 getI32Imm(fromTypeWidth), N1, Chain };
590 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
593 if (NVPTXLD != NULL) {
594 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
595 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
596 cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
602 SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
604 SDValue Chain = N->getOperand(0);
605 SDValue Op1 = N->getOperand(1);
606 SDValue Addr, Offset, Base;
610 MemSDNode *MemSD = cast<MemSDNode>(N);
611 EVT LoadedVT = MemSD->getMemoryVT();
613 if (!LoadedVT.isSimple())
616 // Address Space Setting
617 unsigned int CodeAddrSpace = getCodeAddrSpace(MemSD, Subtarget);
620 // - .volatile is only availalble for .global and .shared
621 bool IsVolatile = MemSD->isVolatile();
622 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
623 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
624 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
628 MVT SimpleVT = LoadedVT.getSimpleVT();
630 // Type Setting: fromType + fromTypeWidth
632 // Sign : ISD::SEXTLOAD
633 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
635 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
636 MVT ScalarVT = SimpleVT.getScalarType();
637 // Read at least 8 bits (predicates are stored as 8-bit values)
638 unsigned FromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
639 unsigned int FromType;
640 // The last operand holds the original LoadSDNode::getExtensionType() value
641 unsigned ExtensionType = cast<ConstantSDNode>(
642 N->getOperand(N->getNumOperands() - 1))->getZExtValue();
643 if (ExtensionType == ISD::SEXTLOAD)
644 FromType = NVPTX::PTXLdStInstCode::Signed;
645 else if (ScalarVT.isFloatingPoint())
646 FromType = NVPTX::PTXLdStInstCode::Float;
648 FromType = NVPTX::PTXLdStInstCode::Unsigned;
652 switch (N->getOpcode()) {
653 case NVPTXISD::LoadV2:
654 VecType = NVPTX::PTXLdStInstCode::V2;
656 case NVPTXISD::LoadV4:
657 VecType = NVPTX::PTXLdStInstCode::V4;
663 EVT EltVT = N->getValueType(0);
665 if (SelectDirectAddr(Op1, Addr)) {
666 switch (N->getOpcode()) {
669 case NVPTXISD::LoadV2:
670 switch (EltVT.getSimpleVT().SimpleTy) {
674 Opcode = NVPTX::LDV_i8_v2_avar;
677 Opcode = NVPTX::LDV_i16_v2_avar;
680 Opcode = NVPTX::LDV_i32_v2_avar;
683 Opcode = NVPTX::LDV_i64_v2_avar;
686 Opcode = NVPTX::LDV_f32_v2_avar;
689 Opcode = NVPTX::LDV_f64_v2_avar;
693 case NVPTXISD::LoadV4:
694 switch (EltVT.getSimpleVT().SimpleTy) {
698 Opcode = NVPTX::LDV_i8_v4_avar;
701 Opcode = NVPTX::LDV_i16_v4_avar;
704 Opcode = NVPTX::LDV_i32_v4_avar;
707 Opcode = NVPTX::LDV_f32_v4_avar;
713 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
714 getI32Imm(VecType), getI32Imm(FromType),
715 getI32Imm(FromTypeWidth), Addr, Chain };
716 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
717 } else if (Subtarget.is64Bit()
718 ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset)
719 : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
720 switch (N->getOpcode()) {
723 case NVPTXISD::LoadV2:
724 switch (EltVT.getSimpleVT().SimpleTy) {
728 Opcode = NVPTX::LDV_i8_v2_asi;
731 Opcode = NVPTX::LDV_i16_v2_asi;
734 Opcode = NVPTX::LDV_i32_v2_asi;
737 Opcode = NVPTX::LDV_i64_v2_asi;
740 Opcode = NVPTX::LDV_f32_v2_asi;
743 Opcode = NVPTX::LDV_f64_v2_asi;
747 case NVPTXISD::LoadV4:
748 switch (EltVT.getSimpleVT().SimpleTy) {
752 Opcode = NVPTX::LDV_i8_v4_asi;
755 Opcode = NVPTX::LDV_i16_v4_asi;
758 Opcode = NVPTX::LDV_i32_v4_asi;
761 Opcode = NVPTX::LDV_f32_v4_asi;
767 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
768 getI32Imm(VecType), getI32Imm(FromType),
769 getI32Imm(FromTypeWidth), Base, Offset, Chain };
770 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
771 } else if (Subtarget.is64Bit()
772 ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
773 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
774 if (Subtarget.is64Bit()) {
775 switch (N->getOpcode()) {
778 case NVPTXISD::LoadV2:
779 switch (EltVT.getSimpleVT().SimpleTy) {
783 Opcode = NVPTX::LDV_i8_v2_ari_64;
786 Opcode = NVPTX::LDV_i16_v2_ari_64;
789 Opcode = NVPTX::LDV_i32_v2_ari_64;
792 Opcode = NVPTX::LDV_i64_v2_ari_64;
795 Opcode = NVPTX::LDV_f32_v2_ari_64;
798 Opcode = NVPTX::LDV_f64_v2_ari_64;
802 case NVPTXISD::LoadV4:
803 switch (EltVT.getSimpleVT().SimpleTy) {
807 Opcode = NVPTX::LDV_i8_v4_ari_64;
810 Opcode = NVPTX::LDV_i16_v4_ari_64;
813 Opcode = NVPTX::LDV_i32_v4_ari_64;
816 Opcode = NVPTX::LDV_f32_v4_ari_64;
822 switch (N->getOpcode()) {
825 case NVPTXISD::LoadV2:
826 switch (EltVT.getSimpleVT().SimpleTy) {
830 Opcode = NVPTX::LDV_i8_v2_ari;
833 Opcode = NVPTX::LDV_i16_v2_ari;
836 Opcode = NVPTX::LDV_i32_v2_ari;
839 Opcode = NVPTX::LDV_i64_v2_ari;
842 Opcode = NVPTX::LDV_f32_v2_ari;
845 Opcode = NVPTX::LDV_f64_v2_ari;
849 case NVPTXISD::LoadV4:
850 switch (EltVT.getSimpleVT().SimpleTy) {
854 Opcode = NVPTX::LDV_i8_v4_ari;
857 Opcode = NVPTX::LDV_i16_v4_ari;
860 Opcode = NVPTX::LDV_i32_v4_ari;
863 Opcode = NVPTX::LDV_f32_v4_ari;
870 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
871 getI32Imm(VecType), getI32Imm(FromType),
872 getI32Imm(FromTypeWidth), Base, Offset, Chain };
874 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
876 if (Subtarget.is64Bit()) {
877 switch (N->getOpcode()) {
880 case NVPTXISD::LoadV2:
881 switch (EltVT.getSimpleVT().SimpleTy) {
885 Opcode = NVPTX::LDV_i8_v2_areg_64;
888 Opcode = NVPTX::LDV_i16_v2_areg_64;
891 Opcode = NVPTX::LDV_i32_v2_areg_64;
894 Opcode = NVPTX::LDV_i64_v2_areg_64;
897 Opcode = NVPTX::LDV_f32_v2_areg_64;
900 Opcode = NVPTX::LDV_f64_v2_areg_64;
904 case NVPTXISD::LoadV4:
905 switch (EltVT.getSimpleVT().SimpleTy) {
909 Opcode = NVPTX::LDV_i8_v4_areg_64;
912 Opcode = NVPTX::LDV_i16_v4_areg_64;
915 Opcode = NVPTX::LDV_i32_v4_areg_64;
918 Opcode = NVPTX::LDV_f32_v4_areg_64;
924 switch (N->getOpcode()) {
927 case NVPTXISD::LoadV2:
928 switch (EltVT.getSimpleVT().SimpleTy) {
932 Opcode = NVPTX::LDV_i8_v2_areg;
935 Opcode = NVPTX::LDV_i16_v2_areg;
938 Opcode = NVPTX::LDV_i32_v2_areg;
941 Opcode = NVPTX::LDV_i64_v2_areg;
944 Opcode = NVPTX::LDV_f32_v2_areg;
947 Opcode = NVPTX::LDV_f64_v2_areg;
951 case NVPTXISD::LoadV4:
952 switch (EltVT.getSimpleVT().SimpleTy) {
956 Opcode = NVPTX::LDV_i8_v4_areg;
959 Opcode = NVPTX::LDV_i16_v4_areg;
962 Opcode = NVPTX::LDV_i32_v4_areg;
965 Opcode = NVPTX::LDV_f32_v4_areg;
972 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
973 getI32Imm(VecType), getI32Imm(FromType),
974 getI32Imm(FromTypeWidth), Op1, Chain };
975 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
978 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
979 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
980 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
985 SDNode *NVPTXDAGToDAGISel::SelectLDGLDUVector(SDNode *N) {
987 SDValue Chain = N->getOperand(0);
988 SDValue Op1 = N->getOperand(1);
992 MemSDNode *Mem = cast<MemSDNode>(N);
993 SDValue Base, Offset, Addr;
995 EVT EltVT = Mem->getMemoryVT().getVectorElementType();
997 if (SelectDirectAddr(Op1, Addr)) {
998 switch (N->getOpcode()) {
1001 case NVPTXISD::LDGV2:
1002 switch (EltVT.getSimpleVT().SimpleTy) {
1006 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_avar;
1009 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_avar;
1012 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_avar;
1015 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_avar;
1018 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_avar;
1021 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_avar;
1025 case NVPTXISD::LDUV2:
1026 switch (EltVT.getSimpleVT().SimpleTy) {
1030 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_avar;
1033 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_avar;
1036 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_avar;
1039 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_avar;
1042 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_avar;
1045 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_avar;
1049 case NVPTXISD::LDGV4:
1050 switch (EltVT.getSimpleVT().SimpleTy) {
1054 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_avar;
1057 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_avar;
1060 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_avar;
1063 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_avar;
1067 case NVPTXISD::LDUV4:
1068 switch (EltVT.getSimpleVT().SimpleTy) {
1072 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_avar;
1075 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_avar;
1078 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_avar;
1081 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_avar;
1087 SDValue Ops[] = { Addr, Chain };
1088 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
1089 ArrayRef<SDValue>(Ops, 2));
1090 } else if (Subtarget.is64Bit()
1091 ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1092 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1093 if (Subtarget.is64Bit()) {
1094 switch (N->getOpcode()) {
1097 case NVPTXISD::LDGV2:
1098 switch (EltVT.getSimpleVT().SimpleTy) {
1102 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari64;
1105 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari64;
1108 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari64;
1111 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari64;
1114 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari64;
1117 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari64;
1121 case NVPTXISD::LDUV2:
1122 switch (EltVT.getSimpleVT().SimpleTy) {
1126 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari64;
1129 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari64;
1132 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari64;
1135 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari64;
1138 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari64;
1141 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari64;
1145 case NVPTXISD::LDGV4:
1146 switch (EltVT.getSimpleVT().SimpleTy) {
1150 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari64;
1153 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari64;
1156 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari64;
1159 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari64;
1163 case NVPTXISD::LDUV4:
1164 switch (EltVT.getSimpleVT().SimpleTy) {
1168 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari64;
1171 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari64;
1174 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari64;
1177 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari64;
1183 switch (N->getOpcode()) {
1186 case NVPTXISD::LDGV2:
1187 switch (EltVT.getSimpleVT().SimpleTy) {
1191 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari32;
1194 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari32;
1197 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari32;
1200 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari32;
1203 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari32;
1206 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari32;
1210 case NVPTXISD::LDUV2:
1211 switch (EltVT.getSimpleVT().SimpleTy) {
1215 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari32;
1218 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari32;
1221 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari32;
1224 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari32;
1227 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari32;
1230 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari32;
1234 case NVPTXISD::LDGV4:
1235 switch (EltVT.getSimpleVT().SimpleTy) {
1239 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari32;
1242 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari32;
1245 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari32;
1248 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari32;
1252 case NVPTXISD::LDUV4:
1253 switch (EltVT.getSimpleVT().SimpleTy) {
1257 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari32;
1260 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari32;
1263 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari32;
1266 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari32;
1273 SDValue Ops[] = { Base, Offset, Chain };
1275 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
1276 ArrayRef<SDValue>(Ops, 3));
1278 if (Subtarget.is64Bit()) {
1279 switch (N->getOpcode()) {
1282 case NVPTXISD::LDGV2:
1283 switch (EltVT.getSimpleVT().SimpleTy) {
1287 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg64;
1290 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg64;
1293 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg64;
1296 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg64;
1299 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg64;
1302 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg64;
1306 case NVPTXISD::LDUV2:
1307 switch (EltVT.getSimpleVT().SimpleTy) {
1311 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg64;
1314 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg64;
1317 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg64;
1320 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg64;
1323 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg64;
1326 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg64;
1330 case NVPTXISD::LDGV4:
1331 switch (EltVT.getSimpleVT().SimpleTy) {
1335 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64;
1338 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg64;
1341 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg64;
1344 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg64;
1348 case NVPTXISD::LDUV4:
1349 switch (EltVT.getSimpleVT().SimpleTy) {
1353 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64;
1356 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg64;
1359 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg64;
1362 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg64;
1368 switch (N->getOpcode()) {
1371 case NVPTXISD::LDGV2:
1372 switch (EltVT.getSimpleVT().SimpleTy) {
1376 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg32;
1379 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg32;
1382 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg32;
1385 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg32;
1388 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg32;
1391 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg32;
1395 case NVPTXISD::LDUV2:
1396 switch (EltVT.getSimpleVT().SimpleTy) {
1400 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg32;
1403 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg32;
1406 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg32;
1409 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg32;
1412 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg32;
1415 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg32;
1419 case NVPTXISD::LDGV4:
1420 switch (EltVT.getSimpleVT().SimpleTy) {
1424 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32;
1427 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg32;
1430 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg32;
1433 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg32;
1437 case NVPTXISD::LDUV4:
1438 switch (EltVT.getSimpleVT().SimpleTy) {
1442 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32;
1445 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg32;
1448 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg32;
1451 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg32;
1458 SDValue Ops[] = { Op1, Chain };
1459 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
1460 ArrayRef<SDValue>(Ops, 2));
1463 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1464 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
1465 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1470 SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
1472 StoreSDNode *ST = cast<StoreSDNode>(N);
1473 EVT StoreVT = ST->getMemoryVT();
1474 SDNode *NVPTXST = NULL;
1476 // do not support pre/post inc/dec
1477 if (ST->isIndexed())
1480 if (!StoreVT.isSimple())
1483 // Address Space Setting
1484 unsigned int codeAddrSpace = getCodeAddrSpace(ST, Subtarget);
1487 // - .volatile is only availalble for .global and .shared
1488 bool isVolatile = ST->isVolatile();
1489 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
1490 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
1491 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
1495 MVT SimpleVT = StoreVT.getSimpleVT();
1496 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
1497 if (SimpleVT.isVector()) {
1498 unsigned num = SimpleVT.getVectorNumElements();
1500 vecType = NVPTX::PTXLdStInstCode::V2;
1502 vecType = NVPTX::PTXLdStInstCode::V4;
1507 // Type Setting: toType + toTypeWidth
1508 // - for integer type, always use 'u'
1510 MVT ScalarVT = SimpleVT.getScalarType();
1511 unsigned toTypeWidth = ScalarVT.getSizeInBits();
1512 unsigned int toType;
1513 if (ScalarVT.isFloatingPoint())
1514 toType = NVPTX::PTXLdStInstCode::Float;
1516 toType = NVPTX::PTXLdStInstCode::Unsigned;
1518 // Create the machine instruction DAG
1519 SDValue Chain = N->getOperand(0);
1520 SDValue N1 = N->getOperand(1);
1521 SDValue N2 = N->getOperand(2);
1523 SDValue Offset, Base;
1525 MVT::SimpleValueType SourceVT = N1.getNode()->getSimpleValueType(0).SimpleTy;
1527 if (SelectDirectAddr(N2, Addr)) {
1530 Opcode = NVPTX::ST_i8_avar;
1533 Opcode = NVPTX::ST_i16_avar;
1536 Opcode = NVPTX::ST_i32_avar;
1539 Opcode = NVPTX::ST_i64_avar;
1542 Opcode = NVPTX::ST_f32_avar;
1545 Opcode = NVPTX::ST_f64_avar;
1550 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
1551 getI32Imm(vecType), getI32Imm(toType),
1552 getI32Imm(toTypeWidth), Addr, Chain };
1553 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
1554 } else if (Subtarget.is64Bit()
1555 ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
1556 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
1559 Opcode = NVPTX::ST_i8_asi;
1562 Opcode = NVPTX::ST_i16_asi;
1565 Opcode = NVPTX::ST_i32_asi;
1568 Opcode = NVPTX::ST_i64_asi;
1571 Opcode = NVPTX::ST_f32_asi;
1574 Opcode = NVPTX::ST_f64_asi;
1579 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
1580 getI32Imm(vecType), getI32Imm(toType),
1581 getI32Imm(toTypeWidth), Base, Offset, Chain };
1582 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
1583 } else if (Subtarget.is64Bit()
1584 ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
1585 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
1586 if (Subtarget.is64Bit()) {
1589 Opcode = NVPTX::ST_i8_ari_64;
1592 Opcode = NVPTX::ST_i16_ari_64;
1595 Opcode = NVPTX::ST_i32_ari_64;
1598 Opcode = NVPTX::ST_i64_ari_64;
1601 Opcode = NVPTX::ST_f32_ari_64;
1604 Opcode = NVPTX::ST_f64_ari_64;
1612 Opcode = NVPTX::ST_i8_ari;
1615 Opcode = NVPTX::ST_i16_ari;
1618 Opcode = NVPTX::ST_i32_ari;
1621 Opcode = NVPTX::ST_i64_ari;
1624 Opcode = NVPTX::ST_f32_ari;
1627 Opcode = NVPTX::ST_f64_ari;
1633 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
1634 getI32Imm(vecType), getI32Imm(toType),
1635 getI32Imm(toTypeWidth), Base, Offset, Chain };
1636 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
1638 if (Subtarget.is64Bit()) {
1641 Opcode = NVPTX::ST_i8_areg_64;
1644 Opcode = NVPTX::ST_i16_areg_64;
1647 Opcode = NVPTX::ST_i32_areg_64;
1650 Opcode = NVPTX::ST_i64_areg_64;
1653 Opcode = NVPTX::ST_f32_areg_64;
1656 Opcode = NVPTX::ST_f64_areg_64;
1664 Opcode = NVPTX::ST_i8_areg;
1667 Opcode = NVPTX::ST_i16_areg;
1670 Opcode = NVPTX::ST_i32_areg;
1673 Opcode = NVPTX::ST_i64_areg;
1676 Opcode = NVPTX::ST_f32_areg;
1679 Opcode = NVPTX::ST_f64_areg;
1685 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
1686 getI32Imm(vecType), getI32Imm(toType),
1687 getI32Imm(toTypeWidth), N2, Chain };
1688 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
1691 if (NVPTXST != NULL) {
1692 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1693 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
1694 cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
1700 SDNode *NVPTXDAGToDAGISel::SelectStoreVector(SDNode *N) {
1701 SDValue Chain = N->getOperand(0);
1702 SDValue Op1 = N->getOperand(1);
1703 SDValue Addr, Offset, Base;
1707 EVT EltVT = Op1.getValueType();
1708 MemSDNode *MemSD = cast<MemSDNode>(N);
1709 EVT StoreVT = MemSD->getMemoryVT();
1711 // Address Space Setting
1712 unsigned CodeAddrSpace = getCodeAddrSpace(MemSD, Subtarget);
1714 if (CodeAddrSpace == NVPTX::PTXLdStInstCode::CONSTANT) {
1715 report_fatal_error("Cannot store to pointer that points to constant "
1720 // - .volatile is only availalble for .global and .shared
1721 bool IsVolatile = MemSD->isVolatile();
1722 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
1723 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
1724 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
1727 // Type Setting: toType + toTypeWidth
1728 // - for integer type, always use 'u'
1729 assert(StoreVT.isSimple() && "Store value is not simple");
1730 MVT ScalarVT = StoreVT.getSimpleVT().getScalarType();
1731 unsigned ToTypeWidth = ScalarVT.getSizeInBits();
1733 if (ScalarVT.isFloatingPoint())
1734 ToType = NVPTX::PTXLdStInstCode::Float;
1736 ToType = NVPTX::PTXLdStInstCode::Unsigned;
1738 SmallVector<SDValue, 12> StOps;
1742 switch (N->getOpcode()) {
1743 case NVPTXISD::StoreV2:
1744 VecType = NVPTX::PTXLdStInstCode::V2;
1745 StOps.push_back(N->getOperand(1));
1746 StOps.push_back(N->getOperand(2));
1747 N2 = N->getOperand(3);
1749 case NVPTXISD::StoreV4:
1750 VecType = NVPTX::PTXLdStInstCode::V4;
1751 StOps.push_back(N->getOperand(1));
1752 StOps.push_back(N->getOperand(2));
1753 StOps.push_back(N->getOperand(3));
1754 StOps.push_back(N->getOperand(4));
1755 N2 = N->getOperand(5);
1761 StOps.push_back(getI32Imm(IsVolatile));
1762 StOps.push_back(getI32Imm(CodeAddrSpace));
1763 StOps.push_back(getI32Imm(VecType));
1764 StOps.push_back(getI32Imm(ToType));
1765 StOps.push_back(getI32Imm(ToTypeWidth));
1767 if (SelectDirectAddr(N2, Addr)) {
1768 switch (N->getOpcode()) {
1771 case NVPTXISD::StoreV2:
1772 switch (EltVT.getSimpleVT().SimpleTy) {
1776 Opcode = NVPTX::STV_i8_v2_avar;
1779 Opcode = NVPTX::STV_i16_v2_avar;
1782 Opcode = NVPTX::STV_i32_v2_avar;
1785 Opcode = NVPTX::STV_i64_v2_avar;
1788 Opcode = NVPTX::STV_f32_v2_avar;
1791 Opcode = NVPTX::STV_f64_v2_avar;
1795 case NVPTXISD::StoreV4:
1796 switch (EltVT.getSimpleVT().SimpleTy) {
1800 Opcode = NVPTX::STV_i8_v4_avar;
1803 Opcode = NVPTX::STV_i16_v4_avar;
1806 Opcode = NVPTX::STV_i32_v4_avar;
1809 Opcode = NVPTX::STV_f32_v4_avar;
1814 StOps.push_back(Addr);
1815 } else if (Subtarget.is64Bit()
1816 ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
1817 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
1818 switch (N->getOpcode()) {
1821 case NVPTXISD::StoreV2:
1822 switch (EltVT.getSimpleVT().SimpleTy) {
1826 Opcode = NVPTX::STV_i8_v2_asi;
1829 Opcode = NVPTX::STV_i16_v2_asi;
1832 Opcode = NVPTX::STV_i32_v2_asi;
1835 Opcode = NVPTX::STV_i64_v2_asi;
1838 Opcode = NVPTX::STV_f32_v2_asi;
1841 Opcode = NVPTX::STV_f64_v2_asi;
1845 case NVPTXISD::StoreV4:
1846 switch (EltVT.getSimpleVT().SimpleTy) {
1850 Opcode = NVPTX::STV_i8_v4_asi;
1853 Opcode = NVPTX::STV_i16_v4_asi;
1856 Opcode = NVPTX::STV_i32_v4_asi;
1859 Opcode = NVPTX::STV_f32_v4_asi;
1864 StOps.push_back(Base);
1865 StOps.push_back(Offset);
1866 } else if (Subtarget.is64Bit()
1867 ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
1868 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
1869 if (Subtarget.is64Bit()) {
1870 switch (N->getOpcode()) {
1873 case NVPTXISD::StoreV2:
1874 switch (EltVT.getSimpleVT().SimpleTy) {
1878 Opcode = NVPTX::STV_i8_v2_ari_64;
1881 Opcode = NVPTX::STV_i16_v2_ari_64;
1884 Opcode = NVPTX::STV_i32_v2_ari_64;
1887 Opcode = NVPTX::STV_i64_v2_ari_64;
1890 Opcode = NVPTX::STV_f32_v2_ari_64;
1893 Opcode = NVPTX::STV_f64_v2_ari_64;
1897 case NVPTXISD::StoreV4:
1898 switch (EltVT.getSimpleVT().SimpleTy) {
1902 Opcode = NVPTX::STV_i8_v4_ari_64;
1905 Opcode = NVPTX::STV_i16_v4_ari_64;
1908 Opcode = NVPTX::STV_i32_v4_ari_64;
1911 Opcode = NVPTX::STV_f32_v4_ari_64;
1917 switch (N->getOpcode()) {
1920 case NVPTXISD::StoreV2:
1921 switch (EltVT.getSimpleVT().SimpleTy) {
1925 Opcode = NVPTX::STV_i8_v2_ari;
1928 Opcode = NVPTX::STV_i16_v2_ari;
1931 Opcode = NVPTX::STV_i32_v2_ari;
1934 Opcode = NVPTX::STV_i64_v2_ari;
1937 Opcode = NVPTX::STV_f32_v2_ari;
1940 Opcode = NVPTX::STV_f64_v2_ari;
1944 case NVPTXISD::StoreV4:
1945 switch (EltVT.getSimpleVT().SimpleTy) {
1949 Opcode = NVPTX::STV_i8_v4_ari;
1952 Opcode = NVPTX::STV_i16_v4_ari;
1955 Opcode = NVPTX::STV_i32_v4_ari;
1958 Opcode = NVPTX::STV_f32_v4_ari;
1964 StOps.push_back(Base);
1965 StOps.push_back(Offset);
1967 if (Subtarget.is64Bit()) {
1968 switch (N->getOpcode()) {
1971 case NVPTXISD::StoreV2:
1972 switch (EltVT.getSimpleVT().SimpleTy) {
1976 Opcode = NVPTX::STV_i8_v2_areg_64;
1979 Opcode = NVPTX::STV_i16_v2_areg_64;
1982 Opcode = NVPTX::STV_i32_v2_areg_64;
1985 Opcode = NVPTX::STV_i64_v2_areg_64;
1988 Opcode = NVPTX::STV_f32_v2_areg_64;
1991 Opcode = NVPTX::STV_f64_v2_areg_64;
1995 case NVPTXISD::StoreV4:
1996 switch (EltVT.getSimpleVT().SimpleTy) {
2000 Opcode = NVPTX::STV_i8_v4_areg_64;
2003 Opcode = NVPTX::STV_i16_v4_areg_64;
2006 Opcode = NVPTX::STV_i32_v4_areg_64;
2009 Opcode = NVPTX::STV_f32_v4_areg_64;
2015 switch (N->getOpcode()) {
2018 case NVPTXISD::StoreV2:
2019 switch (EltVT.getSimpleVT().SimpleTy) {
2023 Opcode = NVPTX::STV_i8_v2_areg;
2026 Opcode = NVPTX::STV_i16_v2_areg;
2029 Opcode = NVPTX::STV_i32_v2_areg;
2032 Opcode = NVPTX::STV_i64_v2_areg;
2035 Opcode = NVPTX::STV_f32_v2_areg;
2038 Opcode = NVPTX::STV_f64_v2_areg;
2042 case NVPTXISD::StoreV4:
2043 switch (EltVT.getSimpleVT().SimpleTy) {
2047 Opcode = NVPTX::STV_i8_v4_areg;
2050 Opcode = NVPTX::STV_i16_v4_areg;
2053 Opcode = NVPTX::STV_i32_v4_areg;
2056 Opcode = NVPTX::STV_f32_v4_areg;
2062 StOps.push_back(N2);
2065 StOps.push_back(Chain);
2067 ST = CurDAG->getMachineNode(Opcode, DL, MVT::Other, StOps);
2069 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2070 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2071 cast<MachineSDNode>(ST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2076 SDNode *NVPTXDAGToDAGISel::SelectLoadParam(SDNode *Node) {
2077 SDValue Chain = Node->getOperand(0);
2078 SDValue Offset = Node->getOperand(2);
2079 SDValue Flag = Node->getOperand(3);
2081 MemSDNode *Mem = cast<MemSDNode>(Node);
2084 switch (Node->getOpcode()) {
2087 case NVPTXISD::LoadParam:
2090 case NVPTXISD::LoadParamV2:
2093 case NVPTXISD::LoadParamV4:
2098 EVT EltVT = Node->getValueType(0);
2099 EVT MemVT = Mem->getMemoryVT();
2107 switch (MemVT.getSimpleVT().SimpleTy) {
2111 Opc = NVPTX::LoadParamMemI8;
2114 Opc = NVPTX::LoadParamMemI8;
2117 Opc = NVPTX::LoadParamMemI16;
2120 Opc = NVPTX::LoadParamMemI32;
2123 Opc = NVPTX::LoadParamMemI64;
2126 Opc = NVPTX::LoadParamMemF32;
2129 Opc = NVPTX::LoadParamMemF64;
2134 switch (MemVT.getSimpleVT().SimpleTy) {
2138 Opc = NVPTX::LoadParamMemV2I8;
2141 Opc = NVPTX::LoadParamMemV2I8;
2144 Opc = NVPTX::LoadParamMemV2I16;
2147 Opc = NVPTX::LoadParamMemV2I32;
2150 Opc = NVPTX::LoadParamMemV2I64;
2153 Opc = NVPTX::LoadParamMemV2F32;
2156 Opc = NVPTX::LoadParamMemV2F64;
2161 switch (MemVT.getSimpleVT().SimpleTy) {
2165 Opc = NVPTX::LoadParamMemV4I8;
2168 Opc = NVPTX::LoadParamMemV4I8;
2171 Opc = NVPTX::LoadParamMemV4I16;
2174 Opc = NVPTX::LoadParamMemV4I32;
2177 Opc = NVPTX::LoadParamMemV4F32;
2185 VTs = CurDAG->getVTList(EltVT, MVT::Other, MVT::Glue);
2186 } else if (VecSize == 2) {
2187 VTs = CurDAG->getVTList(EltVT, EltVT, MVT::Other, MVT::Glue);
2189 EVT EVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other, MVT::Glue };
2190 VTs = CurDAG->getVTList(&EVTs[0], array_lengthof(EVTs));
2193 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2195 SmallVector<SDValue, 2> Ops;
2196 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2197 Ops.push_back(Chain);
2198 Ops.push_back(Flag);
2201 CurDAG->getMachineNode(Opc, DL, VTs, Ops);
2205 SDNode *NVPTXDAGToDAGISel::SelectStoreRetval(SDNode *N) {
2207 SDValue Chain = N->getOperand(0);
2208 SDValue Offset = N->getOperand(1);
2209 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2210 MemSDNode *Mem = cast<MemSDNode>(N);
2212 // How many elements do we have?
2213 unsigned NumElts = 1;
2214 switch (N->getOpcode()) {
2217 case NVPTXISD::StoreRetval:
2220 case NVPTXISD::StoreRetvalV2:
2223 case NVPTXISD::StoreRetvalV4:
2228 // Build vector of operands
2229 SmallVector<SDValue, 6> Ops;
2230 for (unsigned i = 0; i < NumElts; ++i)
2231 Ops.push_back(N->getOperand(i + 2));
2232 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2233 Ops.push_back(Chain);
2235 // Determine target opcode
2236 // If we have an i1, use an 8-bit store. The lowering code in
2237 // NVPTXISelLowering will have already emitted an upcast.
2238 unsigned Opcode = 0;
2243 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2247 Opcode = NVPTX::StoreRetvalI8;
2250 Opcode = NVPTX::StoreRetvalI8;
2253 Opcode = NVPTX::StoreRetvalI16;
2256 Opcode = NVPTX::StoreRetvalI32;
2259 Opcode = NVPTX::StoreRetvalI64;
2262 Opcode = NVPTX::StoreRetvalF32;
2265 Opcode = NVPTX::StoreRetvalF64;
2270 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2274 Opcode = NVPTX::StoreRetvalV2I8;
2277 Opcode = NVPTX::StoreRetvalV2I8;
2280 Opcode = NVPTX::StoreRetvalV2I16;
2283 Opcode = NVPTX::StoreRetvalV2I32;
2286 Opcode = NVPTX::StoreRetvalV2I64;
2289 Opcode = NVPTX::StoreRetvalV2F32;
2292 Opcode = NVPTX::StoreRetvalV2F64;
2297 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2301 Opcode = NVPTX::StoreRetvalV4I8;
2304 Opcode = NVPTX::StoreRetvalV4I8;
2307 Opcode = NVPTX::StoreRetvalV4I16;
2310 Opcode = NVPTX::StoreRetvalV4I32;
2313 Opcode = NVPTX::StoreRetvalV4F32;
2320 CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
2321 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2322 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2323 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
2328 SDNode *NVPTXDAGToDAGISel::SelectStoreParam(SDNode *N) {
2330 SDValue Chain = N->getOperand(0);
2331 SDValue Param = N->getOperand(1);
2332 unsigned ParamVal = cast<ConstantSDNode>(Param)->getZExtValue();
2333 SDValue Offset = N->getOperand(2);
2334 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2335 MemSDNode *Mem = cast<MemSDNode>(N);
2336 SDValue Flag = N->getOperand(N->getNumOperands() - 1);
2338 // How many elements do we have?
2339 unsigned NumElts = 1;
2340 switch (N->getOpcode()) {
2343 case NVPTXISD::StoreParamU32:
2344 case NVPTXISD::StoreParamS32:
2345 case NVPTXISD::StoreParam:
2348 case NVPTXISD::StoreParamV2:
2351 case NVPTXISD::StoreParamV4:
2356 // Build vector of operands
2357 SmallVector<SDValue, 8> Ops;
2358 for (unsigned i = 0; i < NumElts; ++i)
2359 Ops.push_back(N->getOperand(i + 3));
2360 Ops.push_back(CurDAG->getTargetConstant(ParamVal, MVT::i32));
2361 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2362 Ops.push_back(Chain);
2363 Ops.push_back(Flag);
2365 // Determine target opcode
2366 // If we have an i1, use an 8-bit store. The lowering code in
2367 // NVPTXISelLowering will have already emitted an upcast.
2368 unsigned Opcode = 0;
2369 switch (N->getOpcode()) {
2375 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2379 Opcode = NVPTX::StoreParamI8;
2382 Opcode = NVPTX::StoreParamI8;
2385 Opcode = NVPTX::StoreParamI16;
2388 Opcode = NVPTX::StoreParamI32;
2391 Opcode = NVPTX::StoreParamI64;
2394 Opcode = NVPTX::StoreParamF32;
2397 Opcode = NVPTX::StoreParamF64;
2402 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2406 Opcode = NVPTX::StoreParamV2I8;
2409 Opcode = NVPTX::StoreParamV2I8;
2412 Opcode = NVPTX::StoreParamV2I16;
2415 Opcode = NVPTX::StoreParamV2I32;
2418 Opcode = NVPTX::StoreParamV2I64;
2421 Opcode = NVPTX::StoreParamV2F32;
2424 Opcode = NVPTX::StoreParamV2F64;
2429 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2433 Opcode = NVPTX::StoreParamV4I8;
2436 Opcode = NVPTX::StoreParamV4I8;
2439 Opcode = NVPTX::StoreParamV4I16;
2442 Opcode = NVPTX::StoreParamV4I32;
2445 Opcode = NVPTX::StoreParamV4F32;
2451 // Special case: if we have a sign-extend/zero-extend node, insert the
2452 // conversion instruction first, and use that as the value operand to
2453 // the selected StoreParam node.
2454 case NVPTXISD::StoreParamU32: {
2455 Opcode = NVPTX::StoreParamI32;
2456 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
2458 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL,
2459 MVT::i32, Ops[0], CvtNone);
2460 Ops[0] = SDValue(Cvt, 0);
2463 case NVPTXISD::StoreParamS32: {
2464 Opcode = NVPTX::StoreParamI32;
2465 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
2467 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL,
2468 MVT::i32, Ops[0], CvtNone);
2469 Ops[0] = SDValue(Cvt, 0);
2474 SDVTList RetVTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2476 CurDAG->getMachineNode(Opcode, DL, RetVTs, Ops);
2477 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2478 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2479 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
2484 SDNode *NVPTXDAGToDAGISel::SelectTextureIntrinsic(SDNode *N) {
2485 SDValue Chain = N->getOperand(0);
2486 SDValue TexRef = N->getOperand(1);
2487 SDValue SampRef = N->getOperand(2);
2490 SmallVector<SDValue, 8> Ops;
2492 switch (N->getOpcode()) {
2493 default: return NULL;
2494 case NVPTXISD::Tex1DFloatI32:
2495 Opc = NVPTX::TEX_1D_F32_I32;
2497 case NVPTXISD::Tex1DFloatFloat:
2498 Opc = NVPTX::TEX_1D_F32_F32;
2500 case NVPTXISD::Tex1DFloatFloatLevel:
2501 Opc = NVPTX::TEX_1D_F32_F32_LEVEL;
2503 case NVPTXISD::Tex1DFloatFloatGrad:
2504 Opc = NVPTX::TEX_1D_F32_F32_GRAD;
2506 case NVPTXISD::Tex1DI32I32:
2507 Opc = NVPTX::TEX_1D_I32_I32;
2509 case NVPTXISD::Tex1DI32Float:
2510 Opc = NVPTX::TEX_1D_I32_F32;
2512 case NVPTXISD::Tex1DI32FloatLevel:
2513 Opc = NVPTX::TEX_1D_I32_F32_LEVEL;
2515 case NVPTXISD::Tex1DI32FloatGrad:
2516 Opc = NVPTX::TEX_1D_I32_F32_GRAD;
2518 case NVPTXISD::Tex1DArrayFloatI32:
2519 Opc = NVPTX::TEX_1D_ARRAY_F32_I32;
2521 case NVPTXISD::Tex1DArrayFloatFloat:
2522 Opc = NVPTX::TEX_1D_ARRAY_F32_F32;
2524 case NVPTXISD::Tex1DArrayFloatFloatLevel:
2525 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL;
2527 case NVPTXISD::Tex1DArrayFloatFloatGrad:
2528 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_GRAD;
2530 case NVPTXISD::Tex1DArrayI32I32:
2531 Opc = NVPTX::TEX_1D_ARRAY_I32_I32;
2533 case NVPTXISD::Tex1DArrayI32Float:
2534 Opc = NVPTX::TEX_1D_ARRAY_I32_F32;
2536 case NVPTXISD::Tex1DArrayI32FloatLevel:
2537 Opc = NVPTX::TEX_1D_ARRAY_I32_F32_LEVEL;
2539 case NVPTXISD::Tex1DArrayI32FloatGrad:
2540 Opc = NVPTX::TEX_1D_ARRAY_I32_F32_GRAD;
2542 case NVPTXISD::Tex2DFloatI32:
2543 Opc = NVPTX::TEX_2D_F32_I32;
2545 case NVPTXISD::Tex2DFloatFloat:
2546 Opc = NVPTX::TEX_2D_F32_F32;
2548 case NVPTXISD::Tex2DFloatFloatLevel:
2549 Opc = NVPTX::TEX_2D_F32_F32_LEVEL;
2551 case NVPTXISD::Tex2DFloatFloatGrad:
2552 Opc = NVPTX::TEX_2D_F32_F32_GRAD;
2554 case NVPTXISD::Tex2DI32I32:
2555 Opc = NVPTX::TEX_2D_I32_I32;
2557 case NVPTXISD::Tex2DI32Float:
2558 Opc = NVPTX::TEX_2D_I32_F32;
2560 case NVPTXISD::Tex2DI32FloatLevel:
2561 Opc = NVPTX::TEX_2D_I32_F32_LEVEL;
2563 case NVPTXISD::Tex2DI32FloatGrad:
2564 Opc = NVPTX::TEX_2D_I32_F32_GRAD;
2566 case NVPTXISD::Tex2DArrayFloatI32:
2567 Opc = NVPTX::TEX_2D_ARRAY_F32_I32;
2569 case NVPTXISD::Tex2DArrayFloatFloat:
2570 Opc = NVPTX::TEX_2D_ARRAY_F32_F32;
2572 case NVPTXISD::Tex2DArrayFloatFloatLevel:
2573 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL;
2575 case NVPTXISD::Tex2DArrayFloatFloatGrad:
2576 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_GRAD;
2578 case NVPTXISD::Tex2DArrayI32I32:
2579 Opc = NVPTX::TEX_2D_ARRAY_I32_I32;
2581 case NVPTXISD::Tex2DArrayI32Float:
2582 Opc = NVPTX::TEX_2D_ARRAY_I32_F32;
2584 case NVPTXISD::Tex2DArrayI32FloatLevel:
2585 Opc = NVPTX::TEX_2D_ARRAY_I32_F32_LEVEL;
2587 case NVPTXISD::Tex2DArrayI32FloatGrad:
2588 Opc = NVPTX::TEX_2D_ARRAY_I32_F32_GRAD;
2590 case NVPTXISD::Tex3DFloatI32:
2591 Opc = NVPTX::TEX_3D_F32_I32;
2593 case NVPTXISD::Tex3DFloatFloat:
2594 Opc = NVPTX::TEX_3D_F32_F32;
2596 case NVPTXISD::Tex3DFloatFloatLevel:
2597 Opc = NVPTX::TEX_3D_F32_F32_LEVEL;
2599 case NVPTXISD::Tex3DFloatFloatGrad:
2600 Opc = NVPTX::TEX_3D_F32_F32_GRAD;
2602 case NVPTXISD::Tex3DI32I32:
2603 Opc = NVPTX::TEX_3D_I32_I32;
2605 case NVPTXISD::Tex3DI32Float:
2606 Opc = NVPTX::TEX_3D_I32_F32;
2608 case NVPTXISD::Tex3DI32FloatLevel:
2609 Opc = NVPTX::TEX_3D_I32_F32_LEVEL;
2611 case NVPTXISD::Tex3DI32FloatGrad:
2612 Opc = NVPTX::TEX_3D_I32_F32_GRAD;
2616 Ops.push_back(TexRef);
2617 Ops.push_back(SampRef);
2619 // Copy over indices
2620 for (unsigned i = 3; i < N->getNumOperands(); ++i) {
2621 Ops.push_back(N->getOperand(i));
2624 Ops.push_back(Chain);
2625 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
2629 SDNode *NVPTXDAGToDAGISel::SelectSurfaceIntrinsic(SDNode *N) {
2630 SDValue Chain = N->getOperand(0);
2631 SDValue TexHandle = N->getOperand(1);
2634 SmallVector<SDValue, 8> Ops;
2635 switch (N->getOpcode()) {
2636 default: return NULL;
2637 case NVPTXISD::Suld1DI8Trap:
2638 Opc = NVPTX::SULD_1D_I8_TRAP;
2639 Ops.push_back(TexHandle);
2640 Ops.push_back(N->getOperand(2));
2641 Ops.push_back(Chain);
2643 case NVPTXISD::Suld1DI16Trap:
2644 Opc = NVPTX::SULD_1D_I16_TRAP;
2645 Ops.push_back(TexHandle);
2646 Ops.push_back(N->getOperand(2));
2647 Ops.push_back(Chain);
2649 case NVPTXISD::Suld1DI32Trap:
2650 Opc = NVPTX::SULD_1D_I32_TRAP;
2651 Ops.push_back(TexHandle);
2652 Ops.push_back(N->getOperand(2));
2653 Ops.push_back(Chain);
2655 case NVPTXISD::Suld1DV2I8Trap:
2656 Opc = NVPTX::SULD_1D_V2I8_TRAP;
2657 Ops.push_back(TexHandle);
2658 Ops.push_back(N->getOperand(2));
2659 Ops.push_back(Chain);
2661 case NVPTXISD::Suld1DV2I16Trap:
2662 Opc = NVPTX::SULD_1D_V2I16_TRAP;
2663 Ops.push_back(TexHandle);
2664 Ops.push_back(N->getOperand(2));
2665 Ops.push_back(Chain);
2667 case NVPTXISD::Suld1DV2I32Trap:
2668 Opc = NVPTX::SULD_1D_V2I32_TRAP;
2669 Ops.push_back(TexHandle);
2670 Ops.push_back(N->getOperand(2));
2671 Ops.push_back(Chain);
2673 case NVPTXISD::Suld1DV4I8Trap:
2674 Opc = NVPTX::SULD_1D_V4I8_TRAP;
2675 Ops.push_back(TexHandle);
2676 Ops.push_back(N->getOperand(2));
2677 Ops.push_back(Chain);
2679 case NVPTXISD::Suld1DV4I16Trap:
2680 Opc = NVPTX::SULD_1D_V4I16_TRAP;
2681 Ops.push_back(TexHandle);
2682 Ops.push_back(N->getOperand(2));
2683 Ops.push_back(Chain);
2685 case NVPTXISD::Suld1DV4I32Trap:
2686 Opc = NVPTX::SULD_1D_V4I32_TRAP;
2687 Ops.push_back(TexHandle);
2688 Ops.push_back(N->getOperand(2));
2689 Ops.push_back(Chain);
2691 case NVPTXISD::Suld1DArrayI8Trap:
2692 Opc = NVPTX::SULD_1D_ARRAY_I8_TRAP;
2693 Ops.push_back(TexHandle);
2694 Ops.push_back(N->getOperand(2));
2695 Ops.push_back(N->getOperand(3));
2696 Ops.push_back(Chain);
2698 case NVPTXISD::Suld1DArrayI16Trap:
2699 Opc = NVPTX::SULD_1D_ARRAY_I16_TRAP;
2700 Ops.push_back(TexHandle);
2701 Ops.push_back(N->getOperand(2));
2702 Ops.push_back(N->getOperand(3));
2703 Ops.push_back(Chain);
2705 case NVPTXISD::Suld1DArrayI32Trap:
2706 Opc = NVPTX::SULD_1D_ARRAY_I32_TRAP;
2707 Ops.push_back(TexHandle);
2708 Ops.push_back(N->getOperand(2));
2709 Ops.push_back(N->getOperand(3));
2710 Ops.push_back(Chain);
2712 case NVPTXISD::Suld1DArrayV2I8Trap:
2713 Opc = NVPTX::SULD_1D_ARRAY_V2I8_TRAP;
2714 Ops.push_back(TexHandle);
2715 Ops.push_back(N->getOperand(2));
2716 Ops.push_back(N->getOperand(3));
2717 Ops.push_back(Chain);
2719 case NVPTXISD::Suld1DArrayV2I16Trap:
2720 Opc = NVPTX::SULD_1D_ARRAY_V2I16_TRAP;
2721 Ops.push_back(TexHandle);
2722 Ops.push_back(N->getOperand(2));
2723 Ops.push_back(N->getOperand(3));
2724 Ops.push_back(Chain);
2726 case NVPTXISD::Suld1DArrayV2I32Trap:
2727 Opc = NVPTX::SULD_1D_ARRAY_V2I32_TRAP;
2728 Ops.push_back(TexHandle);
2729 Ops.push_back(N->getOperand(2));
2730 Ops.push_back(N->getOperand(3));
2731 Ops.push_back(Chain);
2733 case NVPTXISD::Suld1DArrayV4I8Trap:
2734 Opc = NVPTX::SULD_1D_ARRAY_V4I8_TRAP;
2735 Ops.push_back(TexHandle);
2736 Ops.push_back(N->getOperand(2));
2737 Ops.push_back(N->getOperand(3));
2738 Ops.push_back(Chain);
2740 case NVPTXISD::Suld1DArrayV4I16Trap:
2741 Opc = NVPTX::SULD_1D_ARRAY_V4I16_TRAP;
2742 Ops.push_back(TexHandle);
2743 Ops.push_back(N->getOperand(2));
2744 Ops.push_back(N->getOperand(3));
2745 Ops.push_back(Chain);
2747 case NVPTXISD::Suld1DArrayV4I32Trap:
2748 Opc = NVPTX::SULD_1D_ARRAY_V4I32_TRAP;
2749 Ops.push_back(TexHandle);
2750 Ops.push_back(N->getOperand(2));
2751 Ops.push_back(N->getOperand(3));
2752 Ops.push_back(Chain);
2754 case NVPTXISD::Suld2DI8Trap:
2755 Opc = NVPTX::SULD_2D_I8_TRAP;
2756 Ops.push_back(TexHandle);
2757 Ops.push_back(N->getOperand(2));
2758 Ops.push_back(N->getOperand(3));
2759 Ops.push_back(Chain);
2761 case NVPTXISD::Suld2DI16Trap:
2762 Opc = NVPTX::SULD_2D_I16_TRAP;
2763 Ops.push_back(TexHandle);
2764 Ops.push_back(N->getOperand(2));
2765 Ops.push_back(N->getOperand(3));
2766 Ops.push_back(Chain);
2768 case NVPTXISD::Suld2DI32Trap:
2769 Opc = NVPTX::SULD_2D_I32_TRAP;
2770 Ops.push_back(TexHandle);
2771 Ops.push_back(N->getOperand(2));
2772 Ops.push_back(N->getOperand(3));
2773 Ops.push_back(Chain);
2775 case NVPTXISD::Suld2DV2I8Trap:
2776 Opc = NVPTX::SULD_2D_V2I8_TRAP;
2777 Ops.push_back(TexHandle);
2778 Ops.push_back(N->getOperand(2));
2779 Ops.push_back(N->getOperand(3));
2780 Ops.push_back(Chain);
2782 case NVPTXISD::Suld2DV2I16Trap:
2783 Opc = NVPTX::SULD_2D_V2I16_TRAP;
2784 Ops.push_back(TexHandle);
2785 Ops.push_back(N->getOperand(2));
2786 Ops.push_back(N->getOperand(3));
2787 Ops.push_back(Chain);
2789 case NVPTXISD::Suld2DV2I32Trap:
2790 Opc = NVPTX::SULD_2D_V2I32_TRAP;
2791 Ops.push_back(TexHandle);
2792 Ops.push_back(N->getOperand(2));
2793 Ops.push_back(N->getOperand(3));
2794 Ops.push_back(Chain);
2796 case NVPTXISD::Suld2DV4I8Trap:
2797 Opc = NVPTX::SULD_2D_V4I8_TRAP;
2798 Ops.push_back(TexHandle);
2799 Ops.push_back(N->getOperand(2));
2800 Ops.push_back(N->getOperand(3));
2801 Ops.push_back(Chain);
2803 case NVPTXISD::Suld2DV4I16Trap:
2804 Opc = NVPTX::SULD_2D_V4I16_TRAP;
2805 Ops.push_back(TexHandle);
2806 Ops.push_back(N->getOperand(2));
2807 Ops.push_back(N->getOperand(3));
2808 Ops.push_back(Chain);
2810 case NVPTXISD::Suld2DV4I32Trap:
2811 Opc = NVPTX::SULD_2D_V4I32_TRAP;
2812 Ops.push_back(TexHandle);
2813 Ops.push_back(N->getOperand(2));
2814 Ops.push_back(N->getOperand(3));
2815 Ops.push_back(Chain);
2817 case NVPTXISD::Suld2DArrayI8Trap:
2818 Opc = NVPTX::SULD_2D_ARRAY_I8_TRAP;
2819 Ops.push_back(TexHandle);
2820 Ops.push_back(N->getOperand(2));
2821 Ops.push_back(N->getOperand(3));
2822 Ops.push_back(N->getOperand(4));
2823 Ops.push_back(Chain);
2825 case NVPTXISD::Suld2DArrayI16Trap:
2826 Opc = NVPTX::SULD_2D_ARRAY_I16_TRAP;
2827 Ops.push_back(TexHandle);
2828 Ops.push_back(N->getOperand(2));
2829 Ops.push_back(N->getOperand(3));
2830 Ops.push_back(N->getOperand(4));
2831 Ops.push_back(Chain);
2833 case NVPTXISD::Suld2DArrayI32Trap:
2834 Opc = NVPTX::SULD_2D_ARRAY_I32_TRAP;
2835 Ops.push_back(TexHandle);
2836 Ops.push_back(N->getOperand(2));
2837 Ops.push_back(N->getOperand(3));
2838 Ops.push_back(N->getOperand(4));
2839 Ops.push_back(Chain);
2841 case NVPTXISD::Suld2DArrayV2I8Trap:
2842 Opc = NVPTX::SULD_2D_ARRAY_V2I8_TRAP;
2843 Ops.push_back(TexHandle);
2844 Ops.push_back(N->getOperand(2));
2845 Ops.push_back(N->getOperand(3));
2846 Ops.push_back(N->getOperand(4));
2847 Ops.push_back(Chain);
2849 case NVPTXISD::Suld2DArrayV2I16Trap:
2850 Opc = NVPTX::SULD_2D_ARRAY_V2I16_TRAP;
2851 Ops.push_back(TexHandle);
2852 Ops.push_back(N->getOperand(2));
2853 Ops.push_back(N->getOperand(3));
2854 Ops.push_back(N->getOperand(4));
2855 Ops.push_back(Chain);
2857 case NVPTXISD::Suld2DArrayV2I32Trap:
2858 Opc = NVPTX::SULD_2D_ARRAY_V2I32_TRAP;
2859 Ops.push_back(TexHandle);
2860 Ops.push_back(N->getOperand(2));
2861 Ops.push_back(N->getOperand(3));
2862 Ops.push_back(N->getOperand(4));
2863 Ops.push_back(Chain);
2865 case NVPTXISD::Suld2DArrayV4I8Trap:
2866 Opc = NVPTX::SULD_2D_ARRAY_V4I8_TRAP;
2867 Ops.push_back(TexHandle);
2868 Ops.push_back(N->getOperand(2));
2869 Ops.push_back(N->getOperand(3));
2870 Ops.push_back(N->getOperand(4));
2871 Ops.push_back(Chain);
2873 case NVPTXISD::Suld2DArrayV4I16Trap:
2874 Opc = NVPTX::SULD_2D_ARRAY_V4I16_TRAP;
2875 Ops.push_back(TexHandle);
2876 Ops.push_back(N->getOperand(2));
2877 Ops.push_back(N->getOperand(3));
2878 Ops.push_back(N->getOperand(4));
2879 Ops.push_back(Chain);
2881 case NVPTXISD::Suld2DArrayV4I32Trap:
2882 Opc = NVPTX::SULD_2D_ARRAY_V4I32_TRAP;
2883 Ops.push_back(TexHandle);
2884 Ops.push_back(N->getOperand(2));
2885 Ops.push_back(N->getOperand(3));
2886 Ops.push_back(N->getOperand(4));
2887 Ops.push_back(Chain);
2889 case NVPTXISD::Suld3DI8Trap:
2890 Opc = NVPTX::SULD_3D_I8_TRAP;
2891 Ops.push_back(TexHandle);
2892 Ops.push_back(N->getOperand(2));
2893 Ops.push_back(N->getOperand(3));
2894 Ops.push_back(N->getOperand(4));
2895 Ops.push_back(Chain);
2897 case NVPTXISD::Suld3DI16Trap:
2898 Opc = NVPTX::SULD_3D_I16_TRAP;
2899 Ops.push_back(TexHandle);
2900 Ops.push_back(N->getOperand(2));
2901 Ops.push_back(N->getOperand(3));
2902 Ops.push_back(N->getOperand(4));
2903 Ops.push_back(Chain);
2905 case NVPTXISD::Suld3DI32Trap:
2906 Opc = NVPTX::SULD_3D_I32_TRAP;
2907 Ops.push_back(TexHandle);
2908 Ops.push_back(N->getOperand(2));
2909 Ops.push_back(N->getOperand(3));
2910 Ops.push_back(N->getOperand(4));
2911 Ops.push_back(Chain);
2913 case NVPTXISD::Suld3DV2I8Trap:
2914 Opc = NVPTX::SULD_3D_V2I8_TRAP;
2915 Ops.push_back(TexHandle);
2916 Ops.push_back(N->getOperand(2));
2917 Ops.push_back(N->getOperand(3));
2918 Ops.push_back(N->getOperand(4));
2919 Ops.push_back(Chain);
2921 case NVPTXISD::Suld3DV2I16Trap:
2922 Opc = NVPTX::SULD_3D_V2I16_TRAP;
2923 Ops.push_back(TexHandle);
2924 Ops.push_back(N->getOperand(2));
2925 Ops.push_back(N->getOperand(3));
2926 Ops.push_back(N->getOperand(4));
2927 Ops.push_back(Chain);
2929 case NVPTXISD::Suld3DV2I32Trap:
2930 Opc = NVPTX::SULD_3D_V2I32_TRAP;
2931 Ops.push_back(TexHandle);
2932 Ops.push_back(N->getOperand(2));
2933 Ops.push_back(N->getOperand(3));
2934 Ops.push_back(N->getOperand(4));
2935 Ops.push_back(Chain);
2937 case NVPTXISD::Suld3DV4I8Trap:
2938 Opc = NVPTX::SULD_3D_V4I8_TRAP;
2939 Ops.push_back(TexHandle);
2940 Ops.push_back(N->getOperand(2));
2941 Ops.push_back(N->getOperand(3));
2942 Ops.push_back(N->getOperand(4));
2943 Ops.push_back(Chain);
2945 case NVPTXISD::Suld3DV4I16Trap:
2946 Opc = NVPTX::SULD_3D_V4I16_TRAP;
2947 Ops.push_back(TexHandle);
2948 Ops.push_back(N->getOperand(2));
2949 Ops.push_back(N->getOperand(3));
2950 Ops.push_back(N->getOperand(4));
2951 Ops.push_back(Chain);
2953 case NVPTXISD::Suld3DV4I32Trap:
2954 Opc = NVPTX::SULD_3D_V4I32_TRAP;
2955 Ops.push_back(TexHandle);
2956 Ops.push_back(N->getOperand(2));
2957 Ops.push_back(N->getOperand(3));
2958 Ops.push_back(N->getOperand(4));
2959 Ops.push_back(Chain);
2962 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
2966 // SelectDirectAddr - Match a direct address for DAG.
2967 // A direct address could be a globaladdress or externalsymbol.
2968 bool NVPTXDAGToDAGISel::SelectDirectAddr(SDValue N, SDValue &Address) {
2969 // Return true if TGA or ES.
2970 if (N.getOpcode() == ISD::TargetGlobalAddress ||
2971 N.getOpcode() == ISD::TargetExternalSymbol) {
2975 if (N.getOpcode() == NVPTXISD::Wrapper) {
2976 Address = N.getOperand(0);
2979 if (N.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
2980 unsigned IID = cast<ConstantSDNode>(N.getOperand(0))->getZExtValue();
2981 if (IID == Intrinsic::nvvm_ptr_gen_to_param)
2982 if (N.getOperand(1).getOpcode() == NVPTXISD::MoveParam)
2983 return (SelectDirectAddr(N.getOperand(1).getOperand(0), Address));
2989 bool NVPTXDAGToDAGISel::SelectADDRsi_imp(
2990 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
2991 if (Addr.getOpcode() == ISD::ADD) {
2992 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
2993 SDValue base = Addr.getOperand(0);
2994 if (SelectDirectAddr(base, Base)) {
2995 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
3004 bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr,
3005 SDValue &Base, SDValue &Offset) {
3006 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32);
3010 bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr,
3011 SDValue &Base, SDValue &Offset) {
3012 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64);
3016 bool NVPTXDAGToDAGISel::SelectADDRri_imp(
3017 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
3018 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
3019 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
3020 Offset = CurDAG->getTargetConstant(0, mvt);
3023 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
3024 Addr.getOpcode() == ISD::TargetGlobalAddress)
3025 return false; // direct calls.
3027 if (Addr.getOpcode() == ISD::ADD) {
3028 if (SelectDirectAddr(Addr.getOperand(0), Addr)) {
3031 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
3032 if (FrameIndexSDNode *FIN =
3033 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
3034 // Constant offset from frame ref.
3035 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
3037 Base = Addr.getOperand(0);
3038 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
3046 bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr,
3047 SDValue &Base, SDValue &Offset) {
3048 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32);
3052 bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr,
3053 SDValue &Base, SDValue &Offset) {
3054 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64);
3057 bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
3058 unsigned int spN) const {
3059 const Value *Src = NULL;
3060 // Even though MemIntrinsicSDNode is a subclas of MemSDNode,
3061 // the classof() for MemSDNode does not include MemIntrinsicSDNode
3062 // (See SelectionDAGNodes.h). So we need to check for both.
3063 if (MemSDNode *mN = dyn_cast<MemSDNode>(N)) {
3064 Src = mN->getSrcValue();
3065 } else if (MemSDNode *mN = dyn_cast<MemIntrinsicSDNode>(N)) {
3066 Src = mN->getSrcValue();
3070 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
3071 return (PT->getAddressSpace() == spN);
3075 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
3076 /// inline asm expressions.
3077 bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
3078 const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
3080 switch (ConstraintCode) {
3084 if (SelectDirectAddr(Op, Op0)) {
3085 OutOps.push_back(Op0);
3086 OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
3089 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
3090 OutOps.push_back(Op0);
3091 OutOps.push_back(Op1);