1 //===-- NVPTXISelDAGToDAG.cpp - A dag to dag inst selector for NVPTX ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXISelDAGToDAG.h"
15 #include "llvm/IR/GlobalValue.h"
16 #include "llvm/IR/Instructions.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Target/TargetIntrinsicInfo.h"
25 #define DEBUG_TYPE "nvptx-isel"
27 static cl::opt<int> UsePrecDivF32(
28 "nvptx-prec-divf32", cl::ZeroOrMore, cl::Hidden,
29 cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
30 " IEEE Compliant F32 div.rnd if available."),
34 UsePrecSqrtF32("nvptx-prec-sqrtf32", cl::Hidden,
35 cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."),
39 FtzEnabled("nvptx-f32ftz", cl::ZeroOrMore, cl::Hidden,
40 cl::desc("NVPTX Specific: Flush f32 subnormals to sign-preserving zero."),
44 /// createNVPTXISelDag - This pass converts a legalized DAG into a
45 /// NVPTX-specific DAG, ready for instruction scheduling.
46 FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
47 llvm::CodeGenOpt::Level OptLevel) {
48 return new NVPTXDAGToDAGISel(TM, OptLevel);
51 NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
52 CodeGenOpt::Level OptLevel)
53 : SelectionDAGISel(tm, OptLevel) {
54 doMulWide = (OptLevel > 0);
57 bool NVPTXDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
58 Subtarget = &static_cast<const NVPTXSubtarget &>(MF.getSubtarget());
59 return SelectionDAGISel::runOnMachineFunction(MF);
62 int NVPTXDAGToDAGISel::getDivF32Level() const {
63 if (UsePrecDivF32.getNumOccurrences() > 0) {
64 // If nvptx-prec-div32=N is used on the command-line, always honor it
67 // Otherwise, use div.approx if fast math is enabled
68 if (TM.Options.UnsafeFPMath)
75 bool NVPTXDAGToDAGISel::usePrecSqrtF32() const {
76 if (UsePrecSqrtF32.getNumOccurrences() > 0) {
77 // If nvptx-prec-sqrtf32 is used on the command-line, always honor it
78 return UsePrecSqrtF32;
80 // Otherwise, use sqrt.approx if fast math is enabled
81 if (TM.Options.UnsafeFPMath)
88 bool NVPTXDAGToDAGISel::useF32FTZ() const {
89 if (FtzEnabled.getNumOccurrences() > 0) {
90 // If nvptx-f32ftz is used on the command-line, always honor it
93 const Function *F = MF->getFunction();
94 // Otherwise, check for an nvptx-f32ftz attribute on the function
95 if (F->hasFnAttribute("nvptx-f32ftz"))
96 return (F->getAttributes().getAttribute(AttributeSet::FunctionIndex,
98 .getValueAsString() == "true");
104 bool NVPTXDAGToDAGISel::allowFMA() const {
105 const NVPTXTargetLowering *TL = Subtarget->getTargetLowering();
106 return TL->allowFMA(*MF, OptLevel);
109 /// Select - Select instructions not customized! Used for
110 /// expanded, promoted and normal instructions.
111 SDNode *NVPTXDAGToDAGISel::Select(SDNode *N) {
113 if (N->isMachineOpcode()) {
115 return nullptr; // Already selected.
118 SDNode *ResNode = nullptr;
119 switch (N->getOpcode()) {
121 ResNode = SelectLoad(N);
124 ResNode = SelectStore(N);
126 case NVPTXISD::LoadV2:
127 case NVPTXISD::LoadV4:
128 ResNode = SelectLoadVector(N);
130 case NVPTXISD::LDGV2:
131 case NVPTXISD::LDGV4:
132 case NVPTXISD::LDUV2:
133 case NVPTXISD::LDUV4:
134 ResNode = SelectLDGLDU(N);
136 case NVPTXISD::StoreV2:
137 case NVPTXISD::StoreV4:
138 ResNode = SelectStoreVector(N);
140 case NVPTXISD::LoadParam:
141 case NVPTXISD::LoadParamV2:
142 case NVPTXISD::LoadParamV4:
143 ResNode = SelectLoadParam(N);
145 case NVPTXISD::StoreRetval:
146 case NVPTXISD::StoreRetvalV2:
147 case NVPTXISD::StoreRetvalV4:
148 ResNode = SelectStoreRetval(N);
150 case NVPTXISD::StoreParam:
151 case NVPTXISD::StoreParamV2:
152 case NVPTXISD::StoreParamV4:
153 case NVPTXISD::StoreParamS32:
154 case NVPTXISD::StoreParamU32:
155 ResNode = SelectStoreParam(N);
157 case ISD::INTRINSIC_WO_CHAIN:
158 ResNode = SelectIntrinsicNoChain(N);
160 case ISD::INTRINSIC_W_CHAIN:
161 ResNode = SelectIntrinsicChain(N);
163 case NVPTXISD::Tex1DFloatS32:
164 case NVPTXISD::Tex1DFloatFloat:
165 case NVPTXISD::Tex1DFloatFloatLevel:
166 case NVPTXISD::Tex1DFloatFloatGrad:
167 case NVPTXISD::Tex1DS32S32:
168 case NVPTXISD::Tex1DS32Float:
169 case NVPTXISD::Tex1DS32FloatLevel:
170 case NVPTXISD::Tex1DS32FloatGrad:
171 case NVPTXISD::Tex1DU32S32:
172 case NVPTXISD::Tex1DU32Float:
173 case NVPTXISD::Tex1DU32FloatLevel:
174 case NVPTXISD::Tex1DU32FloatGrad:
175 case NVPTXISD::Tex1DArrayFloatS32:
176 case NVPTXISD::Tex1DArrayFloatFloat:
177 case NVPTXISD::Tex1DArrayFloatFloatLevel:
178 case NVPTXISD::Tex1DArrayFloatFloatGrad:
179 case NVPTXISD::Tex1DArrayS32S32:
180 case NVPTXISD::Tex1DArrayS32Float:
181 case NVPTXISD::Tex1DArrayS32FloatLevel:
182 case NVPTXISD::Tex1DArrayS32FloatGrad:
183 case NVPTXISD::Tex1DArrayU32S32:
184 case NVPTXISD::Tex1DArrayU32Float:
185 case NVPTXISD::Tex1DArrayU32FloatLevel:
186 case NVPTXISD::Tex1DArrayU32FloatGrad:
187 case NVPTXISD::Tex2DFloatS32:
188 case NVPTXISD::Tex2DFloatFloat:
189 case NVPTXISD::Tex2DFloatFloatLevel:
190 case NVPTXISD::Tex2DFloatFloatGrad:
191 case NVPTXISD::Tex2DS32S32:
192 case NVPTXISD::Tex2DS32Float:
193 case NVPTXISD::Tex2DS32FloatLevel:
194 case NVPTXISD::Tex2DS32FloatGrad:
195 case NVPTXISD::Tex2DU32S32:
196 case NVPTXISD::Tex2DU32Float:
197 case NVPTXISD::Tex2DU32FloatLevel:
198 case NVPTXISD::Tex2DU32FloatGrad:
199 case NVPTXISD::Tex2DArrayFloatS32:
200 case NVPTXISD::Tex2DArrayFloatFloat:
201 case NVPTXISD::Tex2DArrayFloatFloatLevel:
202 case NVPTXISD::Tex2DArrayFloatFloatGrad:
203 case NVPTXISD::Tex2DArrayS32S32:
204 case NVPTXISD::Tex2DArrayS32Float:
205 case NVPTXISD::Tex2DArrayS32FloatLevel:
206 case NVPTXISD::Tex2DArrayS32FloatGrad:
207 case NVPTXISD::Tex2DArrayU32S32:
208 case NVPTXISD::Tex2DArrayU32Float:
209 case NVPTXISD::Tex2DArrayU32FloatLevel:
210 case NVPTXISD::Tex2DArrayU32FloatGrad:
211 case NVPTXISD::Tex3DFloatS32:
212 case NVPTXISD::Tex3DFloatFloat:
213 case NVPTXISD::Tex3DFloatFloatLevel:
214 case NVPTXISD::Tex3DFloatFloatGrad:
215 case NVPTXISD::Tex3DS32S32:
216 case NVPTXISD::Tex3DS32Float:
217 case NVPTXISD::Tex3DS32FloatLevel:
218 case NVPTXISD::Tex3DS32FloatGrad:
219 case NVPTXISD::Tex3DU32S32:
220 case NVPTXISD::Tex3DU32Float:
221 case NVPTXISD::Tex3DU32FloatLevel:
222 case NVPTXISD::Tex3DU32FloatGrad:
223 case NVPTXISD::TexCubeFloatFloat:
224 case NVPTXISD::TexCubeFloatFloatLevel:
225 case NVPTXISD::TexCubeS32Float:
226 case NVPTXISD::TexCubeS32FloatLevel:
227 case NVPTXISD::TexCubeU32Float:
228 case NVPTXISD::TexCubeU32FloatLevel:
229 case NVPTXISD::TexCubeArrayFloatFloat:
230 case NVPTXISD::TexCubeArrayFloatFloatLevel:
231 case NVPTXISD::TexCubeArrayS32Float:
232 case NVPTXISD::TexCubeArrayS32FloatLevel:
233 case NVPTXISD::TexCubeArrayU32Float:
234 case NVPTXISD::TexCubeArrayU32FloatLevel:
235 case NVPTXISD::Tld4R2DFloatFloat:
236 case NVPTXISD::Tld4G2DFloatFloat:
237 case NVPTXISD::Tld4B2DFloatFloat:
238 case NVPTXISD::Tld4A2DFloatFloat:
239 case NVPTXISD::Tld4R2DS64Float:
240 case NVPTXISD::Tld4G2DS64Float:
241 case NVPTXISD::Tld4B2DS64Float:
242 case NVPTXISD::Tld4A2DS64Float:
243 case NVPTXISD::Tld4R2DU64Float:
244 case NVPTXISD::Tld4G2DU64Float:
245 case NVPTXISD::Tld4B2DU64Float:
246 case NVPTXISD::Tld4A2DU64Float:
247 case NVPTXISD::TexUnified1DFloatS32:
248 case NVPTXISD::TexUnified1DFloatFloat:
249 case NVPTXISD::TexUnified1DFloatFloatLevel:
250 case NVPTXISD::TexUnified1DFloatFloatGrad:
251 case NVPTXISD::TexUnified1DS32S32:
252 case NVPTXISD::TexUnified1DS32Float:
253 case NVPTXISD::TexUnified1DS32FloatLevel:
254 case NVPTXISD::TexUnified1DS32FloatGrad:
255 case NVPTXISD::TexUnified1DU32S32:
256 case NVPTXISD::TexUnified1DU32Float:
257 case NVPTXISD::TexUnified1DU32FloatLevel:
258 case NVPTXISD::TexUnified1DU32FloatGrad:
259 case NVPTXISD::TexUnified1DArrayFloatS32:
260 case NVPTXISD::TexUnified1DArrayFloatFloat:
261 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
262 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
263 case NVPTXISD::TexUnified1DArrayS32S32:
264 case NVPTXISD::TexUnified1DArrayS32Float:
265 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
266 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
267 case NVPTXISD::TexUnified1DArrayU32S32:
268 case NVPTXISD::TexUnified1DArrayU32Float:
269 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
270 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
271 case NVPTXISD::TexUnified2DFloatS32:
272 case NVPTXISD::TexUnified2DFloatFloat:
273 case NVPTXISD::TexUnified2DFloatFloatLevel:
274 case NVPTXISD::TexUnified2DFloatFloatGrad:
275 case NVPTXISD::TexUnified2DS32S32:
276 case NVPTXISD::TexUnified2DS32Float:
277 case NVPTXISD::TexUnified2DS32FloatLevel:
278 case NVPTXISD::TexUnified2DS32FloatGrad:
279 case NVPTXISD::TexUnified2DU32S32:
280 case NVPTXISD::TexUnified2DU32Float:
281 case NVPTXISD::TexUnified2DU32FloatLevel:
282 case NVPTXISD::TexUnified2DU32FloatGrad:
283 case NVPTXISD::TexUnified2DArrayFloatS32:
284 case NVPTXISD::TexUnified2DArrayFloatFloat:
285 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
286 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
287 case NVPTXISD::TexUnified2DArrayS32S32:
288 case NVPTXISD::TexUnified2DArrayS32Float:
289 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
290 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
291 case NVPTXISD::TexUnified2DArrayU32S32:
292 case NVPTXISD::TexUnified2DArrayU32Float:
293 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
294 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
295 case NVPTXISD::TexUnified3DFloatS32:
296 case NVPTXISD::TexUnified3DFloatFloat:
297 case NVPTXISD::TexUnified3DFloatFloatLevel:
298 case NVPTXISD::TexUnified3DFloatFloatGrad:
299 case NVPTXISD::TexUnified3DS32S32:
300 case NVPTXISD::TexUnified3DS32Float:
301 case NVPTXISD::TexUnified3DS32FloatLevel:
302 case NVPTXISD::TexUnified3DS32FloatGrad:
303 case NVPTXISD::TexUnified3DU32S32:
304 case NVPTXISD::TexUnified3DU32Float:
305 case NVPTXISD::TexUnified3DU32FloatLevel:
306 case NVPTXISD::TexUnified3DU32FloatGrad:
307 case NVPTXISD::TexUnifiedCubeFloatFloat:
308 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
309 case NVPTXISD::TexUnifiedCubeS32Float:
310 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
311 case NVPTXISD::TexUnifiedCubeU32Float:
312 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
313 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
314 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
315 case NVPTXISD::TexUnifiedCubeArrayS32Float:
316 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
317 case NVPTXISD::TexUnifiedCubeArrayU32Float:
318 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
319 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
320 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
321 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
322 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
323 case NVPTXISD::Tld4UnifiedR2DS64Float:
324 case NVPTXISD::Tld4UnifiedG2DS64Float:
325 case NVPTXISD::Tld4UnifiedB2DS64Float:
326 case NVPTXISD::Tld4UnifiedA2DS64Float:
327 case NVPTXISD::Tld4UnifiedR2DU64Float:
328 case NVPTXISD::Tld4UnifiedG2DU64Float:
329 case NVPTXISD::Tld4UnifiedB2DU64Float:
330 case NVPTXISD::Tld4UnifiedA2DU64Float:
331 ResNode = SelectTextureIntrinsic(N);
333 case NVPTXISD::Suld1DI8Clamp:
334 case NVPTXISD::Suld1DI16Clamp:
335 case NVPTXISD::Suld1DI32Clamp:
336 case NVPTXISD::Suld1DI64Clamp:
337 case NVPTXISD::Suld1DV2I8Clamp:
338 case NVPTXISD::Suld1DV2I16Clamp:
339 case NVPTXISD::Suld1DV2I32Clamp:
340 case NVPTXISD::Suld1DV2I64Clamp:
341 case NVPTXISD::Suld1DV4I8Clamp:
342 case NVPTXISD::Suld1DV4I16Clamp:
343 case NVPTXISD::Suld1DV4I32Clamp:
344 case NVPTXISD::Suld1DArrayI8Clamp:
345 case NVPTXISD::Suld1DArrayI16Clamp:
346 case NVPTXISD::Suld1DArrayI32Clamp:
347 case NVPTXISD::Suld1DArrayI64Clamp:
348 case NVPTXISD::Suld1DArrayV2I8Clamp:
349 case NVPTXISD::Suld1DArrayV2I16Clamp:
350 case NVPTXISD::Suld1DArrayV2I32Clamp:
351 case NVPTXISD::Suld1DArrayV2I64Clamp:
352 case NVPTXISD::Suld1DArrayV4I8Clamp:
353 case NVPTXISD::Suld1DArrayV4I16Clamp:
354 case NVPTXISD::Suld1DArrayV4I32Clamp:
355 case NVPTXISD::Suld2DI8Clamp:
356 case NVPTXISD::Suld2DI16Clamp:
357 case NVPTXISD::Suld2DI32Clamp:
358 case NVPTXISD::Suld2DI64Clamp:
359 case NVPTXISD::Suld2DV2I8Clamp:
360 case NVPTXISD::Suld2DV2I16Clamp:
361 case NVPTXISD::Suld2DV2I32Clamp:
362 case NVPTXISD::Suld2DV2I64Clamp:
363 case NVPTXISD::Suld2DV4I8Clamp:
364 case NVPTXISD::Suld2DV4I16Clamp:
365 case NVPTXISD::Suld2DV4I32Clamp:
366 case NVPTXISD::Suld2DArrayI8Clamp:
367 case NVPTXISD::Suld2DArrayI16Clamp:
368 case NVPTXISD::Suld2DArrayI32Clamp:
369 case NVPTXISD::Suld2DArrayI64Clamp:
370 case NVPTXISD::Suld2DArrayV2I8Clamp:
371 case NVPTXISD::Suld2DArrayV2I16Clamp:
372 case NVPTXISD::Suld2DArrayV2I32Clamp:
373 case NVPTXISD::Suld2DArrayV2I64Clamp:
374 case NVPTXISD::Suld2DArrayV4I8Clamp:
375 case NVPTXISD::Suld2DArrayV4I16Clamp:
376 case NVPTXISD::Suld2DArrayV4I32Clamp:
377 case NVPTXISD::Suld3DI8Clamp:
378 case NVPTXISD::Suld3DI16Clamp:
379 case NVPTXISD::Suld3DI32Clamp:
380 case NVPTXISD::Suld3DI64Clamp:
381 case NVPTXISD::Suld3DV2I8Clamp:
382 case NVPTXISD::Suld3DV2I16Clamp:
383 case NVPTXISD::Suld3DV2I32Clamp:
384 case NVPTXISD::Suld3DV2I64Clamp:
385 case NVPTXISD::Suld3DV4I8Clamp:
386 case NVPTXISD::Suld3DV4I16Clamp:
387 case NVPTXISD::Suld3DV4I32Clamp:
388 case NVPTXISD::Suld1DI8Trap:
389 case NVPTXISD::Suld1DI16Trap:
390 case NVPTXISD::Suld1DI32Trap:
391 case NVPTXISD::Suld1DI64Trap:
392 case NVPTXISD::Suld1DV2I8Trap:
393 case NVPTXISD::Suld1DV2I16Trap:
394 case NVPTXISD::Suld1DV2I32Trap:
395 case NVPTXISD::Suld1DV2I64Trap:
396 case NVPTXISD::Suld1DV4I8Trap:
397 case NVPTXISD::Suld1DV4I16Trap:
398 case NVPTXISD::Suld1DV4I32Trap:
399 case NVPTXISD::Suld1DArrayI8Trap:
400 case NVPTXISD::Suld1DArrayI16Trap:
401 case NVPTXISD::Suld1DArrayI32Trap:
402 case NVPTXISD::Suld1DArrayI64Trap:
403 case NVPTXISD::Suld1DArrayV2I8Trap:
404 case NVPTXISD::Suld1DArrayV2I16Trap:
405 case NVPTXISD::Suld1DArrayV2I32Trap:
406 case NVPTXISD::Suld1DArrayV2I64Trap:
407 case NVPTXISD::Suld1DArrayV4I8Trap:
408 case NVPTXISD::Suld1DArrayV4I16Trap:
409 case NVPTXISD::Suld1DArrayV4I32Trap:
410 case NVPTXISD::Suld2DI8Trap:
411 case NVPTXISD::Suld2DI16Trap:
412 case NVPTXISD::Suld2DI32Trap:
413 case NVPTXISD::Suld2DI64Trap:
414 case NVPTXISD::Suld2DV2I8Trap:
415 case NVPTXISD::Suld2DV2I16Trap:
416 case NVPTXISD::Suld2DV2I32Trap:
417 case NVPTXISD::Suld2DV2I64Trap:
418 case NVPTXISD::Suld2DV4I8Trap:
419 case NVPTXISD::Suld2DV4I16Trap:
420 case NVPTXISD::Suld2DV4I32Trap:
421 case NVPTXISD::Suld2DArrayI8Trap:
422 case NVPTXISD::Suld2DArrayI16Trap:
423 case NVPTXISD::Suld2DArrayI32Trap:
424 case NVPTXISD::Suld2DArrayI64Trap:
425 case NVPTXISD::Suld2DArrayV2I8Trap:
426 case NVPTXISD::Suld2DArrayV2I16Trap:
427 case NVPTXISD::Suld2DArrayV2I32Trap:
428 case NVPTXISD::Suld2DArrayV2I64Trap:
429 case NVPTXISD::Suld2DArrayV4I8Trap:
430 case NVPTXISD::Suld2DArrayV4I16Trap:
431 case NVPTXISD::Suld2DArrayV4I32Trap:
432 case NVPTXISD::Suld3DI8Trap:
433 case NVPTXISD::Suld3DI16Trap:
434 case NVPTXISD::Suld3DI32Trap:
435 case NVPTXISD::Suld3DI64Trap:
436 case NVPTXISD::Suld3DV2I8Trap:
437 case NVPTXISD::Suld3DV2I16Trap:
438 case NVPTXISD::Suld3DV2I32Trap:
439 case NVPTXISD::Suld3DV2I64Trap:
440 case NVPTXISD::Suld3DV4I8Trap:
441 case NVPTXISD::Suld3DV4I16Trap:
442 case NVPTXISD::Suld3DV4I32Trap:
443 case NVPTXISD::Suld1DI8Zero:
444 case NVPTXISD::Suld1DI16Zero:
445 case NVPTXISD::Suld1DI32Zero:
446 case NVPTXISD::Suld1DI64Zero:
447 case NVPTXISD::Suld1DV2I8Zero:
448 case NVPTXISD::Suld1DV2I16Zero:
449 case NVPTXISD::Suld1DV2I32Zero:
450 case NVPTXISD::Suld1DV2I64Zero:
451 case NVPTXISD::Suld1DV4I8Zero:
452 case NVPTXISD::Suld1DV4I16Zero:
453 case NVPTXISD::Suld1DV4I32Zero:
454 case NVPTXISD::Suld1DArrayI8Zero:
455 case NVPTXISD::Suld1DArrayI16Zero:
456 case NVPTXISD::Suld1DArrayI32Zero:
457 case NVPTXISD::Suld1DArrayI64Zero:
458 case NVPTXISD::Suld1DArrayV2I8Zero:
459 case NVPTXISD::Suld1DArrayV2I16Zero:
460 case NVPTXISD::Suld1DArrayV2I32Zero:
461 case NVPTXISD::Suld1DArrayV2I64Zero:
462 case NVPTXISD::Suld1DArrayV4I8Zero:
463 case NVPTXISD::Suld1DArrayV4I16Zero:
464 case NVPTXISD::Suld1DArrayV4I32Zero:
465 case NVPTXISD::Suld2DI8Zero:
466 case NVPTXISD::Suld2DI16Zero:
467 case NVPTXISD::Suld2DI32Zero:
468 case NVPTXISD::Suld2DI64Zero:
469 case NVPTXISD::Suld2DV2I8Zero:
470 case NVPTXISD::Suld2DV2I16Zero:
471 case NVPTXISD::Suld2DV2I32Zero:
472 case NVPTXISD::Suld2DV2I64Zero:
473 case NVPTXISD::Suld2DV4I8Zero:
474 case NVPTXISD::Suld2DV4I16Zero:
475 case NVPTXISD::Suld2DV4I32Zero:
476 case NVPTXISD::Suld2DArrayI8Zero:
477 case NVPTXISD::Suld2DArrayI16Zero:
478 case NVPTXISD::Suld2DArrayI32Zero:
479 case NVPTXISD::Suld2DArrayI64Zero:
480 case NVPTXISD::Suld2DArrayV2I8Zero:
481 case NVPTXISD::Suld2DArrayV2I16Zero:
482 case NVPTXISD::Suld2DArrayV2I32Zero:
483 case NVPTXISD::Suld2DArrayV2I64Zero:
484 case NVPTXISD::Suld2DArrayV4I8Zero:
485 case NVPTXISD::Suld2DArrayV4I16Zero:
486 case NVPTXISD::Suld2DArrayV4I32Zero:
487 case NVPTXISD::Suld3DI8Zero:
488 case NVPTXISD::Suld3DI16Zero:
489 case NVPTXISD::Suld3DI32Zero:
490 case NVPTXISD::Suld3DI64Zero:
491 case NVPTXISD::Suld3DV2I8Zero:
492 case NVPTXISD::Suld3DV2I16Zero:
493 case NVPTXISD::Suld3DV2I32Zero:
494 case NVPTXISD::Suld3DV2I64Zero:
495 case NVPTXISD::Suld3DV4I8Zero:
496 case NVPTXISD::Suld3DV4I16Zero:
497 case NVPTXISD::Suld3DV4I32Zero:
498 ResNode = SelectSurfaceIntrinsic(N);
504 ResNode = SelectBFE(N);
506 case ISD::ADDRSPACECAST:
507 ResNode = SelectAddrSpaceCast(N);
514 return SelectCode(N);
517 SDNode *NVPTXDAGToDAGISel::SelectIntrinsicChain(SDNode *N) {
518 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
522 case Intrinsic::nvvm_ldg_global_f:
523 case Intrinsic::nvvm_ldg_global_i:
524 case Intrinsic::nvvm_ldg_global_p:
525 case Intrinsic::nvvm_ldu_global_f:
526 case Intrinsic::nvvm_ldu_global_i:
527 case Intrinsic::nvvm_ldu_global_p:
528 return SelectLDGLDU(N);
532 static unsigned int getCodeAddrSpace(MemSDNode *N) {
533 const Value *Src = N->getMemOperand()->getValue();
536 return NVPTX::PTXLdStInstCode::GENERIC;
538 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) {
539 switch (PT->getAddressSpace()) {
540 case llvm::ADDRESS_SPACE_LOCAL: return NVPTX::PTXLdStInstCode::LOCAL;
541 case llvm::ADDRESS_SPACE_GLOBAL: return NVPTX::PTXLdStInstCode::GLOBAL;
542 case llvm::ADDRESS_SPACE_SHARED: return NVPTX::PTXLdStInstCode::SHARED;
543 case llvm::ADDRESS_SPACE_GENERIC: return NVPTX::PTXLdStInstCode::GENERIC;
544 case llvm::ADDRESS_SPACE_PARAM: return NVPTX::PTXLdStInstCode::PARAM;
545 case llvm::ADDRESS_SPACE_CONST: return NVPTX::PTXLdStInstCode::CONSTANT;
549 return NVPTX::PTXLdStInstCode::GENERIC;
552 SDNode *NVPTXDAGToDAGISel::SelectIntrinsicNoChain(SDNode *N) {
553 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
557 case Intrinsic::nvvm_texsurf_handle_internal:
558 return SelectTexSurfHandle(N);
562 SDNode *NVPTXDAGToDAGISel::SelectTexSurfHandle(SDNode *N) {
563 // Op 0 is the intrinsic ID
564 SDValue Wrapper = N->getOperand(1);
565 SDValue GlobalVal = Wrapper.getOperand(0);
566 return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64,
570 SDNode *NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
571 SDValue Src = N->getOperand(0);
572 AddrSpaceCastSDNode *CastN = cast<AddrSpaceCastSDNode>(N);
573 unsigned SrcAddrSpace = CastN->getSrcAddressSpace();
574 unsigned DstAddrSpace = CastN->getDestAddressSpace();
576 assert(SrcAddrSpace != DstAddrSpace &&
577 "addrspacecast must be between different address spaces");
579 if (DstAddrSpace == ADDRESS_SPACE_GENERIC) {
580 // Specific to generic
582 switch (SrcAddrSpace) {
583 default: report_fatal_error("Bad address space in addrspacecast");
584 case ADDRESS_SPACE_GLOBAL:
585 Opc = Subtarget->is64Bit() ? NVPTX::cvta_global_yes_64
586 : NVPTX::cvta_global_yes;
588 case ADDRESS_SPACE_SHARED:
589 Opc = Subtarget->is64Bit() ? NVPTX::cvta_shared_yes_64
590 : NVPTX::cvta_shared_yes;
592 case ADDRESS_SPACE_CONST:
593 Opc = Subtarget->is64Bit() ? NVPTX::cvta_const_yes_64
594 : NVPTX::cvta_const_yes;
596 case ADDRESS_SPACE_LOCAL:
597 Opc = Subtarget->is64Bit() ? NVPTX::cvta_local_yes_64
598 : NVPTX::cvta_local_yes;
601 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
603 // Generic to specific
604 if (SrcAddrSpace != 0)
605 report_fatal_error("Cannot cast between two non-generic address spaces");
607 switch (DstAddrSpace) {
608 default: report_fatal_error("Bad address space in addrspacecast");
609 case ADDRESS_SPACE_GLOBAL:
610 Opc = Subtarget->is64Bit() ? NVPTX::cvta_to_global_yes_64
611 : NVPTX::cvta_to_global_yes;
613 case ADDRESS_SPACE_SHARED:
614 Opc = Subtarget->is64Bit() ? NVPTX::cvta_to_shared_yes_64
615 : NVPTX::cvta_to_shared_yes;
617 case ADDRESS_SPACE_CONST:
618 Opc = Subtarget->is64Bit() ? NVPTX::cvta_to_const_yes_64
619 : NVPTX::cvta_to_const_yes;
621 case ADDRESS_SPACE_LOCAL:
622 Opc = Subtarget->is64Bit() ? NVPTX::cvta_to_local_yes_64
623 : NVPTX::cvta_to_local_yes;
626 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src);
630 SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
632 LoadSDNode *LD = cast<LoadSDNode>(N);
633 EVT LoadedVT = LD->getMemoryVT();
634 SDNode *NVPTXLD = nullptr;
636 // do not support pre/post inc/dec
640 if (!LoadedVT.isSimple())
643 // Address Space Setting
644 unsigned int codeAddrSpace = getCodeAddrSpace(LD);
647 // - .volatile is only availalble for .global and .shared
648 bool isVolatile = LD->isVolatile();
649 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
650 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
651 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
655 MVT SimpleVT = LoadedVT.getSimpleVT();
656 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
657 if (SimpleVT.isVector()) {
658 unsigned num = SimpleVT.getVectorNumElements();
660 vecType = NVPTX::PTXLdStInstCode::V2;
662 vecType = NVPTX::PTXLdStInstCode::V4;
667 // Type Setting: fromType + fromTypeWidth
669 // Sign : ISD::SEXTLOAD
670 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
672 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
673 MVT ScalarVT = SimpleVT.getScalarType();
674 // Read at least 8 bits (predicates are stored as 8-bit values)
675 unsigned fromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
676 unsigned int fromType;
677 if ((LD->getExtensionType() == ISD::SEXTLOAD))
678 fromType = NVPTX::PTXLdStInstCode::Signed;
679 else if (ScalarVT.isFloatingPoint())
680 fromType = NVPTX::PTXLdStInstCode::Float;
682 fromType = NVPTX::PTXLdStInstCode::Unsigned;
684 // Create the machine instruction DAG
685 SDValue Chain = N->getOperand(0);
686 SDValue N1 = N->getOperand(1);
688 SDValue Offset, Base;
690 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy;
692 if (SelectDirectAddr(N1, Addr)) {
695 Opcode = NVPTX::LD_i8_avar;
698 Opcode = NVPTX::LD_i16_avar;
701 Opcode = NVPTX::LD_i32_avar;
704 Opcode = NVPTX::LD_i64_avar;
707 Opcode = NVPTX::LD_f32_avar;
710 Opcode = NVPTX::LD_f64_avar;
715 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
716 getI32Imm(vecType), getI32Imm(fromType),
717 getI32Imm(fromTypeWidth), Addr, Chain };
718 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
719 } else if (Subtarget->is64Bit()
720 ? SelectADDRsi64(N1.getNode(), N1, Base, Offset)
721 : SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
724 Opcode = NVPTX::LD_i8_asi;
727 Opcode = NVPTX::LD_i16_asi;
730 Opcode = NVPTX::LD_i32_asi;
733 Opcode = NVPTX::LD_i64_asi;
736 Opcode = NVPTX::LD_f32_asi;
739 Opcode = NVPTX::LD_f64_asi;
744 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
745 getI32Imm(vecType), getI32Imm(fromType),
746 getI32Imm(fromTypeWidth), Base, Offset, Chain };
747 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
748 } else if (Subtarget->is64Bit()
749 ? SelectADDRri64(N1.getNode(), N1, Base, Offset)
750 : SelectADDRri(N1.getNode(), N1, Base, Offset)) {
751 if (Subtarget->is64Bit()) {
754 Opcode = NVPTX::LD_i8_ari_64;
757 Opcode = NVPTX::LD_i16_ari_64;
760 Opcode = NVPTX::LD_i32_ari_64;
763 Opcode = NVPTX::LD_i64_ari_64;
766 Opcode = NVPTX::LD_f32_ari_64;
769 Opcode = NVPTX::LD_f64_ari_64;
777 Opcode = NVPTX::LD_i8_ari;
780 Opcode = NVPTX::LD_i16_ari;
783 Opcode = NVPTX::LD_i32_ari;
786 Opcode = NVPTX::LD_i64_ari;
789 Opcode = NVPTX::LD_f32_ari;
792 Opcode = NVPTX::LD_f64_ari;
798 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
799 getI32Imm(vecType), getI32Imm(fromType),
800 getI32Imm(fromTypeWidth), Base, Offset, Chain };
801 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
803 if (Subtarget->is64Bit()) {
806 Opcode = NVPTX::LD_i8_areg_64;
809 Opcode = NVPTX::LD_i16_areg_64;
812 Opcode = NVPTX::LD_i32_areg_64;
815 Opcode = NVPTX::LD_i64_areg_64;
818 Opcode = NVPTX::LD_f32_areg_64;
821 Opcode = NVPTX::LD_f64_areg_64;
829 Opcode = NVPTX::LD_i8_areg;
832 Opcode = NVPTX::LD_i16_areg;
835 Opcode = NVPTX::LD_i32_areg;
838 Opcode = NVPTX::LD_i64_areg;
841 Opcode = NVPTX::LD_f32_areg;
844 Opcode = NVPTX::LD_f64_areg;
850 SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
851 getI32Imm(vecType), getI32Imm(fromType),
852 getI32Imm(fromTypeWidth), N1, Chain };
853 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops);
857 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
858 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
859 cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
865 SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) {
867 SDValue Chain = N->getOperand(0);
868 SDValue Op1 = N->getOperand(1);
869 SDValue Addr, Offset, Base;
873 MemSDNode *MemSD = cast<MemSDNode>(N);
874 EVT LoadedVT = MemSD->getMemoryVT();
876 if (!LoadedVT.isSimple())
879 // Address Space Setting
880 unsigned int CodeAddrSpace = getCodeAddrSpace(MemSD);
883 // - .volatile is only availalble for .global and .shared
884 bool IsVolatile = MemSD->isVolatile();
885 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
886 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
887 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
891 MVT SimpleVT = LoadedVT.getSimpleVT();
893 // Type Setting: fromType + fromTypeWidth
895 // Sign : ISD::SEXTLOAD
896 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
898 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
899 MVT ScalarVT = SimpleVT.getScalarType();
900 // Read at least 8 bits (predicates are stored as 8-bit values)
901 unsigned FromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
902 unsigned int FromType;
903 // The last operand holds the original LoadSDNode::getExtensionType() value
904 unsigned ExtensionType = cast<ConstantSDNode>(
905 N->getOperand(N->getNumOperands() - 1))->getZExtValue();
906 if (ExtensionType == ISD::SEXTLOAD)
907 FromType = NVPTX::PTXLdStInstCode::Signed;
908 else if (ScalarVT.isFloatingPoint())
909 FromType = NVPTX::PTXLdStInstCode::Float;
911 FromType = NVPTX::PTXLdStInstCode::Unsigned;
915 switch (N->getOpcode()) {
916 case NVPTXISD::LoadV2:
917 VecType = NVPTX::PTXLdStInstCode::V2;
919 case NVPTXISD::LoadV4:
920 VecType = NVPTX::PTXLdStInstCode::V4;
926 EVT EltVT = N->getValueType(0);
928 if (SelectDirectAddr(Op1, Addr)) {
929 switch (N->getOpcode()) {
932 case NVPTXISD::LoadV2:
933 switch (EltVT.getSimpleVT().SimpleTy) {
937 Opcode = NVPTX::LDV_i8_v2_avar;
940 Opcode = NVPTX::LDV_i16_v2_avar;
943 Opcode = NVPTX::LDV_i32_v2_avar;
946 Opcode = NVPTX::LDV_i64_v2_avar;
949 Opcode = NVPTX::LDV_f32_v2_avar;
952 Opcode = NVPTX::LDV_f64_v2_avar;
956 case NVPTXISD::LoadV4:
957 switch (EltVT.getSimpleVT().SimpleTy) {
961 Opcode = NVPTX::LDV_i8_v4_avar;
964 Opcode = NVPTX::LDV_i16_v4_avar;
967 Opcode = NVPTX::LDV_i32_v4_avar;
970 Opcode = NVPTX::LDV_f32_v4_avar;
976 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
977 getI32Imm(VecType), getI32Imm(FromType),
978 getI32Imm(FromTypeWidth), Addr, Chain };
979 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
980 } else if (Subtarget->is64Bit()
981 ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset)
982 : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) {
983 switch (N->getOpcode()) {
986 case NVPTXISD::LoadV2:
987 switch (EltVT.getSimpleVT().SimpleTy) {
991 Opcode = NVPTX::LDV_i8_v2_asi;
994 Opcode = NVPTX::LDV_i16_v2_asi;
997 Opcode = NVPTX::LDV_i32_v2_asi;
1000 Opcode = NVPTX::LDV_i64_v2_asi;
1003 Opcode = NVPTX::LDV_f32_v2_asi;
1006 Opcode = NVPTX::LDV_f64_v2_asi;
1010 case NVPTXISD::LoadV4:
1011 switch (EltVT.getSimpleVT().SimpleTy) {
1015 Opcode = NVPTX::LDV_i8_v4_asi;
1018 Opcode = NVPTX::LDV_i16_v4_asi;
1021 Opcode = NVPTX::LDV_i32_v4_asi;
1024 Opcode = NVPTX::LDV_f32_v4_asi;
1030 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
1031 getI32Imm(VecType), getI32Imm(FromType),
1032 getI32Imm(FromTypeWidth), Base, Offset, Chain };
1033 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1034 } else if (Subtarget->is64Bit()
1035 ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1036 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1037 if (Subtarget->is64Bit()) {
1038 switch (N->getOpcode()) {
1041 case NVPTXISD::LoadV2:
1042 switch (EltVT.getSimpleVT().SimpleTy) {
1046 Opcode = NVPTX::LDV_i8_v2_ari_64;
1049 Opcode = NVPTX::LDV_i16_v2_ari_64;
1052 Opcode = NVPTX::LDV_i32_v2_ari_64;
1055 Opcode = NVPTX::LDV_i64_v2_ari_64;
1058 Opcode = NVPTX::LDV_f32_v2_ari_64;
1061 Opcode = NVPTX::LDV_f64_v2_ari_64;
1065 case NVPTXISD::LoadV4:
1066 switch (EltVT.getSimpleVT().SimpleTy) {
1070 Opcode = NVPTX::LDV_i8_v4_ari_64;
1073 Opcode = NVPTX::LDV_i16_v4_ari_64;
1076 Opcode = NVPTX::LDV_i32_v4_ari_64;
1079 Opcode = NVPTX::LDV_f32_v4_ari_64;
1085 switch (N->getOpcode()) {
1088 case NVPTXISD::LoadV2:
1089 switch (EltVT.getSimpleVT().SimpleTy) {
1093 Opcode = NVPTX::LDV_i8_v2_ari;
1096 Opcode = NVPTX::LDV_i16_v2_ari;
1099 Opcode = NVPTX::LDV_i32_v2_ari;
1102 Opcode = NVPTX::LDV_i64_v2_ari;
1105 Opcode = NVPTX::LDV_f32_v2_ari;
1108 Opcode = NVPTX::LDV_f64_v2_ari;
1112 case NVPTXISD::LoadV4:
1113 switch (EltVT.getSimpleVT().SimpleTy) {
1117 Opcode = NVPTX::LDV_i8_v4_ari;
1120 Opcode = NVPTX::LDV_i16_v4_ari;
1123 Opcode = NVPTX::LDV_i32_v4_ari;
1126 Opcode = NVPTX::LDV_f32_v4_ari;
1133 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
1134 getI32Imm(VecType), getI32Imm(FromType),
1135 getI32Imm(FromTypeWidth), Base, Offset, Chain };
1137 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1139 if (Subtarget->is64Bit()) {
1140 switch (N->getOpcode()) {
1143 case NVPTXISD::LoadV2:
1144 switch (EltVT.getSimpleVT().SimpleTy) {
1148 Opcode = NVPTX::LDV_i8_v2_areg_64;
1151 Opcode = NVPTX::LDV_i16_v2_areg_64;
1154 Opcode = NVPTX::LDV_i32_v2_areg_64;
1157 Opcode = NVPTX::LDV_i64_v2_areg_64;
1160 Opcode = NVPTX::LDV_f32_v2_areg_64;
1163 Opcode = NVPTX::LDV_f64_v2_areg_64;
1167 case NVPTXISD::LoadV4:
1168 switch (EltVT.getSimpleVT().SimpleTy) {
1172 Opcode = NVPTX::LDV_i8_v4_areg_64;
1175 Opcode = NVPTX::LDV_i16_v4_areg_64;
1178 Opcode = NVPTX::LDV_i32_v4_areg_64;
1181 Opcode = NVPTX::LDV_f32_v4_areg_64;
1187 switch (N->getOpcode()) {
1190 case NVPTXISD::LoadV2:
1191 switch (EltVT.getSimpleVT().SimpleTy) {
1195 Opcode = NVPTX::LDV_i8_v2_areg;
1198 Opcode = NVPTX::LDV_i16_v2_areg;
1201 Opcode = NVPTX::LDV_i32_v2_areg;
1204 Opcode = NVPTX::LDV_i64_v2_areg;
1207 Opcode = NVPTX::LDV_f32_v2_areg;
1210 Opcode = NVPTX::LDV_f64_v2_areg;
1214 case NVPTXISD::LoadV4:
1215 switch (EltVT.getSimpleVT().SimpleTy) {
1219 Opcode = NVPTX::LDV_i8_v4_areg;
1222 Opcode = NVPTX::LDV_i16_v4_areg;
1225 Opcode = NVPTX::LDV_i32_v4_areg;
1228 Opcode = NVPTX::LDV_f32_v4_areg;
1235 SDValue Ops[] = { getI32Imm(IsVolatile), getI32Imm(CodeAddrSpace),
1236 getI32Imm(VecType), getI32Imm(FromType),
1237 getI32Imm(FromTypeWidth), Op1, Chain };
1238 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1241 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1242 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
1243 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
1248 SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(SDNode *N) {
1250 SDValue Chain = N->getOperand(0);
1255 // If this is an LDG intrinsic, the address is the third operand. Its its an
1256 // LDG/LDU SD node (from custom vector handling), then its the second operand
1257 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
1258 Op1 = N->getOperand(2);
1259 Mem = cast<MemIntrinsicSDNode>(N);
1260 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1264 case Intrinsic::nvvm_ldg_global_f:
1265 case Intrinsic::nvvm_ldg_global_i:
1266 case Intrinsic::nvvm_ldg_global_p:
1269 case Intrinsic::nvvm_ldu_global_f:
1270 case Intrinsic::nvvm_ldu_global_i:
1271 case Intrinsic::nvvm_ldu_global_p:
1276 Op1 = N->getOperand(1);
1277 Mem = cast<MemSDNode>(N);
1283 SDValue Base, Offset, Addr;
1285 EVT EltVT = Mem->getMemoryVT();
1286 if (EltVT.isVector()) {
1287 EltVT = EltVT.getVectorElementType();
1290 if (SelectDirectAddr(Op1, Addr)) {
1291 switch (N->getOpcode()) {
1294 case ISD::INTRINSIC_W_CHAIN:
1296 switch (EltVT.getSimpleVT().SimpleTy) {
1300 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8avar;
1303 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16avar;
1306 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32avar;
1309 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64avar;
1312 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32avar;
1315 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64avar;
1319 switch (EltVT.getSimpleVT().SimpleTy) {
1323 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8avar;
1326 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16avar;
1329 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32avar;
1332 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64avar;
1335 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32avar;
1338 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64avar;
1343 case NVPTXISD::LDGV2:
1344 switch (EltVT.getSimpleVT().SimpleTy) {
1348 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_avar;
1351 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_avar;
1354 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_avar;
1357 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_avar;
1360 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_avar;
1363 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_avar;
1367 case NVPTXISD::LDUV2:
1368 switch (EltVT.getSimpleVT().SimpleTy) {
1372 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_avar;
1375 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_avar;
1378 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_avar;
1381 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_avar;
1384 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_avar;
1387 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_avar;
1391 case NVPTXISD::LDGV4:
1392 switch (EltVT.getSimpleVT().SimpleTy) {
1396 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_avar;
1399 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_avar;
1402 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_avar;
1405 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_avar;
1409 case NVPTXISD::LDUV4:
1410 switch (EltVT.getSimpleVT().SimpleTy) {
1414 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_avar;
1417 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_avar;
1420 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_avar;
1423 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_avar;
1429 SDValue Ops[] = { Addr, Chain };
1430 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1431 } else if (Subtarget->is64Bit()
1432 ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
1433 : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
1434 if (Subtarget->is64Bit()) {
1435 switch (N->getOpcode()) {
1438 case ISD::INTRINSIC_W_CHAIN:
1440 switch (EltVT.getSimpleVT().SimpleTy) {
1444 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari64;
1447 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari64;
1450 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari64;
1453 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari64;
1456 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari64;
1459 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari64;
1463 switch (EltVT.getSimpleVT().SimpleTy) {
1467 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari64;
1470 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari64;
1473 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari64;
1476 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari64;
1479 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari64;
1482 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari64;
1487 case NVPTXISD::LDGV2:
1488 switch (EltVT.getSimpleVT().SimpleTy) {
1492 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari64;
1495 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari64;
1498 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari64;
1501 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari64;
1504 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari64;
1507 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari64;
1511 case NVPTXISD::LDUV2:
1512 switch (EltVT.getSimpleVT().SimpleTy) {
1516 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari64;
1519 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari64;
1522 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari64;
1525 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari64;
1528 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari64;
1531 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari64;
1535 case NVPTXISD::LDGV4:
1536 switch (EltVT.getSimpleVT().SimpleTy) {
1540 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari64;
1543 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari64;
1546 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari64;
1549 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari64;
1553 case NVPTXISD::LDUV4:
1554 switch (EltVT.getSimpleVT().SimpleTy) {
1558 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari64;
1561 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari64;
1564 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari64;
1567 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari64;
1573 switch (N->getOpcode()) {
1576 case ISD::INTRINSIC_W_CHAIN:
1578 switch (EltVT.getSimpleVT().SimpleTy) {
1582 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8ari;
1585 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16ari;
1588 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32ari;
1591 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64ari;
1594 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32ari;
1597 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64ari;
1601 switch (EltVT.getSimpleVT().SimpleTy) {
1605 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8ari;
1608 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16ari;
1611 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32ari;
1614 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64ari;
1617 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32ari;
1620 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64ari;
1625 case NVPTXISD::LDGV2:
1626 switch (EltVT.getSimpleVT().SimpleTy) {
1630 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_ari32;
1633 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_ari32;
1636 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_ari32;
1639 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_ari32;
1642 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_ari32;
1645 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_ari32;
1649 case NVPTXISD::LDUV2:
1650 switch (EltVT.getSimpleVT().SimpleTy) {
1654 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_ari32;
1657 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_ari32;
1660 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_ari32;
1663 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_ari32;
1666 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_ari32;
1669 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_ari32;
1673 case NVPTXISD::LDGV4:
1674 switch (EltVT.getSimpleVT().SimpleTy) {
1678 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_ari32;
1681 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_ari32;
1684 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_ari32;
1687 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_ari32;
1691 case NVPTXISD::LDUV4:
1692 switch (EltVT.getSimpleVT().SimpleTy) {
1696 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_ari32;
1699 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_ari32;
1702 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_ari32;
1705 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_ari32;
1712 SDValue Ops[] = { Base, Offset, Chain };
1714 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1716 if (Subtarget->is64Bit()) {
1717 switch (N->getOpcode()) {
1720 case ISD::INTRINSIC_W_CHAIN:
1722 switch (EltVT.getSimpleVT().SimpleTy) {
1726 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg64;
1729 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg64;
1732 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg64;
1735 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg64;
1738 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg64;
1741 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg64;
1745 switch (EltVT.getSimpleVT().SimpleTy) {
1749 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg64;
1752 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg64;
1755 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg64;
1758 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg64;
1761 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg64;
1764 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg64;
1769 case NVPTXISD::LDGV2:
1770 switch (EltVT.getSimpleVT().SimpleTy) {
1774 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg64;
1777 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg64;
1780 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg64;
1783 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg64;
1786 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg64;
1789 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg64;
1793 case NVPTXISD::LDUV2:
1794 switch (EltVT.getSimpleVT().SimpleTy) {
1798 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg64;
1801 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg64;
1804 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg64;
1807 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg64;
1810 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg64;
1813 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg64;
1817 case NVPTXISD::LDGV4:
1818 switch (EltVT.getSimpleVT().SimpleTy) {
1822 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg64;
1825 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg64;
1828 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg64;
1831 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg64;
1835 case NVPTXISD::LDUV4:
1836 switch (EltVT.getSimpleVT().SimpleTy) {
1840 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg64;
1843 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg64;
1846 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg64;
1849 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg64;
1855 switch (N->getOpcode()) {
1858 case ISD::INTRINSIC_W_CHAIN:
1860 switch (EltVT.getSimpleVT().SimpleTy) {
1864 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i8areg;
1867 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i16areg;
1870 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i32areg;
1873 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_i64areg;
1876 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f32areg;
1879 Opcode = NVPTX::INT_PTX_LDG_GLOBAL_f64areg;
1883 switch (EltVT.getSimpleVT().SimpleTy) {
1887 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i8areg;
1890 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i16areg;
1893 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i32areg;
1896 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_i64areg;
1899 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f32areg;
1902 Opcode = NVPTX::INT_PTX_LDU_GLOBAL_f64areg;
1907 case NVPTXISD::LDGV2:
1908 switch (EltVT.getSimpleVT().SimpleTy) {
1912 Opcode = NVPTX::INT_PTX_LDG_G_v2i8_ELE_areg32;
1915 Opcode = NVPTX::INT_PTX_LDG_G_v2i16_ELE_areg32;
1918 Opcode = NVPTX::INT_PTX_LDG_G_v2i32_ELE_areg32;
1921 Opcode = NVPTX::INT_PTX_LDG_G_v2i64_ELE_areg32;
1924 Opcode = NVPTX::INT_PTX_LDG_G_v2f32_ELE_areg32;
1927 Opcode = NVPTX::INT_PTX_LDG_G_v2f64_ELE_areg32;
1931 case NVPTXISD::LDUV2:
1932 switch (EltVT.getSimpleVT().SimpleTy) {
1936 Opcode = NVPTX::INT_PTX_LDU_G_v2i8_ELE_areg32;
1939 Opcode = NVPTX::INT_PTX_LDU_G_v2i16_ELE_areg32;
1942 Opcode = NVPTX::INT_PTX_LDU_G_v2i32_ELE_areg32;
1945 Opcode = NVPTX::INT_PTX_LDU_G_v2i64_ELE_areg32;
1948 Opcode = NVPTX::INT_PTX_LDU_G_v2f32_ELE_areg32;
1951 Opcode = NVPTX::INT_PTX_LDU_G_v2f64_ELE_areg32;
1955 case NVPTXISD::LDGV4:
1956 switch (EltVT.getSimpleVT().SimpleTy) {
1960 Opcode = NVPTX::INT_PTX_LDG_G_v4i8_ELE_areg32;
1963 Opcode = NVPTX::INT_PTX_LDG_G_v4i16_ELE_areg32;
1966 Opcode = NVPTX::INT_PTX_LDG_G_v4i32_ELE_areg32;
1969 Opcode = NVPTX::INT_PTX_LDG_G_v4f32_ELE_areg32;
1973 case NVPTXISD::LDUV4:
1974 switch (EltVT.getSimpleVT().SimpleTy) {
1978 Opcode = NVPTX::INT_PTX_LDU_G_v4i8_ELE_areg32;
1981 Opcode = NVPTX::INT_PTX_LDU_G_v4i16_ELE_areg32;
1984 Opcode = NVPTX::INT_PTX_LDU_G_v4i32_ELE_areg32;
1987 Opcode = NVPTX::INT_PTX_LDU_G_v4f32_ELE_areg32;
1994 SDValue Ops[] = { Op1, Chain };
1995 LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
1998 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
1999 MemRefs0[0] = Mem->getMemOperand();
2000 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1);
2005 SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
2007 StoreSDNode *ST = cast<StoreSDNode>(N);
2008 EVT StoreVT = ST->getMemoryVT();
2009 SDNode *NVPTXST = nullptr;
2011 // do not support pre/post inc/dec
2012 if (ST->isIndexed())
2015 if (!StoreVT.isSimple())
2018 // Address Space Setting
2019 unsigned int codeAddrSpace = getCodeAddrSpace(ST);
2022 // - .volatile is only availalble for .global and .shared
2023 bool isVolatile = ST->isVolatile();
2024 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
2025 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
2026 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
2030 MVT SimpleVT = StoreVT.getSimpleVT();
2031 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
2032 if (SimpleVT.isVector()) {
2033 unsigned num = SimpleVT.getVectorNumElements();
2035 vecType = NVPTX::PTXLdStInstCode::V2;
2037 vecType = NVPTX::PTXLdStInstCode::V4;
2042 // Type Setting: toType + toTypeWidth
2043 // - for integer type, always use 'u'
2045 MVT ScalarVT = SimpleVT.getScalarType();
2046 unsigned toTypeWidth = ScalarVT.getSizeInBits();
2047 unsigned int toType;
2048 if (ScalarVT.isFloatingPoint())
2049 toType = NVPTX::PTXLdStInstCode::Float;
2051 toType = NVPTX::PTXLdStInstCode::Unsigned;
2053 // Create the machine instruction DAG
2054 SDValue Chain = N->getOperand(0);
2055 SDValue N1 = N->getOperand(1);
2056 SDValue N2 = N->getOperand(2);
2058 SDValue Offset, Base;
2060 MVT::SimpleValueType SourceVT = N1.getNode()->getSimpleValueType(0).SimpleTy;
2062 if (SelectDirectAddr(N2, Addr)) {
2065 Opcode = NVPTX::ST_i8_avar;
2068 Opcode = NVPTX::ST_i16_avar;
2071 Opcode = NVPTX::ST_i32_avar;
2074 Opcode = NVPTX::ST_i64_avar;
2077 Opcode = NVPTX::ST_f32_avar;
2080 Opcode = NVPTX::ST_f64_avar;
2085 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
2086 getI32Imm(vecType), getI32Imm(toType),
2087 getI32Imm(toTypeWidth), Addr, Chain };
2088 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2089 } else if (Subtarget->is64Bit()
2090 ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2091 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
2094 Opcode = NVPTX::ST_i8_asi;
2097 Opcode = NVPTX::ST_i16_asi;
2100 Opcode = NVPTX::ST_i32_asi;
2103 Opcode = NVPTX::ST_i64_asi;
2106 Opcode = NVPTX::ST_f32_asi;
2109 Opcode = NVPTX::ST_f64_asi;
2114 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
2115 getI32Imm(vecType), getI32Imm(toType),
2116 getI32Imm(toTypeWidth), Base, Offset, Chain };
2117 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2118 } else if (Subtarget->is64Bit()
2119 ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2120 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
2121 if (Subtarget->is64Bit()) {
2124 Opcode = NVPTX::ST_i8_ari_64;
2127 Opcode = NVPTX::ST_i16_ari_64;
2130 Opcode = NVPTX::ST_i32_ari_64;
2133 Opcode = NVPTX::ST_i64_ari_64;
2136 Opcode = NVPTX::ST_f32_ari_64;
2139 Opcode = NVPTX::ST_f64_ari_64;
2147 Opcode = NVPTX::ST_i8_ari;
2150 Opcode = NVPTX::ST_i16_ari;
2153 Opcode = NVPTX::ST_i32_ari;
2156 Opcode = NVPTX::ST_i64_ari;
2159 Opcode = NVPTX::ST_f32_ari;
2162 Opcode = NVPTX::ST_f64_ari;
2168 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
2169 getI32Imm(vecType), getI32Imm(toType),
2170 getI32Imm(toTypeWidth), Base, Offset, Chain };
2171 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2173 if (Subtarget->is64Bit()) {
2176 Opcode = NVPTX::ST_i8_areg_64;
2179 Opcode = NVPTX::ST_i16_areg_64;
2182 Opcode = NVPTX::ST_i32_areg_64;
2185 Opcode = NVPTX::ST_i64_areg_64;
2188 Opcode = NVPTX::ST_f32_areg_64;
2191 Opcode = NVPTX::ST_f64_areg_64;
2199 Opcode = NVPTX::ST_i8_areg;
2202 Opcode = NVPTX::ST_i16_areg;
2205 Opcode = NVPTX::ST_i32_areg;
2208 Opcode = NVPTX::ST_i64_areg;
2211 Opcode = NVPTX::ST_f32_areg;
2214 Opcode = NVPTX::ST_f64_areg;
2220 SDValue Ops[] = { N1, getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
2221 getI32Imm(vecType), getI32Imm(toType),
2222 getI32Imm(toTypeWidth), N2, Chain };
2223 NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
2227 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2228 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2229 cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2235 SDNode *NVPTXDAGToDAGISel::SelectStoreVector(SDNode *N) {
2236 SDValue Chain = N->getOperand(0);
2237 SDValue Op1 = N->getOperand(1);
2238 SDValue Addr, Offset, Base;
2242 EVT EltVT = Op1.getValueType();
2243 MemSDNode *MemSD = cast<MemSDNode>(N);
2244 EVT StoreVT = MemSD->getMemoryVT();
2246 // Address Space Setting
2247 unsigned CodeAddrSpace = getCodeAddrSpace(MemSD);
2249 if (CodeAddrSpace == NVPTX::PTXLdStInstCode::CONSTANT) {
2250 report_fatal_error("Cannot store to pointer that points to constant "
2255 // - .volatile is only availalble for .global and .shared
2256 bool IsVolatile = MemSD->isVolatile();
2257 if (CodeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
2258 CodeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
2259 CodeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
2262 // Type Setting: toType + toTypeWidth
2263 // - for integer type, always use 'u'
2264 assert(StoreVT.isSimple() && "Store value is not simple");
2265 MVT ScalarVT = StoreVT.getSimpleVT().getScalarType();
2266 unsigned ToTypeWidth = ScalarVT.getSizeInBits();
2268 if (ScalarVT.isFloatingPoint())
2269 ToType = NVPTX::PTXLdStInstCode::Float;
2271 ToType = NVPTX::PTXLdStInstCode::Unsigned;
2273 SmallVector<SDValue, 12> StOps;
2277 switch (N->getOpcode()) {
2278 case NVPTXISD::StoreV2:
2279 VecType = NVPTX::PTXLdStInstCode::V2;
2280 StOps.push_back(N->getOperand(1));
2281 StOps.push_back(N->getOperand(2));
2282 N2 = N->getOperand(3);
2284 case NVPTXISD::StoreV4:
2285 VecType = NVPTX::PTXLdStInstCode::V4;
2286 StOps.push_back(N->getOperand(1));
2287 StOps.push_back(N->getOperand(2));
2288 StOps.push_back(N->getOperand(3));
2289 StOps.push_back(N->getOperand(4));
2290 N2 = N->getOperand(5);
2296 StOps.push_back(getI32Imm(IsVolatile));
2297 StOps.push_back(getI32Imm(CodeAddrSpace));
2298 StOps.push_back(getI32Imm(VecType));
2299 StOps.push_back(getI32Imm(ToType));
2300 StOps.push_back(getI32Imm(ToTypeWidth));
2302 if (SelectDirectAddr(N2, Addr)) {
2303 switch (N->getOpcode()) {
2306 case NVPTXISD::StoreV2:
2307 switch (EltVT.getSimpleVT().SimpleTy) {
2311 Opcode = NVPTX::STV_i8_v2_avar;
2314 Opcode = NVPTX::STV_i16_v2_avar;
2317 Opcode = NVPTX::STV_i32_v2_avar;
2320 Opcode = NVPTX::STV_i64_v2_avar;
2323 Opcode = NVPTX::STV_f32_v2_avar;
2326 Opcode = NVPTX::STV_f64_v2_avar;
2330 case NVPTXISD::StoreV4:
2331 switch (EltVT.getSimpleVT().SimpleTy) {
2335 Opcode = NVPTX::STV_i8_v4_avar;
2338 Opcode = NVPTX::STV_i16_v4_avar;
2341 Opcode = NVPTX::STV_i32_v4_avar;
2344 Opcode = NVPTX::STV_f32_v4_avar;
2349 StOps.push_back(Addr);
2350 } else if (Subtarget->is64Bit()
2351 ? SelectADDRsi64(N2.getNode(), N2, Base, Offset)
2352 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
2353 switch (N->getOpcode()) {
2356 case NVPTXISD::StoreV2:
2357 switch (EltVT.getSimpleVT().SimpleTy) {
2361 Opcode = NVPTX::STV_i8_v2_asi;
2364 Opcode = NVPTX::STV_i16_v2_asi;
2367 Opcode = NVPTX::STV_i32_v2_asi;
2370 Opcode = NVPTX::STV_i64_v2_asi;
2373 Opcode = NVPTX::STV_f32_v2_asi;
2376 Opcode = NVPTX::STV_f64_v2_asi;
2380 case NVPTXISD::StoreV4:
2381 switch (EltVT.getSimpleVT().SimpleTy) {
2385 Opcode = NVPTX::STV_i8_v4_asi;
2388 Opcode = NVPTX::STV_i16_v4_asi;
2391 Opcode = NVPTX::STV_i32_v4_asi;
2394 Opcode = NVPTX::STV_f32_v4_asi;
2399 StOps.push_back(Base);
2400 StOps.push_back(Offset);
2401 } else if (Subtarget->is64Bit()
2402 ? SelectADDRri64(N2.getNode(), N2, Base, Offset)
2403 : SelectADDRri(N2.getNode(), N2, Base, Offset)) {
2404 if (Subtarget->is64Bit()) {
2405 switch (N->getOpcode()) {
2408 case NVPTXISD::StoreV2:
2409 switch (EltVT.getSimpleVT().SimpleTy) {
2413 Opcode = NVPTX::STV_i8_v2_ari_64;
2416 Opcode = NVPTX::STV_i16_v2_ari_64;
2419 Opcode = NVPTX::STV_i32_v2_ari_64;
2422 Opcode = NVPTX::STV_i64_v2_ari_64;
2425 Opcode = NVPTX::STV_f32_v2_ari_64;
2428 Opcode = NVPTX::STV_f64_v2_ari_64;
2432 case NVPTXISD::StoreV4:
2433 switch (EltVT.getSimpleVT().SimpleTy) {
2437 Opcode = NVPTX::STV_i8_v4_ari_64;
2440 Opcode = NVPTX::STV_i16_v4_ari_64;
2443 Opcode = NVPTX::STV_i32_v4_ari_64;
2446 Opcode = NVPTX::STV_f32_v4_ari_64;
2452 switch (N->getOpcode()) {
2455 case NVPTXISD::StoreV2:
2456 switch (EltVT.getSimpleVT().SimpleTy) {
2460 Opcode = NVPTX::STV_i8_v2_ari;
2463 Opcode = NVPTX::STV_i16_v2_ari;
2466 Opcode = NVPTX::STV_i32_v2_ari;
2469 Opcode = NVPTX::STV_i64_v2_ari;
2472 Opcode = NVPTX::STV_f32_v2_ari;
2475 Opcode = NVPTX::STV_f64_v2_ari;
2479 case NVPTXISD::StoreV4:
2480 switch (EltVT.getSimpleVT().SimpleTy) {
2484 Opcode = NVPTX::STV_i8_v4_ari;
2487 Opcode = NVPTX::STV_i16_v4_ari;
2490 Opcode = NVPTX::STV_i32_v4_ari;
2493 Opcode = NVPTX::STV_f32_v4_ari;
2499 StOps.push_back(Base);
2500 StOps.push_back(Offset);
2502 if (Subtarget->is64Bit()) {
2503 switch (N->getOpcode()) {
2506 case NVPTXISD::StoreV2:
2507 switch (EltVT.getSimpleVT().SimpleTy) {
2511 Opcode = NVPTX::STV_i8_v2_areg_64;
2514 Opcode = NVPTX::STV_i16_v2_areg_64;
2517 Opcode = NVPTX::STV_i32_v2_areg_64;
2520 Opcode = NVPTX::STV_i64_v2_areg_64;
2523 Opcode = NVPTX::STV_f32_v2_areg_64;
2526 Opcode = NVPTX::STV_f64_v2_areg_64;
2530 case NVPTXISD::StoreV4:
2531 switch (EltVT.getSimpleVT().SimpleTy) {
2535 Opcode = NVPTX::STV_i8_v4_areg_64;
2538 Opcode = NVPTX::STV_i16_v4_areg_64;
2541 Opcode = NVPTX::STV_i32_v4_areg_64;
2544 Opcode = NVPTX::STV_f32_v4_areg_64;
2550 switch (N->getOpcode()) {
2553 case NVPTXISD::StoreV2:
2554 switch (EltVT.getSimpleVT().SimpleTy) {
2558 Opcode = NVPTX::STV_i8_v2_areg;
2561 Opcode = NVPTX::STV_i16_v2_areg;
2564 Opcode = NVPTX::STV_i32_v2_areg;
2567 Opcode = NVPTX::STV_i64_v2_areg;
2570 Opcode = NVPTX::STV_f32_v2_areg;
2573 Opcode = NVPTX::STV_f64_v2_areg;
2577 case NVPTXISD::StoreV4:
2578 switch (EltVT.getSimpleVT().SimpleTy) {
2582 Opcode = NVPTX::STV_i8_v4_areg;
2585 Opcode = NVPTX::STV_i16_v4_areg;
2588 Opcode = NVPTX::STV_i32_v4_areg;
2591 Opcode = NVPTX::STV_f32_v4_areg;
2597 StOps.push_back(N2);
2600 StOps.push_back(Chain);
2602 ST = CurDAG->getMachineNode(Opcode, DL, MVT::Other, StOps);
2604 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2605 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2606 cast<MachineSDNode>(ST)->setMemRefs(MemRefs0, MemRefs0 + 1);
2611 SDNode *NVPTXDAGToDAGISel::SelectLoadParam(SDNode *Node) {
2612 SDValue Chain = Node->getOperand(0);
2613 SDValue Offset = Node->getOperand(2);
2614 SDValue Flag = Node->getOperand(3);
2616 MemSDNode *Mem = cast<MemSDNode>(Node);
2619 switch (Node->getOpcode()) {
2622 case NVPTXISD::LoadParam:
2625 case NVPTXISD::LoadParamV2:
2628 case NVPTXISD::LoadParamV4:
2633 EVT EltVT = Node->getValueType(0);
2634 EVT MemVT = Mem->getMemoryVT();
2642 switch (MemVT.getSimpleVT().SimpleTy) {
2646 Opc = NVPTX::LoadParamMemI8;
2649 Opc = NVPTX::LoadParamMemI8;
2652 Opc = NVPTX::LoadParamMemI16;
2655 Opc = NVPTX::LoadParamMemI32;
2658 Opc = NVPTX::LoadParamMemI64;
2661 Opc = NVPTX::LoadParamMemF32;
2664 Opc = NVPTX::LoadParamMemF64;
2669 switch (MemVT.getSimpleVT().SimpleTy) {
2673 Opc = NVPTX::LoadParamMemV2I8;
2676 Opc = NVPTX::LoadParamMemV2I8;
2679 Opc = NVPTX::LoadParamMemV2I16;
2682 Opc = NVPTX::LoadParamMemV2I32;
2685 Opc = NVPTX::LoadParamMemV2I64;
2688 Opc = NVPTX::LoadParamMemV2F32;
2691 Opc = NVPTX::LoadParamMemV2F64;
2696 switch (MemVT.getSimpleVT().SimpleTy) {
2700 Opc = NVPTX::LoadParamMemV4I8;
2703 Opc = NVPTX::LoadParamMemV4I8;
2706 Opc = NVPTX::LoadParamMemV4I16;
2709 Opc = NVPTX::LoadParamMemV4I32;
2712 Opc = NVPTX::LoadParamMemV4F32;
2720 VTs = CurDAG->getVTList(EltVT, MVT::Other, MVT::Glue);
2721 } else if (VecSize == 2) {
2722 VTs = CurDAG->getVTList(EltVT, EltVT, MVT::Other, MVT::Glue);
2724 EVT EVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other, MVT::Glue };
2725 VTs = CurDAG->getVTList(EVTs);
2728 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2730 SmallVector<SDValue, 2> Ops;
2731 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2732 Ops.push_back(Chain);
2733 Ops.push_back(Flag);
2736 CurDAG->getMachineNode(Opc, DL, VTs, Ops);
2740 SDNode *NVPTXDAGToDAGISel::SelectStoreRetval(SDNode *N) {
2742 SDValue Chain = N->getOperand(0);
2743 SDValue Offset = N->getOperand(1);
2744 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2745 MemSDNode *Mem = cast<MemSDNode>(N);
2747 // How many elements do we have?
2748 unsigned NumElts = 1;
2749 switch (N->getOpcode()) {
2752 case NVPTXISD::StoreRetval:
2755 case NVPTXISD::StoreRetvalV2:
2758 case NVPTXISD::StoreRetvalV4:
2763 // Build vector of operands
2764 SmallVector<SDValue, 6> Ops;
2765 for (unsigned i = 0; i < NumElts; ++i)
2766 Ops.push_back(N->getOperand(i + 2));
2767 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2768 Ops.push_back(Chain);
2770 // Determine target opcode
2771 // If we have an i1, use an 8-bit store. The lowering code in
2772 // NVPTXISelLowering will have already emitted an upcast.
2773 unsigned Opcode = 0;
2778 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2782 Opcode = NVPTX::StoreRetvalI8;
2785 Opcode = NVPTX::StoreRetvalI8;
2788 Opcode = NVPTX::StoreRetvalI16;
2791 Opcode = NVPTX::StoreRetvalI32;
2794 Opcode = NVPTX::StoreRetvalI64;
2797 Opcode = NVPTX::StoreRetvalF32;
2800 Opcode = NVPTX::StoreRetvalF64;
2805 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2809 Opcode = NVPTX::StoreRetvalV2I8;
2812 Opcode = NVPTX::StoreRetvalV2I8;
2815 Opcode = NVPTX::StoreRetvalV2I16;
2818 Opcode = NVPTX::StoreRetvalV2I32;
2821 Opcode = NVPTX::StoreRetvalV2I64;
2824 Opcode = NVPTX::StoreRetvalV2F32;
2827 Opcode = NVPTX::StoreRetvalV2F64;
2832 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2836 Opcode = NVPTX::StoreRetvalV4I8;
2839 Opcode = NVPTX::StoreRetvalV4I8;
2842 Opcode = NVPTX::StoreRetvalV4I16;
2845 Opcode = NVPTX::StoreRetvalV4I32;
2848 Opcode = NVPTX::StoreRetvalV4F32;
2855 CurDAG->getMachineNode(Opcode, DL, MVT::Other, Ops);
2856 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
2857 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
2858 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
2863 SDNode *NVPTXDAGToDAGISel::SelectStoreParam(SDNode *N) {
2865 SDValue Chain = N->getOperand(0);
2866 SDValue Param = N->getOperand(1);
2867 unsigned ParamVal = cast<ConstantSDNode>(Param)->getZExtValue();
2868 SDValue Offset = N->getOperand(2);
2869 unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
2870 MemSDNode *Mem = cast<MemSDNode>(N);
2871 SDValue Flag = N->getOperand(N->getNumOperands() - 1);
2873 // How many elements do we have?
2874 unsigned NumElts = 1;
2875 switch (N->getOpcode()) {
2878 case NVPTXISD::StoreParamU32:
2879 case NVPTXISD::StoreParamS32:
2880 case NVPTXISD::StoreParam:
2883 case NVPTXISD::StoreParamV2:
2886 case NVPTXISD::StoreParamV4:
2891 // Build vector of operands
2892 SmallVector<SDValue, 8> Ops;
2893 for (unsigned i = 0; i < NumElts; ++i)
2894 Ops.push_back(N->getOperand(i + 3));
2895 Ops.push_back(CurDAG->getTargetConstant(ParamVal, MVT::i32));
2896 Ops.push_back(CurDAG->getTargetConstant(OffsetVal, MVT::i32));
2897 Ops.push_back(Chain);
2898 Ops.push_back(Flag);
2900 // Determine target opcode
2901 // If we have an i1, use an 8-bit store. The lowering code in
2902 // NVPTXISelLowering will have already emitted an upcast.
2903 unsigned Opcode = 0;
2904 switch (N->getOpcode()) {
2910 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2914 Opcode = NVPTX::StoreParamI8;
2917 Opcode = NVPTX::StoreParamI8;
2920 Opcode = NVPTX::StoreParamI16;
2923 Opcode = NVPTX::StoreParamI32;
2926 Opcode = NVPTX::StoreParamI64;
2929 Opcode = NVPTX::StoreParamF32;
2932 Opcode = NVPTX::StoreParamF64;
2937 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2941 Opcode = NVPTX::StoreParamV2I8;
2944 Opcode = NVPTX::StoreParamV2I8;
2947 Opcode = NVPTX::StoreParamV2I16;
2950 Opcode = NVPTX::StoreParamV2I32;
2953 Opcode = NVPTX::StoreParamV2I64;
2956 Opcode = NVPTX::StoreParamV2F32;
2959 Opcode = NVPTX::StoreParamV2F64;
2964 switch (Mem->getMemoryVT().getSimpleVT().SimpleTy) {
2968 Opcode = NVPTX::StoreParamV4I8;
2971 Opcode = NVPTX::StoreParamV4I8;
2974 Opcode = NVPTX::StoreParamV4I16;
2977 Opcode = NVPTX::StoreParamV4I32;
2980 Opcode = NVPTX::StoreParamV4F32;
2986 // Special case: if we have a sign-extend/zero-extend node, insert the
2987 // conversion instruction first, and use that as the value operand to
2988 // the selected StoreParam node.
2989 case NVPTXISD::StoreParamU32: {
2990 Opcode = NVPTX::StoreParamI32;
2991 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
2993 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_u32_u16, DL,
2994 MVT::i32, Ops[0], CvtNone);
2995 Ops[0] = SDValue(Cvt, 0);
2998 case NVPTXISD::StoreParamS32: {
2999 Opcode = NVPTX::StoreParamI32;
3000 SDValue CvtNone = CurDAG->getTargetConstant(NVPTX::PTXCvtMode::NONE,
3002 SDNode *Cvt = CurDAG->getMachineNode(NVPTX::CVT_s32_s16, DL,
3003 MVT::i32, Ops[0], CvtNone);
3004 Ops[0] = SDValue(Cvt, 0);
3009 SDVTList RetVTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
3011 CurDAG->getMachineNode(Opcode, DL, RetVTs, Ops);
3012 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
3013 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
3014 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1);
3019 SDNode *NVPTXDAGToDAGISel::SelectTextureIntrinsic(SDNode *N) {
3020 SDValue Chain = N->getOperand(0);
3021 SDNode *Ret = nullptr;
3023 SmallVector<SDValue, 8> Ops;
3025 switch (N->getOpcode()) {
3026 default: return nullptr;
3027 case NVPTXISD::Tex1DFloatS32:
3028 Opc = NVPTX::TEX_1D_F32_S32;
3030 case NVPTXISD::Tex1DFloatFloat:
3031 Opc = NVPTX::TEX_1D_F32_F32;
3033 case NVPTXISD::Tex1DFloatFloatLevel:
3034 Opc = NVPTX::TEX_1D_F32_F32_LEVEL;
3036 case NVPTXISD::Tex1DFloatFloatGrad:
3037 Opc = NVPTX::TEX_1D_F32_F32_GRAD;
3039 case NVPTXISD::Tex1DS32S32:
3040 Opc = NVPTX::TEX_1D_S32_S32;
3042 case NVPTXISD::Tex1DS32Float:
3043 Opc = NVPTX::TEX_1D_S32_F32;
3045 case NVPTXISD::Tex1DS32FloatLevel:
3046 Opc = NVPTX::TEX_1D_S32_F32_LEVEL;
3048 case NVPTXISD::Tex1DS32FloatGrad:
3049 Opc = NVPTX::TEX_1D_S32_F32_GRAD;
3051 case NVPTXISD::Tex1DU32S32:
3052 Opc = NVPTX::TEX_1D_U32_S32;
3054 case NVPTXISD::Tex1DU32Float:
3055 Opc = NVPTX::TEX_1D_U32_F32;
3057 case NVPTXISD::Tex1DU32FloatLevel:
3058 Opc = NVPTX::TEX_1D_U32_F32_LEVEL;
3060 case NVPTXISD::Tex1DU32FloatGrad:
3061 Opc = NVPTX::TEX_1D_U32_F32_GRAD;
3063 case NVPTXISD::Tex1DArrayFloatS32:
3064 Opc = NVPTX::TEX_1D_ARRAY_F32_S32;
3066 case NVPTXISD::Tex1DArrayFloatFloat:
3067 Opc = NVPTX::TEX_1D_ARRAY_F32_F32;
3069 case NVPTXISD::Tex1DArrayFloatFloatLevel:
3070 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL;
3072 case NVPTXISD::Tex1DArrayFloatFloatGrad:
3073 Opc = NVPTX::TEX_1D_ARRAY_F32_F32_GRAD;
3075 case NVPTXISD::Tex1DArrayS32S32:
3076 Opc = NVPTX::TEX_1D_ARRAY_S32_S32;
3078 case NVPTXISD::Tex1DArrayS32Float:
3079 Opc = NVPTX::TEX_1D_ARRAY_S32_F32;
3081 case NVPTXISD::Tex1DArrayS32FloatLevel:
3082 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL;
3084 case NVPTXISD::Tex1DArrayS32FloatGrad:
3085 Opc = NVPTX::TEX_1D_ARRAY_S32_F32_GRAD;
3087 case NVPTXISD::Tex1DArrayU32S32:
3088 Opc = NVPTX::TEX_1D_ARRAY_U32_S32;
3090 case NVPTXISD::Tex1DArrayU32Float:
3091 Opc = NVPTX::TEX_1D_ARRAY_U32_F32;
3093 case NVPTXISD::Tex1DArrayU32FloatLevel:
3094 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL;
3096 case NVPTXISD::Tex1DArrayU32FloatGrad:
3097 Opc = NVPTX::TEX_1D_ARRAY_U32_F32_GRAD;
3099 case NVPTXISD::Tex2DFloatS32:
3100 Opc = NVPTX::TEX_2D_F32_S32;
3102 case NVPTXISD::Tex2DFloatFloat:
3103 Opc = NVPTX::TEX_2D_F32_F32;
3105 case NVPTXISD::Tex2DFloatFloatLevel:
3106 Opc = NVPTX::TEX_2D_F32_F32_LEVEL;
3108 case NVPTXISD::Tex2DFloatFloatGrad:
3109 Opc = NVPTX::TEX_2D_F32_F32_GRAD;
3111 case NVPTXISD::Tex2DS32S32:
3112 Opc = NVPTX::TEX_2D_S32_S32;
3114 case NVPTXISD::Tex2DS32Float:
3115 Opc = NVPTX::TEX_2D_S32_F32;
3117 case NVPTXISD::Tex2DS32FloatLevel:
3118 Opc = NVPTX::TEX_2D_S32_F32_LEVEL;
3120 case NVPTXISD::Tex2DS32FloatGrad:
3121 Opc = NVPTX::TEX_2D_S32_F32_GRAD;
3123 case NVPTXISD::Tex2DU32S32:
3124 Opc = NVPTX::TEX_2D_U32_S32;
3126 case NVPTXISD::Tex2DU32Float:
3127 Opc = NVPTX::TEX_2D_U32_F32;
3129 case NVPTXISD::Tex2DU32FloatLevel:
3130 Opc = NVPTX::TEX_2D_U32_F32_LEVEL;
3132 case NVPTXISD::Tex2DU32FloatGrad:
3133 Opc = NVPTX::TEX_2D_U32_F32_GRAD;
3135 case NVPTXISD::Tex2DArrayFloatS32:
3136 Opc = NVPTX::TEX_2D_ARRAY_F32_S32;
3138 case NVPTXISD::Tex2DArrayFloatFloat:
3139 Opc = NVPTX::TEX_2D_ARRAY_F32_F32;
3141 case NVPTXISD::Tex2DArrayFloatFloatLevel:
3142 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL;
3144 case NVPTXISD::Tex2DArrayFloatFloatGrad:
3145 Opc = NVPTX::TEX_2D_ARRAY_F32_F32_GRAD;
3147 case NVPTXISD::Tex2DArrayS32S32:
3148 Opc = NVPTX::TEX_2D_ARRAY_S32_S32;
3150 case NVPTXISD::Tex2DArrayS32Float:
3151 Opc = NVPTX::TEX_2D_ARRAY_S32_F32;
3153 case NVPTXISD::Tex2DArrayS32FloatLevel:
3154 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL;
3156 case NVPTXISD::Tex2DArrayS32FloatGrad:
3157 Opc = NVPTX::TEX_2D_ARRAY_S32_F32_GRAD;
3159 case NVPTXISD::Tex2DArrayU32S32:
3160 Opc = NVPTX::TEX_2D_ARRAY_U32_S32;
3162 case NVPTXISD::Tex2DArrayU32Float:
3163 Opc = NVPTX::TEX_2D_ARRAY_U32_F32;
3165 case NVPTXISD::Tex2DArrayU32FloatLevel:
3166 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL;
3168 case NVPTXISD::Tex2DArrayU32FloatGrad:
3169 Opc = NVPTX::TEX_2D_ARRAY_U32_F32_GRAD;
3171 case NVPTXISD::Tex3DFloatS32:
3172 Opc = NVPTX::TEX_3D_F32_S32;
3174 case NVPTXISD::Tex3DFloatFloat:
3175 Opc = NVPTX::TEX_3D_F32_F32;
3177 case NVPTXISD::Tex3DFloatFloatLevel:
3178 Opc = NVPTX::TEX_3D_F32_F32_LEVEL;
3180 case NVPTXISD::Tex3DFloatFloatGrad:
3181 Opc = NVPTX::TEX_3D_F32_F32_GRAD;
3183 case NVPTXISD::Tex3DS32S32:
3184 Opc = NVPTX::TEX_3D_S32_S32;
3186 case NVPTXISD::Tex3DS32Float:
3187 Opc = NVPTX::TEX_3D_S32_F32;
3189 case NVPTXISD::Tex3DS32FloatLevel:
3190 Opc = NVPTX::TEX_3D_S32_F32_LEVEL;
3192 case NVPTXISD::Tex3DS32FloatGrad:
3193 Opc = NVPTX::TEX_3D_S32_F32_GRAD;
3195 case NVPTXISD::Tex3DU32S32:
3196 Opc = NVPTX::TEX_3D_U32_S32;
3198 case NVPTXISD::Tex3DU32Float:
3199 Opc = NVPTX::TEX_3D_U32_F32;
3201 case NVPTXISD::Tex3DU32FloatLevel:
3202 Opc = NVPTX::TEX_3D_U32_F32_LEVEL;
3204 case NVPTXISD::Tex3DU32FloatGrad:
3205 Opc = NVPTX::TEX_3D_U32_F32_GRAD;
3207 case NVPTXISD::TexCubeFloatFloat:
3208 Opc = NVPTX::TEX_CUBE_F32_F32;
3210 case NVPTXISD::TexCubeFloatFloatLevel:
3211 Opc = NVPTX::TEX_CUBE_F32_F32_LEVEL;
3213 case NVPTXISD::TexCubeS32Float:
3214 Opc = NVPTX::TEX_CUBE_S32_F32;
3216 case NVPTXISD::TexCubeS32FloatLevel:
3217 Opc = NVPTX::TEX_CUBE_S32_F32_LEVEL;
3219 case NVPTXISD::TexCubeU32Float:
3220 Opc = NVPTX::TEX_CUBE_U32_F32;
3222 case NVPTXISD::TexCubeU32FloatLevel:
3223 Opc = NVPTX::TEX_CUBE_U32_F32_LEVEL;
3225 case NVPTXISD::TexCubeArrayFloatFloat:
3226 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32;
3228 case NVPTXISD::TexCubeArrayFloatFloatLevel:
3229 Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL;
3231 case NVPTXISD::TexCubeArrayS32Float:
3232 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32;
3234 case NVPTXISD::TexCubeArrayS32FloatLevel:
3235 Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL;
3237 case NVPTXISD::TexCubeArrayU32Float:
3238 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32;
3240 case NVPTXISD::TexCubeArrayU32FloatLevel:
3241 Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL;
3243 case NVPTXISD::Tld4R2DFloatFloat:
3244 Opc = NVPTX::TLD4_R_2D_F32_F32;
3246 case NVPTXISD::Tld4G2DFloatFloat:
3247 Opc = NVPTX::TLD4_G_2D_F32_F32;
3249 case NVPTXISD::Tld4B2DFloatFloat:
3250 Opc = NVPTX::TLD4_B_2D_F32_F32;
3252 case NVPTXISD::Tld4A2DFloatFloat:
3253 Opc = NVPTX::TLD4_A_2D_F32_F32;
3255 case NVPTXISD::Tld4R2DS64Float:
3256 Opc = NVPTX::TLD4_R_2D_S32_F32;
3258 case NVPTXISD::Tld4G2DS64Float:
3259 Opc = NVPTX::TLD4_G_2D_S32_F32;
3261 case NVPTXISD::Tld4B2DS64Float:
3262 Opc = NVPTX::TLD4_B_2D_S32_F32;
3264 case NVPTXISD::Tld4A2DS64Float:
3265 Opc = NVPTX::TLD4_A_2D_S32_F32;
3267 case NVPTXISD::Tld4R2DU64Float:
3268 Opc = NVPTX::TLD4_R_2D_U32_F32;
3270 case NVPTXISD::Tld4G2DU64Float:
3271 Opc = NVPTX::TLD4_G_2D_U32_F32;
3273 case NVPTXISD::Tld4B2DU64Float:
3274 Opc = NVPTX::TLD4_B_2D_U32_F32;
3276 case NVPTXISD::Tld4A2DU64Float:
3277 Opc = NVPTX::TLD4_A_2D_U32_F32;
3279 case NVPTXISD::TexUnified1DFloatS32:
3280 Opc = NVPTX::TEX_UNIFIED_1D_F32_S32;
3282 case NVPTXISD::TexUnified1DFloatFloat:
3283 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32;
3285 case NVPTXISD::TexUnified1DFloatFloatLevel:
3286 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_LEVEL;
3288 case NVPTXISD::TexUnified1DFloatFloatGrad:
3289 Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_GRAD;
3291 case NVPTXISD::TexUnified1DS32S32:
3292 Opc = NVPTX::TEX_UNIFIED_1D_S32_S32;
3294 case NVPTXISD::TexUnified1DS32Float:
3295 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32;
3297 case NVPTXISD::TexUnified1DS32FloatLevel:
3298 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_LEVEL;
3300 case NVPTXISD::TexUnified1DS32FloatGrad:
3301 Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_GRAD;
3303 case NVPTXISD::TexUnified1DU32S32:
3304 Opc = NVPTX::TEX_UNIFIED_1D_U32_S32;
3306 case NVPTXISD::TexUnified1DU32Float:
3307 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32;
3309 case NVPTXISD::TexUnified1DU32FloatLevel:
3310 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_LEVEL;
3312 case NVPTXISD::TexUnified1DU32FloatGrad:
3313 Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_GRAD;
3315 case NVPTXISD::TexUnified1DArrayFloatS32:
3316 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_S32;
3318 case NVPTXISD::TexUnified1DArrayFloatFloat:
3319 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32;
3321 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
3322 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL;
3324 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
3325 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD;
3327 case NVPTXISD::TexUnified1DArrayS32S32:
3328 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_S32;
3330 case NVPTXISD::TexUnified1DArrayS32Float:
3331 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32;
3333 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
3334 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL;
3336 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
3337 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD;
3339 case NVPTXISD::TexUnified1DArrayU32S32:
3340 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_S32;
3342 case NVPTXISD::TexUnified1DArrayU32Float:
3343 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32;
3345 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
3346 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL;
3348 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
3349 Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD;
3351 case NVPTXISD::TexUnified2DFloatS32:
3352 Opc = NVPTX::TEX_UNIFIED_2D_F32_S32;
3354 case NVPTXISD::TexUnified2DFloatFloat:
3355 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32;
3357 case NVPTXISD::TexUnified2DFloatFloatLevel:
3358 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_LEVEL;
3360 case NVPTXISD::TexUnified2DFloatFloatGrad:
3361 Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_GRAD;
3363 case NVPTXISD::TexUnified2DS32S32:
3364 Opc = NVPTX::TEX_UNIFIED_2D_S32_S32;
3366 case NVPTXISD::TexUnified2DS32Float:
3367 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32;
3369 case NVPTXISD::TexUnified2DS32FloatLevel:
3370 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_LEVEL;
3372 case NVPTXISD::TexUnified2DS32FloatGrad:
3373 Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_GRAD;
3375 case NVPTXISD::TexUnified2DU32S32:
3376 Opc = NVPTX::TEX_UNIFIED_2D_U32_S32;
3378 case NVPTXISD::TexUnified2DU32Float:
3379 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32;
3381 case NVPTXISD::TexUnified2DU32FloatLevel:
3382 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_LEVEL;
3384 case NVPTXISD::TexUnified2DU32FloatGrad:
3385 Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_GRAD;
3387 case NVPTXISD::TexUnified2DArrayFloatS32:
3388 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_S32;
3390 case NVPTXISD::TexUnified2DArrayFloatFloat:
3391 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32;
3393 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
3394 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL;
3396 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
3397 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD;
3399 case NVPTXISD::TexUnified2DArrayS32S32:
3400 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_S32;
3402 case NVPTXISD::TexUnified2DArrayS32Float:
3403 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32;
3405 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
3406 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL;
3408 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
3409 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD;
3411 case NVPTXISD::TexUnified2DArrayU32S32:
3412 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_S32;
3414 case NVPTXISD::TexUnified2DArrayU32Float:
3415 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32;
3417 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
3418 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL;
3420 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
3421 Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD;
3423 case NVPTXISD::TexUnified3DFloatS32:
3424 Opc = NVPTX::TEX_UNIFIED_3D_F32_S32;
3426 case NVPTXISD::TexUnified3DFloatFloat:
3427 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32;
3429 case NVPTXISD::TexUnified3DFloatFloatLevel:
3430 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_LEVEL;
3432 case NVPTXISD::TexUnified3DFloatFloatGrad:
3433 Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_GRAD;
3435 case NVPTXISD::TexUnified3DS32S32:
3436 Opc = NVPTX::TEX_UNIFIED_3D_S32_S32;
3438 case NVPTXISD::TexUnified3DS32Float:
3439 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32;
3441 case NVPTXISD::TexUnified3DS32FloatLevel:
3442 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_LEVEL;
3444 case NVPTXISD::TexUnified3DS32FloatGrad:
3445 Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_GRAD;
3447 case NVPTXISD::TexUnified3DU32S32:
3448 Opc = NVPTX::TEX_UNIFIED_3D_U32_S32;
3450 case NVPTXISD::TexUnified3DU32Float:
3451 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32;
3453 case NVPTXISD::TexUnified3DU32FloatLevel:
3454 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_LEVEL;
3456 case NVPTXISD::TexUnified3DU32FloatGrad:
3457 Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_GRAD;
3459 case NVPTXISD::TexUnifiedCubeFloatFloat:
3460 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32;
3462 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
3463 Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32_LEVEL;
3465 case NVPTXISD::TexUnifiedCubeS32Float:
3466 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32;
3468 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
3469 Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32_LEVEL;
3471 case NVPTXISD::TexUnifiedCubeU32Float:
3472 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32;
3474 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
3475 Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32_LEVEL;
3477 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
3478 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32;
3480 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
3481 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL;
3483 case NVPTXISD::TexUnifiedCubeArrayS32Float:
3484 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32;
3486 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
3487 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL;
3489 case NVPTXISD::TexUnifiedCubeArrayU32Float:
3490 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32;
3492 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
3493 Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL;
3495 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
3496 Opc = NVPTX::TLD4_UNIFIED_R_2D_F32_F32;
3498 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
3499 Opc = NVPTX::TLD4_UNIFIED_G_2D_F32_F32;
3501 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
3502 Opc = NVPTX::TLD4_UNIFIED_B_2D_F32_F32;
3504 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
3505 Opc = NVPTX::TLD4_UNIFIED_A_2D_F32_F32;
3507 case NVPTXISD::Tld4UnifiedR2DS64Float:
3508 Opc = NVPTX::TLD4_UNIFIED_R_2D_S32_F32;
3510 case NVPTXISD::Tld4UnifiedG2DS64Float:
3511 Opc = NVPTX::TLD4_UNIFIED_G_2D_S32_F32;
3513 case NVPTXISD::Tld4UnifiedB2DS64Float:
3514 Opc = NVPTX::TLD4_UNIFIED_B_2D_S32_F32;
3516 case NVPTXISD::Tld4UnifiedA2DS64Float:
3517 Opc = NVPTX::TLD4_UNIFIED_A_2D_S32_F32;
3519 case NVPTXISD::Tld4UnifiedR2DU64Float:
3520 Opc = NVPTX::TLD4_UNIFIED_R_2D_U32_F32;
3522 case NVPTXISD::Tld4UnifiedG2DU64Float:
3523 Opc = NVPTX::TLD4_UNIFIED_G_2D_U32_F32;
3525 case NVPTXISD::Tld4UnifiedB2DU64Float:
3526 Opc = NVPTX::TLD4_UNIFIED_B_2D_U32_F32;
3528 case NVPTXISD::Tld4UnifiedA2DU64Float:
3529 Opc = NVPTX::TLD4_UNIFIED_A_2D_U32_F32;
3533 // Copy over operands
3534 for (unsigned i = 1; i < N->getNumOperands(); ++i) {
3535 Ops.push_back(N->getOperand(i));
3538 Ops.push_back(Chain);
3539 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
3543 SDNode *NVPTXDAGToDAGISel::SelectSurfaceIntrinsic(SDNode *N) {
3544 SDValue Chain = N->getOperand(0);
3545 SDValue TexHandle = N->getOperand(1);
3546 SDNode *Ret = nullptr;
3548 SmallVector<SDValue, 8> Ops;
3549 switch (N->getOpcode()) {
3550 default: return nullptr;
3551 case NVPTXISD::Suld1DI8Clamp:
3552 Opc = NVPTX::SULD_1D_I8_CLAMP;
3553 Ops.push_back(TexHandle);
3554 Ops.push_back(N->getOperand(2));
3555 Ops.push_back(Chain);
3557 case NVPTXISD::Suld1DI16Clamp:
3558 Opc = NVPTX::SULD_1D_I16_CLAMP;
3559 Ops.push_back(TexHandle);
3560 Ops.push_back(N->getOperand(2));
3561 Ops.push_back(Chain);
3563 case NVPTXISD::Suld1DI32Clamp:
3564 Opc = NVPTX::SULD_1D_I32_CLAMP;
3565 Ops.push_back(TexHandle);
3566 Ops.push_back(N->getOperand(2));
3567 Ops.push_back(Chain);
3569 case NVPTXISD::Suld1DI64Clamp:
3570 Opc = NVPTX::SULD_1D_I64_CLAMP;
3571 Ops.push_back(TexHandle);
3572 Ops.push_back(N->getOperand(2));
3573 Ops.push_back(Chain);
3575 case NVPTXISD::Suld1DV2I8Clamp:
3576 Opc = NVPTX::SULD_1D_V2I8_CLAMP;
3577 Ops.push_back(TexHandle);
3578 Ops.push_back(N->getOperand(2));
3579 Ops.push_back(Chain);
3581 case NVPTXISD::Suld1DV2I16Clamp:
3582 Opc = NVPTX::SULD_1D_V2I16_CLAMP;
3583 Ops.push_back(TexHandle);
3584 Ops.push_back(N->getOperand(2));
3585 Ops.push_back(Chain);
3587 case NVPTXISD::Suld1DV2I32Clamp:
3588 Opc = NVPTX::SULD_1D_V2I32_CLAMP;
3589 Ops.push_back(TexHandle);
3590 Ops.push_back(N->getOperand(2));
3591 Ops.push_back(Chain);
3593 case NVPTXISD::Suld1DV2I64Clamp:
3594 Opc = NVPTX::SULD_1D_V2I64_CLAMP;
3595 Ops.push_back(TexHandle);
3596 Ops.push_back(N->getOperand(2));
3597 Ops.push_back(Chain);
3599 case NVPTXISD::Suld1DV4I8Clamp:
3600 Opc = NVPTX::SULD_1D_V4I8_CLAMP;
3601 Ops.push_back(TexHandle);
3602 Ops.push_back(N->getOperand(2));
3603 Ops.push_back(Chain);
3605 case NVPTXISD::Suld1DV4I16Clamp:
3606 Opc = NVPTX::SULD_1D_V4I16_CLAMP;
3607 Ops.push_back(TexHandle);
3608 Ops.push_back(N->getOperand(2));
3609 Ops.push_back(Chain);
3611 case NVPTXISD::Suld1DV4I32Clamp:
3612 Opc = NVPTX::SULD_1D_V4I32_CLAMP;
3613 Ops.push_back(TexHandle);
3614 Ops.push_back(N->getOperand(2));
3615 Ops.push_back(Chain);
3617 case NVPTXISD::Suld1DArrayI8Clamp:
3618 Opc = NVPTX::SULD_1D_ARRAY_I8_CLAMP;
3619 Ops.push_back(TexHandle);
3620 Ops.push_back(N->getOperand(2));
3621 Ops.push_back(N->getOperand(3));
3622 Ops.push_back(Chain);
3624 case NVPTXISD::Suld1DArrayI16Clamp:
3625 Opc = NVPTX::SULD_1D_ARRAY_I16_CLAMP;
3626 Ops.push_back(TexHandle);
3627 Ops.push_back(N->getOperand(2));
3628 Ops.push_back(N->getOperand(3));
3629 Ops.push_back(Chain);
3631 case NVPTXISD::Suld1DArrayI32Clamp:
3632 Opc = NVPTX::SULD_1D_ARRAY_I32_CLAMP;
3633 Ops.push_back(TexHandle);
3634 Ops.push_back(N->getOperand(2));
3635 Ops.push_back(N->getOperand(3));
3636 Ops.push_back(Chain);
3638 case NVPTXISD::Suld1DArrayI64Clamp:
3639 Opc = NVPTX::SULD_1D_ARRAY_I64_CLAMP;
3640 Ops.push_back(TexHandle);
3641 Ops.push_back(N->getOperand(2));
3642 Ops.push_back(N->getOperand(3));
3643 Ops.push_back(Chain);
3645 case NVPTXISD::Suld1DArrayV2I8Clamp:
3646 Opc = NVPTX::SULD_1D_ARRAY_V2I8_CLAMP;
3647 Ops.push_back(TexHandle);
3648 Ops.push_back(N->getOperand(2));
3649 Ops.push_back(N->getOperand(3));
3650 Ops.push_back(Chain);
3652 case NVPTXISD::Suld1DArrayV2I16Clamp:
3653 Opc = NVPTX::SULD_1D_ARRAY_V2I16_CLAMP;
3654 Ops.push_back(TexHandle);
3655 Ops.push_back(N->getOperand(2));
3656 Ops.push_back(N->getOperand(3));
3657 Ops.push_back(Chain);
3659 case NVPTXISD::Suld1DArrayV2I32Clamp:
3660 Opc = NVPTX::SULD_1D_ARRAY_V2I32_CLAMP;
3661 Ops.push_back(TexHandle);
3662 Ops.push_back(N->getOperand(2));
3663 Ops.push_back(N->getOperand(3));
3664 Ops.push_back(Chain);
3666 case NVPTXISD::Suld1DArrayV2I64Clamp:
3667 Opc = NVPTX::SULD_1D_ARRAY_V2I64_CLAMP;
3668 Ops.push_back(TexHandle);
3669 Ops.push_back(N->getOperand(2));
3670 Ops.push_back(N->getOperand(3));
3671 Ops.push_back(Chain);
3673 case NVPTXISD::Suld1DArrayV4I8Clamp:
3674 Opc = NVPTX::SULD_1D_ARRAY_V4I8_CLAMP;
3675 Ops.push_back(TexHandle);
3676 Ops.push_back(N->getOperand(2));
3677 Ops.push_back(N->getOperand(3));
3678 Ops.push_back(Chain);
3680 case NVPTXISD::Suld1DArrayV4I16Clamp:
3681 Opc = NVPTX::SULD_1D_ARRAY_V4I16_CLAMP;
3682 Ops.push_back(TexHandle);
3683 Ops.push_back(N->getOperand(2));
3684 Ops.push_back(N->getOperand(3));
3685 Ops.push_back(Chain);
3687 case NVPTXISD::Suld1DArrayV4I32Clamp:
3688 Opc = NVPTX::SULD_1D_ARRAY_V4I32_CLAMP;
3689 Ops.push_back(TexHandle);
3690 Ops.push_back(N->getOperand(2));
3691 Ops.push_back(N->getOperand(3));
3692 Ops.push_back(Chain);
3694 case NVPTXISD::Suld2DI8Clamp:
3695 Opc = NVPTX::SULD_2D_I8_CLAMP;
3696 Ops.push_back(TexHandle);
3697 Ops.push_back(N->getOperand(2));
3698 Ops.push_back(N->getOperand(3));
3699 Ops.push_back(Chain);
3701 case NVPTXISD::Suld2DI16Clamp:
3702 Opc = NVPTX::SULD_2D_I16_CLAMP;
3703 Ops.push_back(TexHandle);
3704 Ops.push_back(N->getOperand(2));
3705 Ops.push_back(N->getOperand(3));
3706 Ops.push_back(Chain);
3708 case NVPTXISD::Suld2DI32Clamp:
3709 Opc = NVPTX::SULD_2D_I32_CLAMP;
3710 Ops.push_back(TexHandle);
3711 Ops.push_back(N->getOperand(2));
3712 Ops.push_back(N->getOperand(3));
3713 Ops.push_back(Chain);
3715 case NVPTXISD::Suld2DI64Clamp:
3716 Opc = NVPTX::SULD_2D_I64_CLAMP;
3717 Ops.push_back(TexHandle);
3718 Ops.push_back(N->getOperand(2));
3719 Ops.push_back(N->getOperand(3));
3720 Ops.push_back(Chain);
3722 case NVPTXISD::Suld2DV2I8Clamp:
3723 Opc = NVPTX::SULD_2D_V2I8_CLAMP;
3724 Ops.push_back(TexHandle);
3725 Ops.push_back(N->getOperand(2));
3726 Ops.push_back(N->getOperand(3));
3727 Ops.push_back(Chain);
3729 case NVPTXISD::Suld2DV2I16Clamp:
3730 Opc = NVPTX::SULD_2D_V2I16_CLAMP;
3731 Ops.push_back(TexHandle);
3732 Ops.push_back(N->getOperand(2));
3733 Ops.push_back(N->getOperand(3));
3734 Ops.push_back(Chain);
3736 case NVPTXISD::Suld2DV2I32Clamp:
3737 Opc = NVPTX::SULD_2D_V2I32_CLAMP;
3738 Ops.push_back(TexHandle);
3739 Ops.push_back(N->getOperand(2));
3740 Ops.push_back(N->getOperand(3));
3741 Ops.push_back(Chain);
3743 case NVPTXISD::Suld2DV2I64Clamp:
3744 Opc = NVPTX::SULD_2D_V2I64_CLAMP;
3745 Ops.push_back(TexHandle);
3746 Ops.push_back(N->getOperand(2));
3747 Ops.push_back(N->getOperand(3));
3748 Ops.push_back(Chain);
3750 case NVPTXISD::Suld2DV4I8Clamp:
3751 Opc = NVPTX::SULD_2D_V4I8_CLAMP;
3752 Ops.push_back(TexHandle);
3753 Ops.push_back(N->getOperand(2));
3754 Ops.push_back(N->getOperand(3));
3755 Ops.push_back(Chain);
3757 case NVPTXISD::Suld2DV4I16Clamp:
3758 Opc = NVPTX::SULD_2D_V4I16_CLAMP;
3759 Ops.push_back(TexHandle);
3760 Ops.push_back(N->getOperand(2));
3761 Ops.push_back(N->getOperand(3));
3762 Ops.push_back(Chain);
3764 case NVPTXISD::Suld2DV4I32Clamp:
3765 Opc = NVPTX::SULD_2D_V4I32_CLAMP;
3766 Ops.push_back(TexHandle);
3767 Ops.push_back(N->getOperand(2));
3768 Ops.push_back(N->getOperand(3));
3769 Ops.push_back(Chain);
3771 case NVPTXISD::Suld2DArrayI8Clamp:
3772 Opc = NVPTX::SULD_2D_ARRAY_I8_CLAMP;
3773 Ops.push_back(TexHandle);
3774 Ops.push_back(N->getOperand(2));
3775 Ops.push_back(N->getOperand(3));
3776 Ops.push_back(N->getOperand(4));
3777 Ops.push_back(Chain);
3779 case NVPTXISD::Suld2DArrayI16Clamp:
3780 Opc = NVPTX::SULD_2D_ARRAY_I16_CLAMP;
3781 Ops.push_back(TexHandle);
3782 Ops.push_back(N->getOperand(2));
3783 Ops.push_back(N->getOperand(3));
3784 Ops.push_back(N->getOperand(4));
3785 Ops.push_back(Chain);
3787 case NVPTXISD::Suld2DArrayI32Clamp:
3788 Opc = NVPTX::SULD_2D_ARRAY_I32_CLAMP;
3789 Ops.push_back(TexHandle);
3790 Ops.push_back(N->getOperand(2));
3791 Ops.push_back(N->getOperand(3));
3792 Ops.push_back(N->getOperand(4));
3793 Ops.push_back(Chain);
3795 case NVPTXISD::Suld2DArrayI64Clamp:
3796 Opc = NVPTX::SULD_2D_ARRAY_I64_CLAMP;
3797 Ops.push_back(TexHandle);
3798 Ops.push_back(N->getOperand(2));
3799 Ops.push_back(N->getOperand(3));
3800 Ops.push_back(N->getOperand(4));
3801 Ops.push_back(Chain);
3803 case NVPTXISD::Suld2DArrayV2I8Clamp:
3804 Opc = NVPTX::SULD_2D_ARRAY_V2I8_CLAMP;
3805 Ops.push_back(TexHandle);
3806 Ops.push_back(N->getOperand(2));
3807 Ops.push_back(N->getOperand(3));
3808 Ops.push_back(N->getOperand(4));
3809 Ops.push_back(Chain);
3811 case NVPTXISD::Suld2DArrayV2I16Clamp:
3812 Opc = NVPTX::SULD_2D_ARRAY_V2I16_CLAMP;
3813 Ops.push_back(TexHandle);
3814 Ops.push_back(N->getOperand(2));
3815 Ops.push_back(N->getOperand(3));
3816 Ops.push_back(N->getOperand(4));
3817 Ops.push_back(Chain);
3819 case NVPTXISD::Suld2DArrayV2I32Clamp:
3820 Opc = NVPTX::SULD_2D_ARRAY_V2I32_CLAMP;
3821 Ops.push_back(TexHandle);
3822 Ops.push_back(N->getOperand(2));
3823 Ops.push_back(N->getOperand(3));
3824 Ops.push_back(N->getOperand(4));
3825 Ops.push_back(Chain);
3827 case NVPTXISD::Suld2DArrayV2I64Clamp:
3828 Opc = NVPTX::SULD_2D_ARRAY_V2I64_CLAMP;
3829 Ops.push_back(TexHandle);
3830 Ops.push_back(N->getOperand(2));
3831 Ops.push_back(N->getOperand(3));
3832 Ops.push_back(N->getOperand(4));
3833 Ops.push_back(Chain);
3835 case NVPTXISD::Suld2DArrayV4I8Clamp:
3836 Opc = NVPTX::SULD_2D_ARRAY_V4I8_CLAMP;
3837 Ops.push_back(TexHandle);
3838 Ops.push_back(N->getOperand(2));
3839 Ops.push_back(N->getOperand(3));
3840 Ops.push_back(N->getOperand(4));
3841 Ops.push_back(Chain);
3843 case NVPTXISD::Suld2DArrayV4I16Clamp:
3844 Opc = NVPTX::SULD_2D_ARRAY_V4I16_CLAMP;
3845 Ops.push_back(TexHandle);
3846 Ops.push_back(N->getOperand(2));
3847 Ops.push_back(N->getOperand(3));
3848 Ops.push_back(N->getOperand(4));
3849 Ops.push_back(Chain);
3851 case NVPTXISD::Suld2DArrayV4I32Clamp:
3852 Opc = NVPTX::SULD_2D_ARRAY_V4I32_CLAMP;
3853 Ops.push_back(TexHandle);
3854 Ops.push_back(N->getOperand(2));
3855 Ops.push_back(N->getOperand(3));
3856 Ops.push_back(N->getOperand(4));
3857 Ops.push_back(Chain);
3859 case NVPTXISD::Suld3DI8Clamp:
3860 Opc = NVPTX::SULD_3D_I8_CLAMP;
3861 Ops.push_back(TexHandle);
3862 Ops.push_back(N->getOperand(2));
3863 Ops.push_back(N->getOperand(3));
3864 Ops.push_back(N->getOperand(4));
3865 Ops.push_back(Chain);
3867 case NVPTXISD::Suld3DI16Clamp:
3868 Opc = NVPTX::SULD_3D_I16_CLAMP;
3869 Ops.push_back(TexHandle);
3870 Ops.push_back(N->getOperand(2));
3871 Ops.push_back(N->getOperand(3));
3872 Ops.push_back(N->getOperand(4));
3873 Ops.push_back(Chain);
3875 case NVPTXISD::Suld3DI32Clamp:
3876 Opc = NVPTX::SULD_3D_I32_CLAMP;
3877 Ops.push_back(TexHandle);
3878 Ops.push_back(N->getOperand(2));
3879 Ops.push_back(N->getOperand(3));
3880 Ops.push_back(N->getOperand(4));
3881 Ops.push_back(Chain);
3883 case NVPTXISD::Suld3DI64Clamp:
3884 Opc = NVPTX::SULD_3D_I64_CLAMP;
3885 Ops.push_back(TexHandle);
3886 Ops.push_back(N->getOperand(2));
3887 Ops.push_back(N->getOperand(3));
3888 Ops.push_back(N->getOperand(4));
3889 Ops.push_back(Chain);
3891 case NVPTXISD::Suld3DV2I8Clamp:
3892 Opc = NVPTX::SULD_3D_V2I8_CLAMP;
3893 Ops.push_back(TexHandle);
3894 Ops.push_back(N->getOperand(2));
3895 Ops.push_back(N->getOperand(3));
3896 Ops.push_back(N->getOperand(4));
3897 Ops.push_back(Chain);
3899 case NVPTXISD::Suld3DV2I16Clamp:
3900 Opc = NVPTX::SULD_3D_V2I16_CLAMP;
3901 Ops.push_back(TexHandle);
3902 Ops.push_back(N->getOperand(2));
3903 Ops.push_back(N->getOperand(3));
3904 Ops.push_back(N->getOperand(4));
3905 Ops.push_back(Chain);
3907 case NVPTXISD::Suld3DV2I32Clamp:
3908 Opc = NVPTX::SULD_3D_V2I32_CLAMP;
3909 Ops.push_back(TexHandle);
3910 Ops.push_back(N->getOperand(2));
3911 Ops.push_back(N->getOperand(3));
3912 Ops.push_back(N->getOperand(4));
3913 Ops.push_back(Chain);
3915 case NVPTXISD::Suld3DV2I64Clamp:
3916 Opc = NVPTX::SULD_3D_V2I64_CLAMP;
3917 Ops.push_back(TexHandle);
3918 Ops.push_back(N->getOperand(2));
3919 Ops.push_back(N->getOperand(3));
3920 Ops.push_back(N->getOperand(4));
3921 Ops.push_back(Chain);
3923 case NVPTXISD::Suld3DV4I8Clamp:
3924 Opc = NVPTX::SULD_3D_V4I8_CLAMP;
3925 Ops.push_back(TexHandle);
3926 Ops.push_back(N->getOperand(2));
3927 Ops.push_back(N->getOperand(3));
3928 Ops.push_back(N->getOperand(4));
3929 Ops.push_back(Chain);
3931 case NVPTXISD::Suld3DV4I16Clamp:
3932 Opc = NVPTX::SULD_3D_V4I16_CLAMP;
3933 Ops.push_back(TexHandle);
3934 Ops.push_back(N->getOperand(2));
3935 Ops.push_back(N->getOperand(3));
3936 Ops.push_back(N->getOperand(4));
3937 Ops.push_back(Chain);
3939 case NVPTXISD::Suld3DV4I32Clamp:
3940 Opc = NVPTX::SULD_3D_V4I32_CLAMP;
3941 Ops.push_back(TexHandle);
3942 Ops.push_back(N->getOperand(2));
3943 Ops.push_back(N->getOperand(3));
3944 Ops.push_back(N->getOperand(4));
3945 Ops.push_back(Chain);
3947 case NVPTXISD::Suld1DI8Trap:
3948 Opc = NVPTX::SULD_1D_I8_TRAP;
3949 Ops.push_back(TexHandle);
3950 Ops.push_back(N->getOperand(2));
3951 Ops.push_back(Chain);
3953 case NVPTXISD::Suld1DI16Trap:
3954 Opc = NVPTX::SULD_1D_I16_TRAP;
3955 Ops.push_back(TexHandle);
3956 Ops.push_back(N->getOperand(2));
3957 Ops.push_back(Chain);
3959 case NVPTXISD::Suld1DI32Trap:
3960 Opc = NVPTX::SULD_1D_I32_TRAP;
3961 Ops.push_back(TexHandle);
3962 Ops.push_back(N->getOperand(2));
3963 Ops.push_back(Chain);
3965 case NVPTXISD::Suld1DI64Trap:
3966 Opc = NVPTX::SULD_1D_I64_TRAP;
3967 Ops.push_back(TexHandle);
3968 Ops.push_back(N->getOperand(2));
3969 Ops.push_back(Chain);
3971 case NVPTXISD::Suld1DV2I8Trap:
3972 Opc = NVPTX::SULD_1D_V2I8_TRAP;
3973 Ops.push_back(TexHandle);
3974 Ops.push_back(N->getOperand(2));
3975 Ops.push_back(Chain);
3977 case NVPTXISD::Suld1DV2I16Trap:
3978 Opc = NVPTX::SULD_1D_V2I16_TRAP;
3979 Ops.push_back(TexHandle);
3980 Ops.push_back(N->getOperand(2));
3981 Ops.push_back(Chain);
3983 case NVPTXISD::Suld1DV2I32Trap:
3984 Opc = NVPTX::SULD_1D_V2I32_TRAP;
3985 Ops.push_back(TexHandle);
3986 Ops.push_back(N->getOperand(2));
3987 Ops.push_back(Chain);
3989 case NVPTXISD::Suld1DV2I64Trap:
3990 Opc = NVPTX::SULD_1D_V2I64_TRAP;
3991 Ops.push_back(TexHandle);
3992 Ops.push_back(N->getOperand(2));
3993 Ops.push_back(Chain);
3995 case NVPTXISD::Suld1DV4I8Trap:
3996 Opc = NVPTX::SULD_1D_V4I8_TRAP;
3997 Ops.push_back(TexHandle);
3998 Ops.push_back(N->getOperand(2));
3999 Ops.push_back(Chain);
4001 case NVPTXISD::Suld1DV4I16Trap:
4002 Opc = NVPTX::SULD_1D_V4I16_TRAP;
4003 Ops.push_back(TexHandle);
4004 Ops.push_back(N->getOperand(2));
4005 Ops.push_back(Chain);
4007 case NVPTXISD::Suld1DV4I32Trap:
4008 Opc = NVPTX::SULD_1D_V4I32_TRAP;
4009 Ops.push_back(TexHandle);
4010 Ops.push_back(N->getOperand(2));
4011 Ops.push_back(Chain);
4013 case NVPTXISD::Suld1DArrayI8Trap:
4014 Opc = NVPTX::SULD_1D_ARRAY_I8_TRAP;
4015 Ops.push_back(TexHandle);
4016 Ops.push_back(N->getOperand(2));
4017 Ops.push_back(N->getOperand(3));
4018 Ops.push_back(Chain);
4020 case NVPTXISD::Suld1DArrayI16Trap:
4021 Opc = NVPTX::SULD_1D_ARRAY_I16_TRAP;
4022 Ops.push_back(TexHandle);
4023 Ops.push_back(N->getOperand(2));
4024 Ops.push_back(N->getOperand(3));
4025 Ops.push_back(Chain);
4027 case NVPTXISD::Suld1DArrayI32Trap:
4028 Opc = NVPTX::SULD_1D_ARRAY_I32_TRAP;
4029 Ops.push_back(TexHandle);
4030 Ops.push_back(N->getOperand(2));
4031 Ops.push_back(N->getOperand(3));
4032 Ops.push_back(Chain);
4034 case NVPTXISD::Suld1DArrayI64Trap:
4035 Opc = NVPTX::SULD_1D_ARRAY_I64_TRAP;
4036 Ops.push_back(TexHandle);
4037 Ops.push_back(N->getOperand(2));
4038 Ops.push_back(N->getOperand(3));
4039 Ops.push_back(Chain);
4041 case NVPTXISD::Suld1DArrayV2I8Trap:
4042 Opc = NVPTX::SULD_1D_ARRAY_V2I8_TRAP;
4043 Ops.push_back(TexHandle);
4044 Ops.push_back(N->getOperand(2));
4045 Ops.push_back(N->getOperand(3));
4046 Ops.push_back(Chain);
4048 case NVPTXISD::Suld1DArrayV2I16Trap:
4049 Opc = NVPTX::SULD_1D_ARRAY_V2I16_TRAP;
4050 Ops.push_back(TexHandle);
4051 Ops.push_back(N->getOperand(2));
4052 Ops.push_back(N->getOperand(3));
4053 Ops.push_back(Chain);
4055 case NVPTXISD::Suld1DArrayV2I32Trap:
4056 Opc = NVPTX::SULD_1D_ARRAY_V2I32_TRAP;
4057 Ops.push_back(TexHandle);
4058 Ops.push_back(N->getOperand(2));
4059 Ops.push_back(N->getOperand(3));
4060 Ops.push_back(Chain);
4062 case NVPTXISD::Suld1DArrayV2I64Trap:
4063 Opc = NVPTX::SULD_1D_ARRAY_V2I64_TRAP;
4064 Ops.push_back(TexHandle);
4065 Ops.push_back(N->getOperand(2));
4066 Ops.push_back(N->getOperand(3));
4067 Ops.push_back(Chain);
4069 case NVPTXISD::Suld1DArrayV4I8Trap:
4070 Opc = NVPTX::SULD_1D_ARRAY_V4I8_TRAP;
4071 Ops.push_back(TexHandle);
4072 Ops.push_back(N->getOperand(2));
4073 Ops.push_back(N->getOperand(3));
4074 Ops.push_back(Chain);
4076 case NVPTXISD::Suld1DArrayV4I16Trap:
4077 Opc = NVPTX::SULD_1D_ARRAY_V4I16_TRAP;
4078 Ops.push_back(TexHandle);
4079 Ops.push_back(N->getOperand(2));
4080 Ops.push_back(N->getOperand(3));
4081 Ops.push_back(Chain);
4083 case NVPTXISD::Suld1DArrayV4I32Trap:
4084 Opc = NVPTX::SULD_1D_ARRAY_V4I32_TRAP;
4085 Ops.push_back(TexHandle);
4086 Ops.push_back(N->getOperand(2));
4087 Ops.push_back(N->getOperand(3));
4088 Ops.push_back(Chain);
4090 case NVPTXISD::Suld2DI8Trap:
4091 Opc = NVPTX::SULD_2D_I8_TRAP;
4092 Ops.push_back(TexHandle);
4093 Ops.push_back(N->getOperand(2));
4094 Ops.push_back(N->getOperand(3));
4095 Ops.push_back(Chain);
4097 case NVPTXISD::Suld2DI16Trap:
4098 Opc = NVPTX::SULD_2D_I16_TRAP;
4099 Ops.push_back(TexHandle);
4100 Ops.push_back(N->getOperand(2));
4101 Ops.push_back(N->getOperand(3));
4102 Ops.push_back(Chain);
4104 case NVPTXISD::Suld2DI32Trap:
4105 Opc = NVPTX::SULD_2D_I32_TRAP;
4106 Ops.push_back(TexHandle);
4107 Ops.push_back(N->getOperand(2));
4108 Ops.push_back(N->getOperand(3));
4109 Ops.push_back(Chain);
4111 case NVPTXISD::Suld2DI64Trap:
4112 Opc = NVPTX::SULD_2D_I64_TRAP;
4113 Ops.push_back(TexHandle);
4114 Ops.push_back(N->getOperand(2));
4115 Ops.push_back(N->getOperand(3));
4116 Ops.push_back(Chain);
4118 case NVPTXISD::Suld2DV2I8Trap:
4119 Opc = NVPTX::SULD_2D_V2I8_TRAP;
4120 Ops.push_back(TexHandle);
4121 Ops.push_back(N->getOperand(2));
4122 Ops.push_back(N->getOperand(3));
4123 Ops.push_back(Chain);
4125 case NVPTXISD::Suld2DV2I16Trap:
4126 Opc = NVPTX::SULD_2D_V2I16_TRAP;
4127 Ops.push_back(TexHandle);
4128 Ops.push_back(N->getOperand(2));
4129 Ops.push_back(N->getOperand(3));
4130 Ops.push_back(Chain);
4132 case NVPTXISD::Suld2DV2I32Trap:
4133 Opc = NVPTX::SULD_2D_V2I32_TRAP;
4134 Ops.push_back(TexHandle);
4135 Ops.push_back(N->getOperand(2));
4136 Ops.push_back(N->getOperand(3));
4137 Ops.push_back(Chain);
4139 case NVPTXISD::Suld2DV2I64Trap:
4140 Opc = NVPTX::SULD_2D_V2I64_TRAP;
4141 Ops.push_back(TexHandle);
4142 Ops.push_back(N->getOperand(2));
4143 Ops.push_back(N->getOperand(3));
4144 Ops.push_back(Chain);
4146 case NVPTXISD::Suld2DV4I8Trap:
4147 Opc = NVPTX::SULD_2D_V4I8_TRAP;
4148 Ops.push_back(TexHandle);
4149 Ops.push_back(N->getOperand(2));
4150 Ops.push_back(N->getOperand(3));
4151 Ops.push_back(Chain);
4153 case NVPTXISD::Suld2DV4I16Trap:
4154 Opc = NVPTX::SULD_2D_V4I16_TRAP;
4155 Ops.push_back(TexHandle);
4156 Ops.push_back(N->getOperand(2));
4157 Ops.push_back(N->getOperand(3));
4158 Ops.push_back(Chain);
4160 case NVPTXISD::Suld2DV4I32Trap:
4161 Opc = NVPTX::SULD_2D_V4I32_TRAP;
4162 Ops.push_back(TexHandle);
4163 Ops.push_back(N->getOperand(2));
4164 Ops.push_back(N->getOperand(3));
4165 Ops.push_back(Chain);
4167 case NVPTXISD::Suld2DArrayI8Trap:
4168 Opc = NVPTX::SULD_2D_ARRAY_I8_TRAP;
4169 Ops.push_back(TexHandle);
4170 Ops.push_back(N->getOperand(2));
4171 Ops.push_back(N->getOperand(3));
4172 Ops.push_back(N->getOperand(4));
4173 Ops.push_back(Chain);
4175 case NVPTXISD::Suld2DArrayI16Trap:
4176 Opc = NVPTX::SULD_2D_ARRAY_I16_TRAP;
4177 Ops.push_back(TexHandle);
4178 Ops.push_back(N->getOperand(2));
4179 Ops.push_back(N->getOperand(3));
4180 Ops.push_back(N->getOperand(4));
4181 Ops.push_back(Chain);
4183 case NVPTXISD::Suld2DArrayI32Trap:
4184 Opc = NVPTX::SULD_2D_ARRAY_I32_TRAP;
4185 Ops.push_back(TexHandle);
4186 Ops.push_back(N->getOperand(2));
4187 Ops.push_back(N->getOperand(3));
4188 Ops.push_back(N->getOperand(4));
4189 Ops.push_back(Chain);
4191 case NVPTXISD::Suld2DArrayI64Trap:
4192 Opc = NVPTX::SULD_2D_ARRAY_I64_TRAP;
4193 Ops.push_back(TexHandle);
4194 Ops.push_back(N->getOperand(2));
4195 Ops.push_back(N->getOperand(3));
4196 Ops.push_back(N->getOperand(4));
4197 Ops.push_back(Chain);
4199 case NVPTXISD::Suld2DArrayV2I8Trap:
4200 Opc = NVPTX::SULD_2D_ARRAY_V2I8_TRAP;
4201 Ops.push_back(TexHandle);
4202 Ops.push_back(N->getOperand(2));
4203 Ops.push_back(N->getOperand(3));
4204 Ops.push_back(N->getOperand(4));
4205 Ops.push_back(Chain);
4207 case NVPTXISD::Suld2DArrayV2I16Trap:
4208 Opc = NVPTX::SULD_2D_ARRAY_V2I16_TRAP;
4209 Ops.push_back(TexHandle);
4210 Ops.push_back(N->getOperand(2));
4211 Ops.push_back(N->getOperand(3));
4212 Ops.push_back(N->getOperand(4));
4213 Ops.push_back(Chain);
4215 case NVPTXISD::Suld2DArrayV2I32Trap:
4216 Opc = NVPTX::SULD_2D_ARRAY_V2I32_TRAP;
4217 Ops.push_back(TexHandle);
4218 Ops.push_back(N->getOperand(2));
4219 Ops.push_back(N->getOperand(3));
4220 Ops.push_back(N->getOperand(4));
4221 Ops.push_back(Chain);
4223 case NVPTXISD::Suld2DArrayV2I64Trap:
4224 Opc = NVPTX::SULD_2D_ARRAY_V2I64_TRAP;
4225 Ops.push_back(TexHandle);
4226 Ops.push_back(N->getOperand(2));
4227 Ops.push_back(N->getOperand(3));
4228 Ops.push_back(N->getOperand(4));
4229 Ops.push_back(Chain);
4231 case NVPTXISD::Suld2DArrayV4I8Trap:
4232 Opc = NVPTX::SULD_2D_ARRAY_V4I8_TRAP;
4233 Ops.push_back(TexHandle);
4234 Ops.push_back(N->getOperand(2));
4235 Ops.push_back(N->getOperand(3));
4236 Ops.push_back(N->getOperand(4));
4237 Ops.push_back(Chain);
4239 case NVPTXISD::Suld2DArrayV4I16Trap:
4240 Opc = NVPTX::SULD_2D_ARRAY_V4I16_TRAP;
4241 Ops.push_back(TexHandle);
4242 Ops.push_back(N->getOperand(2));
4243 Ops.push_back(N->getOperand(3));
4244 Ops.push_back(N->getOperand(4));
4245 Ops.push_back(Chain);
4247 case NVPTXISD::Suld2DArrayV4I32Trap:
4248 Opc = NVPTX::SULD_2D_ARRAY_V4I32_TRAP;
4249 Ops.push_back(TexHandle);
4250 Ops.push_back(N->getOperand(2));
4251 Ops.push_back(N->getOperand(3));
4252 Ops.push_back(N->getOperand(4));
4253 Ops.push_back(Chain);
4255 case NVPTXISD::Suld3DI8Trap:
4256 Opc = NVPTX::SULD_3D_I8_TRAP;
4257 Ops.push_back(TexHandle);
4258 Ops.push_back(N->getOperand(2));
4259 Ops.push_back(N->getOperand(3));
4260 Ops.push_back(N->getOperand(4));
4261 Ops.push_back(Chain);
4263 case NVPTXISD::Suld3DI16Trap:
4264 Opc = NVPTX::SULD_3D_I16_TRAP;
4265 Ops.push_back(TexHandle);
4266 Ops.push_back(N->getOperand(2));
4267 Ops.push_back(N->getOperand(3));
4268 Ops.push_back(N->getOperand(4));
4269 Ops.push_back(Chain);
4271 case NVPTXISD::Suld3DI32Trap:
4272 Opc = NVPTX::SULD_3D_I32_TRAP;
4273 Ops.push_back(TexHandle);
4274 Ops.push_back(N->getOperand(2));
4275 Ops.push_back(N->getOperand(3));
4276 Ops.push_back(N->getOperand(4));
4277 Ops.push_back(Chain);
4279 case NVPTXISD::Suld3DI64Trap:
4280 Opc = NVPTX::SULD_3D_I64_TRAP;
4281 Ops.push_back(TexHandle);
4282 Ops.push_back(N->getOperand(2));
4283 Ops.push_back(N->getOperand(3));
4284 Ops.push_back(N->getOperand(4));
4285 Ops.push_back(Chain);
4287 case NVPTXISD::Suld3DV2I8Trap:
4288 Opc = NVPTX::SULD_3D_V2I8_TRAP;
4289 Ops.push_back(TexHandle);
4290 Ops.push_back(N->getOperand(2));
4291 Ops.push_back(N->getOperand(3));
4292 Ops.push_back(N->getOperand(4));
4293 Ops.push_back(Chain);
4295 case NVPTXISD::Suld3DV2I16Trap:
4296 Opc = NVPTX::SULD_3D_V2I16_TRAP;
4297 Ops.push_back(TexHandle);
4298 Ops.push_back(N->getOperand(2));
4299 Ops.push_back(N->getOperand(3));
4300 Ops.push_back(N->getOperand(4));
4301 Ops.push_back(Chain);
4303 case NVPTXISD::Suld3DV2I32Trap:
4304 Opc = NVPTX::SULD_3D_V2I32_TRAP;
4305 Ops.push_back(TexHandle);
4306 Ops.push_back(N->getOperand(2));
4307 Ops.push_back(N->getOperand(3));
4308 Ops.push_back(N->getOperand(4));
4309 Ops.push_back(Chain);
4311 case NVPTXISD::Suld3DV2I64Trap:
4312 Opc = NVPTX::SULD_3D_V2I64_TRAP;
4313 Ops.push_back(TexHandle);
4314 Ops.push_back(N->getOperand(2));
4315 Ops.push_back(N->getOperand(3));
4316 Ops.push_back(N->getOperand(4));
4317 Ops.push_back(Chain);
4319 case NVPTXISD::Suld3DV4I8Trap:
4320 Opc = NVPTX::SULD_3D_V4I8_TRAP;
4321 Ops.push_back(TexHandle);
4322 Ops.push_back(N->getOperand(2));
4323 Ops.push_back(N->getOperand(3));
4324 Ops.push_back(N->getOperand(4));
4325 Ops.push_back(Chain);
4327 case NVPTXISD::Suld3DV4I16Trap:
4328 Opc = NVPTX::SULD_3D_V4I16_TRAP;
4329 Ops.push_back(TexHandle);
4330 Ops.push_back(N->getOperand(2));
4331 Ops.push_back(N->getOperand(3));
4332 Ops.push_back(N->getOperand(4));
4333 Ops.push_back(Chain);
4335 case NVPTXISD::Suld3DV4I32Trap:
4336 Opc = NVPTX::SULD_3D_V4I32_TRAP;
4337 Ops.push_back(TexHandle);
4338 Ops.push_back(N->getOperand(2));
4339 Ops.push_back(N->getOperand(3));
4340 Ops.push_back(N->getOperand(4));
4341 Ops.push_back(Chain);
4343 case NVPTXISD::Suld1DI8Zero:
4344 Opc = NVPTX::SULD_1D_I8_ZERO;
4345 Ops.push_back(TexHandle);
4346 Ops.push_back(N->getOperand(2));
4347 Ops.push_back(Chain);
4349 case NVPTXISD::Suld1DI16Zero:
4350 Opc = NVPTX::SULD_1D_I16_ZERO;
4351 Ops.push_back(TexHandle);
4352 Ops.push_back(N->getOperand(2));
4353 Ops.push_back(Chain);
4355 case NVPTXISD::Suld1DI32Zero:
4356 Opc = NVPTX::SULD_1D_I32_ZERO;
4357 Ops.push_back(TexHandle);
4358 Ops.push_back(N->getOperand(2));
4359 Ops.push_back(Chain);
4361 case NVPTXISD::Suld1DI64Zero:
4362 Opc = NVPTX::SULD_1D_I64_ZERO;
4363 Ops.push_back(TexHandle);
4364 Ops.push_back(N->getOperand(2));
4365 Ops.push_back(Chain);
4367 case NVPTXISD::Suld1DV2I8Zero:
4368 Opc = NVPTX::SULD_1D_V2I8_ZERO;
4369 Ops.push_back(TexHandle);
4370 Ops.push_back(N->getOperand(2));
4371 Ops.push_back(Chain);
4373 case NVPTXISD::Suld1DV2I16Zero:
4374 Opc = NVPTX::SULD_1D_V2I16_ZERO;
4375 Ops.push_back(TexHandle);
4376 Ops.push_back(N->getOperand(2));
4377 Ops.push_back(Chain);
4379 case NVPTXISD::Suld1DV2I32Zero:
4380 Opc = NVPTX::SULD_1D_V2I32_ZERO;
4381 Ops.push_back(TexHandle);
4382 Ops.push_back(N->getOperand(2));
4383 Ops.push_back(Chain);
4385 case NVPTXISD::Suld1DV2I64Zero:
4386 Opc = NVPTX::SULD_1D_V2I64_ZERO;
4387 Ops.push_back(TexHandle);
4388 Ops.push_back(N->getOperand(2));
4389 Ops.push_back(Chain);
4391 case NVPTXISD::Suld1DV4I8Zero:
4392 Opc = NVPTX::SULD_1D_V4I8_ZERO;
4393 Ops.push_back(TexHandle);
4394 Ops.push_back(N->getOperand(2));
4395 Ops.push_back(Chain);
4397 case NVPTXISD::Suld1DV4I16Zero:
4398 Opc = NVPTX::SULD_1D_V4I16_ZERO;
4399 Ops.push_back(TexHandle);
4400 Ops.push_back(N->getOperand(2));
4401 Ops.push_back(Chain);
4403 case NVPTXISD::Suld1DV4I32Zero:
4404 Opc = NVPTX::SULD_1D_V4I32_ZERO;
4405 Ops.push_back(TexHandle);
4406 Ops.push_back(N->getOperand(2));
4407 Ops.push_back(Chain);
4409 case NVPTXISD::Suld1DArrayI8Zero:
4410 Opc = NVPTX::SULD_1D_ARRAY_I8_ZERO;
4411 Ops.push_back(TexHandle);
4412 Ops.push_back(N->getOperand(2));
4413 Ops.push_back(N->getOperand(3));
4414 Ops.push_back(Chain);
4416 case NVPTXISD::Suld1DArrayI16Zero:
4417 Opc = NVPTX::SULD_1D_ARRAY_I16_ZERO;
4418 Ops.push_back(TexHandle);
4419 Ops.push_back(N->getOperand(2));
4420 Ops.push_back(N->getOperand(3));
4421 Ops.push_back(Chain);
4423 case NVPTXISD::Suld1DArrayI32Zero:
4424 Opc = NVPTX::SULD_1D_ARRAY_I32_ZERO;
4425 Ops.push_back(TexHandle);
4426 Ops.push_back(N->getOperand(2));
4427 Ops.push_back(N->getOperand(3));
4428 Ops.push_back(Chain);
4430 case NVPTXISD::Suld1DArrayI64Zero:
4431 Opc = NVPTX::SULD_1D_ARRAY_I64_ZERO;
4432 Ops.push_back(TexHandle);
4433 Ops.push_back(N->getOperand(2));
4434 Ops.push_back(N->getOperand(3));
4435 Ops.push_back(Chain);
4437 case NVPTXISD::Suld1DArrayV2I8Zero:
4438 Opc = NVPTX::SULD_1D_ARRAY_V2I8_ZERO;
4439 Ops.push_back(TexHandle);
4440 Ops.push_back(N->getOperand(2));
4441 Ops.push_back(N->getOperand(3));
4442 Ops.push_back(Chain);
4444 case NVPTXISD::Suld1DArrayV2I16Zero:
4445 Opc = NVPTX::SULD_1D_ARRAY_V2I16_ZERO;
4446 Ops.push_back(TexHandle);
4447 Ops.push_back(N->getOperand(2));
4448 Ops.push_back(N->getOperand(3));
4449 Ops.push_back(Chain);
4451 case NVPTXISD::Suld1DArrayV2I32Zero:
4452 Opc = NVPTX::SULD_1D_ARRAY_V2I32_ZERO;
4453 Ops.push_back(TexHandle);
4454 Ops.push_back(N->getOperand(2));
4455 Ops.push_back(N->getOperand(3));
4456 Ops.push_back(Chain);
4458 case NVPTXISD::Suld1DArrayV2I64Zero:
4459 Opc = NVPTX::SULD_1D_ARRAY_V2I64_ZERO;
4460 Ops.push_back(TexHandle);
4461 Ops.push_back(N->getOperand(2));
4462 Ops.push_back(N->getOperand(3));
4463 Ops.push_back(Chain);
4465 case NVPTXISD::Suld1DArrayV4I8Zero:
4466 Opc = NVPTX::SULD_1D_ARRAY_V4I8_ZERO;
4467 Ops.push_back(TexHandle);
4468 Ops.push_back(N->getOperand(2));
4469 Ops.push_back(N->getOperand(3));
4470 Ops.push_back(Chain);
4472 case NVPTXISD::Suld1DArrayV4I16Zero:
4473 Opc = NVPTX::SULD_1D_ARRAY_V4I16_ZERO;
4474 Ops.push_back(TexHandle);
4475 Ops.push_back(N->getOperand(2));
4476 Ops.push_back(N->getOperand(3));
4477 Ops.push_back(Chain);
4479 case NVPTXISD::Suld1DArrayV4I32Zero:
4480 Opc = NVPTX::SULD_1D_ARRAY_V4I32_ZERO;
4481 Ops.push_back(TexHandle);
4482 Ops.push_back(N->getOperand(2));
4483 Ops.push_back(N->getOperand(3));
4484 Ops.push_back(Chain);
4486 case NVPTXISD::Suld2DI8Zero:
4487 Opc = NVPTX::SULD_2D_I8_ZERO;
4488 Ops.push_back(TexHandle);
4489 Ops.push_back(N->getOperand(2));
4490 Ops.push_back(N->getOperand(3));
4491 Ops.push_back(Chain);
4493 case NVPTXISD::Suld2DI16Zero:
4494 Opc = NVPTX::SULD_2D_I16_ZERO;
4495 Ops.push_back(TexHandle);
4496 Ops.push_back(N->getOperand(2));
4497 Ops.push_back(N->getOperand(3));
4498 Ops.push_back(Chain);
4500 case NVPTXISD::Suld2DI32Zero:
4501 Opc = NVPTX::SULD_2D_I32_ZERO;
4502 Ops.push_back(TexHandle);
4503 Ops.push_back(N->getOperand(2));
4504 Ops.push_back(N->getOperand(3));
4505 Ops.push_back(Chain);
4507 case NVPTXISD::Suld2DI64Zero:
4508 Opc = NVPTX::SULD_2D_I64_ZERO;
4509 Ops.push_back(TexHandle);
4510 Ops.push_back(N->getOperand(2));
4511 Ops.push_back(N->getOperand(3));
4512 Ops.push_back(Chain);
4514 case NVPTXISD::Suld2DV2I8Zero:
4515 Opc = NVPTX::SULD_2D_V2I8_ZERO;
4516 Ops.push_back(TexHandle);
4517 Ops.push_back(N->getOperand(2));
4518 Ops.push_back(N->getOperand(3));
4519 Ops.push_back(Chain);
4521 case NVPTXISD::Suld2DV2I16Zero:
4522 Opc = NVPTX::SULD_2D_V2I16_ZERO;
4523 Ops.push_back(TexHandle);
4524 Ops.push_back(N->getOperand(2));
4525 Ops.push_back(N->getOperand(3));
4526 Ops.push_back(Chain);
4528 case NVPTXISD::Suld2DV2I32Zero:
4529 Opc = NVPTX::SULD_2D_V2I32_ZERO;
4530 Ops.push_back(TexHandle);
4531 Ops.push_back(N->getOperand(2));
4532 Ops.push_back(N->getOperand(3));
4533 Ops.push_back(Chain);
4535 case NVPTXISD::Suld2DV2I64Zero:
4536 Opc = NVPTX::SULD_2D_V2I64_ZERO;
4537 Ops.push_back(TexHandle);
4538 Ops.push_back(N->getOperand(2));
4539 Ops.push_back(N->getOperand(3));
4540 Ops.push_back(Chain);
4542 case NVPTXISD::Suld2DV4I8Zero:
4543 Opc = NVPTX::SULD_2D_V4I8_ZERO;
4544 Ops.push_back(TexHandle);
4545 Ops.push_back(N->getOperand(2));
4546 Ops.push_back(N->getOperand(3));
4547 Ops.push_back(Chain);
4549 case NVPTXISD::Suld2DV4I16Zero:
4550 Opc = NVPTX::SULD_2D_V4I16_ZERO;
4551 Ops.push_back(TexHandle);
4552 Ops.push_back(N->getOperand(2));
4553 Ops.push_back(N->getOperand(3));
4554 Ops.push_back(Chain);
4556 case NVPTXISD::Suld2DV4I32Zero:
4557 Opc = NVPTX::SULD_2D_V4I32_ZERO;
4558 Ops.push_back(TexHandle);
4559 Ops.push_back(N->getOperand(2));
4560 Ops.push_back(N->getOperand(3));
4561 Ops.push_back(Chain);
4563 case NVPTXISD::Suld2DArrayI8Zero:
4564 Opc = NVPTX::SULD_2D_ARRAY_I8_ZERO;
4565 Ops.push_back(TexHandle);
4566 Ops.push_back(N->getOperand(2));
4567 Ops.push_back(N->getOperand(3));
4568 Ops.push_back(N->getOperand(4));
4569 Ops.push_back(Chain);
4571 case NVPTXISD::Suld2DArrayI16Zero:
4572 Opc = NVPTX::SULD_2D_ARRAY_I16_ZERO;
4573 Ops.push_back(TexHandle);
4574 Ops.push_back(N->getOperand(2));
4575 Ops.push_back(N->getOperand(3));
4576 Ops.push_back(N->getOperand(4));
4577 Ops.push_back(Chain);
4579 case NVPTXISD::Suld2DArrayI32Zero:
4580 Opc = NVPTX::SULD_2D_ARRAY_I32_ZERO;
4581 Ops.push_back(TexHandle);
4582 Ops.push_back(N->getOperand(2));
4583 Ops.push_back(N->getOperand(3));
4584 Ops.push_back(N->getOperand(4));
4585 Ops.push_back(Chain);
4587 case NVPTXISD::Suld2DArrayI64Zero:
4588 Opc = NVPTX::SULD_2D_ARRAY_I64_ZERO;
4589 Ops.push_back(TexHandle);
4590 Ops.push_back(N->getOperand(2));
4591 Ops.push_back(N->getOperand(3));
4592 Ops.push_back(N->getOperand(4));
4593 Ops.push_back(Chain);
4595 case NVPTXISD::Suld2DArrayV2I8Zero:
4596 Opc = NVPTX::SULD_2D_ARRAY_V2I8_ZERO;
4597 Ops.push_back(TexHandle);
4598 Ops.push_back(N->getOperand(2));
4599 Ops.push_back(N->getOperand(3));
4600 Ops.push_back(N->getOperand(4));
4601 Ops.push_back(Chain);
4603 case NVPTXISD::Suld2DArrayV2I16Zero:
4604 Opc = NVPTX::SULD_2D_ARRAY_V2I16_ZERO;
4605 Ops.push_back(TexHandle);
4606 Ops.push_back(N->getOperand(2));
4607 Ops.push_back(N->getOperand(3));
4608 Ops.push_back(N->getOperand(4));
4609 Ops.push_back(Chain);
4611 case NVPTXISD::Suld2DArrayV2I32Zero:
4612 Opc = NVPTX::SULD_2D_ARRAY_V2I32_ZERO;
4613 Ops.push_back(TexHandle);
4614 Ops.push_back(N->getOperand(2));
4615 Ops.push_back(N->getOperand(3));
4616 Ops.push_back(N->getOperand(4));
4617 Ops.push_back(Chain);
4619 case NVPTXISD::Suld2DArrayV2I64Zero:
4620 Opc = NVPTX::SULD_2D_ARRAY_V2I64_ZERO;
4621 Ops.push_back(TexHandle);
4622 Ops.push_back(N->getOperand(2));
4623 Ops.push_back(N->getOperand(3));
4624 Ops.push_back(N->getOperand(4));
4625 Ops.push_back(Chain);
4627 case NVPTXISD::Suld2DArrayV4I8Zero:
4628 Opc = NVPTX::SULD_2D_ARRAY_V4I8_ZERO;
4629 Ops.push_back(TexHandle);
4630 Ops.push_back(N->getOperand(2));
4631 Ops.push_back(N->getOperand(3));
4632 Ops.push_back(N->getOperand(4));
4633 Ops.push_back(Chain);
4635 case NVPTXISD::Suld2DArrayV4I16Zero:
4636 Opc = NVPTX::SULD_2D_ARRAY_V4I16_ZERO;
4637 Ops.push_back(TexHandle);
4638 Ops.push_back(N->getOperand(2));
4639 Ops.push_back(N->getOperand(3));
4640 Ops.push_back(N->getOperand(4));
4641 Ops.push_back(Chain);
4643 case NVPTXISD::Suld2DArrayV4I32Zero:
4644 Opc = NVPTX::SULD_2D_ARRAY_V4I32_ZERO;
4645 Ops.push_back(TexHandle);
4646 Ops.push_back(N->getOperand(2));
4647 Ops.push_back(N->getOperand(3));
4648 Ops.push_back(N->getOperand(4));
4649 Ops.push_back(Chain);
4651 case NVPTXISD::Suld3DI8Zero:
4652 Opc = NVPTX::SULD_3D_I8_ZERO;
4653 Ops.push_back(TexHandle);
4654 Ops.push_back(N->getOperand(2));
4655 Ops.push_back(N->getOperand(3));
4656 Ops.push_back(N->getOperand(4));
4657 Ops.push_back(Chain);
4659 case NVPTXISD::Suld3DI16Zero:
4660 Opc = NVPTX::SULD_3D_I16_ZERO;
4661 Ops.push_back(TexHandle);
4662 Ops.push_back(N->getOperand(2));
4663 Ops.push_back(N->getOperand(3));
4664 Ops.push_back(N->getOperand(4));
4665 Ops.push_back(Chain);
4667 case NVPTXISD::Suld3DI32Zero:
4668 Opc = NVPTX::SULD_3D_I32_ZERO;
4669 Ops.push_back(TexHandle);
4670 Ops.push_back(N->getOperand(2));
4671 Ops.push_back(N->getOperand(3));
4672 Ops.push_back(N->getOperand(4));
4673 Ops.push_back(Chain);
4675 case NVPTXISD::Suld3DI64Zero:
4676 Opc = NVPTX::SULD_3D_I64_ZERO;
4677 Ops.push_back(TexHandle);
4678 Ops.push_back(N->getOperand(2));
4679 Ops.push_back(N->getOperand(3));
4680 Ops.push_back(N->getOperand(4));
4681 Ops.push_back(Chain);
4683 case NVPTXISD::Suld3DV2I8Zero:
4684 Opc = NVPTX::SULD_3D_V2I8_ZERO;
4685 Ops.push_back(TexHandle);
4686 Ops.push_back(N->getOperand(2));
4687 Ops.push_back(N->getOperand(3));
4688 Ops.push_back(N->getOperand(4));
4689 Ops.push_back(Chain);
4691 case NVPTXISD::Suld3DV2I16Zero:
4692 Opc = NVPTX::SULD_3D_V2I16_ZERO;
4693 Ops.push_back(TexHandle);
4694 Ops.push_back(N->getOperand(2));
4695 Ops.push_back(N->getOperand(3));
4696 Ops.push_back(N->getOperand(4));
4697 Ops.push_back(Chain);
4699 case NVPTXISD::Suld3DV2I32Zero:
4700 Opc = NVPTX::SULD_3D_V2I32_ZERO;
4701 Ops.push_back(TexHandle);
4702 Ops.push_back(N->getOperand(2));
4703 Ops.push_back(N->getOperand(3));
4704 Ops.push_back(N->getOperand(4));
4705 Ops.push_back(Chain);
4707 case NVPTXISD::Suld3DV2I64Zero:
4708 Opc = NVPTX::SULD_3D_V2I64_ZERO;
4709 Ops.push_back(TexHandle);
4710 Ops.push_back(N->getOperand(2));
4711 Ops.push_back(N->getOperand(3));
4712 Ops.push_back(N->getOperand(4));
4713 Ops.push_back(Chain);
4715 case NVPTXISD::Suld3DV4I8Zero:
4716 Opc = NVPTX::SULD_3D_V4I8_ZERO;
4717 Ops.push_back(TexHandle);
4718 Ops.push_back(N->getOperand(2));
4719 Ops.push_back(N->getOperand(3));
4720 Ops.push_back(N->getOperand(4));
4721 Ops.push_back(Chain);
4723 case NVPTXISD::Suld3DV4I16Zero:
4724 Opc = NVPTX::SULD_3D_V4I16_ZERO;
4725 Ops.push_back(TexHandle);
4726 Ops.push_back(N->getOperand(2));
4727 Ops.push_back(N->getOperand(3));
4728 Ops.push_back(N->getOperand(4));
4729 Ops.push_back(Chain);
4731 case NVPTXISD::Suld3DV4I32Zero:
4732 Opc = NVPTX::SULD_3D_V4I32_ZERO;
4733 Ops.push_back(TexHandle);
4734 Ops.push_back(N->getOperand(2));
4735 Ops.push_back(N->getOperand(3));
4736 Ops.push_back(N->getOperand(4));
4737 Ops.push_back(Chain);
4740 Ret = CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
4745 /// SelectBFE - Look for instruction sequences that can be made more efficient
4746 /// by using the 'bfe' (bit-field extract) PTX instruction
4747 SDNode *NVPTXDAGToDAGISel::SelectBFE(SDNode *N) {
4748 SDValue LHS = N->getOperand(0);
4749 SDValue RHS = N->getOperand(1);
4753 bool IsSigned = false;
4755 if (N->getOpcode() == ISD::AND) {
4756 // Canonicalize the operands
4757 // We want 'and %val, %mask'
4758 if (isa<ConstantSDNode>(LHS) && !isa<ConstantSDNode>(RHS)) {
4759 std::swap(LHS, RHS);
4762 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(RHS);
4764 // We need a constant mask on the RHS of the AND
4768 // Extract the mask bits
4769 uint64_t MaskVal = Mask->getZExtValue();
4770 if (!isMask_64(MaskVal)) {
4771 // We *could* handle shifted masks here, but doing so would require an
4772 // 'and' operation to fix up the low-order bits so we would trade
4773 // shr+and for bfe+and, which has the same throughput
4777 // How many bits are in our mask?
4778 uint64_t NumBits = countTrailingOnes(MaskVal);
4779 Len = CurDAG->getTargetConstant(NumBits, MVT::i32);
4781 if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) {
4782 // We have a 'srl/and' pair, extract the effective start bit and length
4783 Val = LHS.getNode()->getOperand(0);
4784 Start = LHS.getNode()->getOperand(1);
4785 ConstantSDNode *StartConst = dyn_cast<ConstantSDNode>(Start);
4787 uint64_t StartVal = StartConst->getZExtValue();
4788 // How many "good" bits do we have left? "good" is defined here as bits
4789 // that exist in the original value, not shifted in.
4790 uint64_t GoodBits = Start.getValueType().getSizeInBits() - StartVal;
4791 if (NumBits > GoodBits) {
4792 // Do not handle the case where bits have been shifted in. In theory
4793 // we could handle this, but the cost is likely higher than just
4794 // emitting the srl/and pair.
4797 Start = CurDAG->getTargetConstant(StartVal, MVT::i32);
4799 // Do not handle the case where the shift amount (can be zero if no srl
4800 // was found) is not constant. We could handle this case, but it would
4801 // require run-time logic that would be more expensive than just
4802 // emitting the srl/and pair.
4806 // Do not handle the case where the LHS of the and is not a shift. While
4807 // it would be trivial to handle this case, it would just transform
4808 // 'and' -> 'bfe', but 'and' has higher-throughput.
4811 } else if (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) {
4812 if (LHS->getOpcode() == ISD::AND) {
4813 ConstantSDNode *ShiftCnst = dyn_cast<ConstantSDNode>(RHS);
4815 // Shift amount must be constant
4819 uint64_t ShiftAmt = ShiftCnst->getZExtValue();
4821 SDValue AndLHS = LHS->getOperand(0);
4822 SDValue AndRHS = LHS->getOperand(1);
4824 // Canonicalize the AND to have the mask on the RHS
4825 if (isa<ConstantSDNode>(AndLHS)) {
4826 std::swap(AndLHS, AndRHS);
4829 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(AndRHS);
4831 // Mask must be constant
4835 uint64_t MaskVal = MaskCnst->getZExtValue();
4838 if (isMask_64(MaskVal)) {
4840 // The number of bits in the result bitfield will be the number of
4841 // trailing ones (the AND) minus the number of bits we shift off
4842 NumBits = countTrailingOnes(MaskVal) - ShiftAmt;
4843 } else if (isShiftedMask_64(MaskVal)) {
4844 NumZeros = countTrailingZeros(MaskVal);
4845 unsigned NumOnes = countTrailingOnes(MaskVal >> NumZeros);
4846 // The number of bits in the result bitfield will be the number of
4847 // trailing zeros plus the number of set bits in the mask minus the
4848 // number of bits we shift off
4849 NumBits = NumZeros + NumOnes - ShiftAmt;
4851 // This is not a mask we can handle
4855 if (ShiftAmt < NumZeros) {
4856 // Handling this case would require extra logic that would make this
4857 // transformation non-profitable
4862 Start = CurDAG->getTargetConstant(ShiftAmt, MVT::i32);
4863 Len = CurDAG->getTargetConstant(NumBits, MVT::i32);
4864 } else if (LHS->getOpcode() == ISD::SHL) {
4865 // Here, we have a pattern like:
4867 // (sra (shl val, NN), MM)
4869 // (srl (shl val, NN), MM)
4871 // If MM >= NN, we can efficiently optimize this with bfe
4872 Val = LHS->getOperand(0);
4874 SDValue ShlRHS = LHS->getOperand(1);
4875 ConstantSDNode *ShlCnst = dyn_cast<ConstantSDNode>(ShlRHS);
4877 // Shift amount must be constant
4880 uint64_t InnerShiftAmt = ShlCnst->getZExtValue();
4882 SDValue ShrRHS = RHS;
4883 ConstantSDNode *ShrCnst = dyn_cast<ConstantSDNode>(ShrRHS);
4885 // Shift amount must be constant
4888 uint64_t OuterShiftAmt = ShrCnst->getZExtValue();
4890 // To avoid extra codegen and be profitable, we need Outer >= Inner
4891 if (OuterShiftAmt < InnerShiftAmt) {
4895 // If the outer shift is more than the type size, we have no bitfield to
4896 // extract (since we also check that the inner shift is <= the outer shift
4897 // then this also implies that the inner shift is < the type size)
4898 if (OuterShiftAmt >= Val.getValueType().getSizeInBits()) {
4903 CurDAG->getTargetConstant(OuterShiftAmt - InnerShiftAmt, MVT::i32);
4905 CurDAG->getTargetConstant(Val.getValueType().getSizeInBits() -
4906 OuterShiftAmt, MVT::i32);
4908 if (N->getOpcode() == ISD::SRA) {
4909 // If we have a arithmetic right shift, we need to use the signed bfe
4924 // For the BFE operations we form here from "and" and "srl", always use the
4925 // unsigned variants.
4926 if (Val.getValueType() == MVT::i32) {
4928 Opc = NVPTX::BFE_S32rii;
4930 Opc = NVPTX::BFE_U32rii;
4932 } else if (Val.getValueType() == MVT::i64) {
4934 Opc = NVPTX::BFE_S64rii;
4936 Opc = NVPTX::BFE_U64rii;
4939 // We cannot handle this type
4948 CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
4953 // SelectDirectAddr - Match a direct address for DAG.
4954 // A direct address could be a globaladdress or externalsymbol.
4955 bool NVPTXDAGToDAGISel::SelectDirectAddr(SDValue N, SDValue &Address) {
4956 // Return true if TGA or ES.
4957 if (N.getOpcode() == ISD::TargetGlobalAddress ||
4958 N.getOpcode() == ISD::TargetExternalSymbol) {
4962 if (N.getOpcode() == NVPTXISD::Wrapper) {
4963 Address = N.getOperand(0);
4966 if (N.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
4967 unsigned IID = cast<ConstantSDNode>(N.getOperand(0))->getZExtValue();
4968 if (IID == Intrinsic::nvvm_ptr_gen_to_param)
4969 if (N.getOperand(1).getOpcode() == NVPTXISD::MoveParam)
4970 return (SelectDirectAddr(N.getOperand(1).getOperand(0), Address));
4976 bool NVPTXDAGToDAGISel::SelectADDRsi_imp(
4977 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
4978 if (Addr.getOpcode() == ISD::ADD) {
4979 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
4980 SDValue base = Addr.getOperand(0);
4981 if (SelectDirectAddr(base, Base)) {
4982 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
4991 bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr,
4992 SDValue &Base, SDValue &Offset) {
4993 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32);
4997 bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr,
4998 SDValue &Base, SDValue &Offset) {
4999 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64);
5003 bool NVPTXDAGToDAGISel::SelectADDRri_imp(
5004 SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
5005 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
5006 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
5007 Offset = CurDAG->getTargetConstant(0, mvt);
5010 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
5011 Addr.getOpcode() == ISD::TargetGlobalAddress)
5012 return false; // direct calls.
5014 if (Addr.getOpcode() == ISD::ADD) {
5015 if (SelectDirectAddr(Addr.getOperand(0), Addr)) {
5018 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
5019 if (FrameIndexSDNode *FIN =
5020 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
5021 // Constant offset from frame ref.
5022 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
5024 Base = Addr.getOperand(0);
5025 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
5033 bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr,
5034 SDValue &Base, SDValue &Offset) {
5035 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32);
5039 bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr,
5040 SDValue &Base, SDValue &Offset) {
5041 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64);
5044 bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
5045 unsigned int spN) const {
5046 const Value *Src = nullptr;
5047 if (MemSDNode *mN = dyn_cast<MemSDNode>(N)) {
5048 if (spN == 0 && mN->getMemOperand()->getPseudoValue())
5050 Src = mN->getMemOperand()->getValue();
5054 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
5055 return (PT->getAddressSpace() == spN);
5059 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
5060 /// inline asm expressions.
5061 bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(
5062 const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
5064 switch (ConstraintCode) {
5068 if (SelectDirectAddr(Op, Op0)) {
5069 OutOps.push_back(Op0);
5070 OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
5073 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
5074 OutOps.push_back(Op0);
5075 OutOps.push_back(Op1);