1 //===-- NVPTXISelDAGToDAG.h - A dag to dag inst selector for NVPTX --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "nvptx-isel"
17 #include "NVPTXISelLowering.h"
18 #include "NVPTXRegisterInfo.h"
19 #include "NVPTXTargetMachine.h"
20 #include "llvm/CodeGen/SelectionDAGISel.h"
21 #include "llvm/IR/Intrinsics.h"
22 #include "llvm/Support/Compiler.h"
27 class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
29 // If true, generate corresponding FPCONTRACT. This is
30 // language dependent (i.e. CUDA and OpenCL works differently).
40 // 2: For sm_20 and later, ieee-compliant div.rnd.f32 can be generated;
41 // Otherwise, use div.full
44 // If true, generate sqrt.rn, else generate sqrt.approx. If FTZ
45 // is true, then generate the corresponding FTZ version.
48 // If true, add .ftz to f32 instructions.
49 // This is only meaningful for sm_20 and later, as the default
51 // For sm earlier than sm_20, f32 denorms are always ftz by the
53 // We always add the .ftz modifier regardless of the sm value
54 // when Use32FTZ is true.
57 // If true, generate mul.wide from sext and mul
61 explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
62 CodeGenOpt::Level OptLevel);
65 virtual const char *getPassName() const {
66 return "NVPTX DAG->DAG Pattern Instruction Selection";
69 const NVPTXSubtarget &Subtarget;
71 virtual bool SelectInlineAsmMemoryOperand(
72 const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps);
74 // Include the pieces autogenerated from the target description.
75 #include "NVPTXGenDAGISel.inc"
77 SDNode *Select(SDNode *N);
78 SDNode *SelectLoad(SDNode *N);
79 SDNode *SelectLoadVector(SDNode *N);
80 SDNode *SelectLDGLDUVector(SDNode *N);
81 SDNode *SelectStore(SDNode *N);
82 SDNode *SelectStoreVector(SDNode *N);
83 SDNode *SelectLoadParam(SDNode *N);
84 SDNode *SelectStoreRetval(SDNode *N);
85 SDNode *SelectStoreParam(SDNode *N);
87 inline SDValue getI32Imm(unsigned Imm) {
88 return CurDAG->getTargetConstant(Imm, MVT::i32);
91 // Match direct address complex pattern.
92 bool SelectDirectAddr(SDValue N, SDValue &Address);
94 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
95 SDValue &Offset, MVT mvt);
96 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
98 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
101 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
102 SDValue &Offset, MVT mvt);
103 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
105 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
108 bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const;
110 bool UndefOrImm(SDValue Op, SDValue N, SDValue &Retval);