1 //===-- NVPTXISelDAGToDAG.h - A dag to dag inst selector for NVPTX --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "nvptx-isel"
17 #include "NVPTXISelLowering.h"
18 #include "NVPTXRegisterInfo.h"
19 #include "NVPTXTargetMachine.h"
20 #include "llvm/CodeGen/SelectionDAGISel.h"
21 #include "llvm/IR/Intrinsics.h"
22 #include "llvm/Support/Compiler.h"
27 class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
29 // If true, generate corresponding FPCONTRACT. This is
30 // language dependent (i.e. CUDA and OpenCL works differently).
40 // 2: For sm_20 and later, ieee-compliant div.rnd.f32 can be generated;
41 // Otherwise, use div.full
44 // If true, add .ftz to f32 instructions.
45 // This is only meaningful for sm_20 and later, as the default
47 // For sm earlier than sm_20, f32 denorms are always ftz by the
49 // We always add the .ftz modifier regardless of the sm value
50 // when Use32FTZ is true.
53 // If true, generate mul.wide from sext and mul
57 explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
58 CodeGenOpt::Level OptLevel);
61 virtual const char *getPassName() const {
62 return "NVPTX DAG->DAG Pattern Instruction Selection";
65 const NVPTXSubtarget &Subtarget;
67 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
69 std::vector<SDValue> &OutOps);
71 // Include the pieces autogenerated from the target description.
72 #include "NVPTXGenDAGISel.inc"
74 SDNode *Select(SDNode *N);
75 SDNode *SelectLoad(SDNode *N);
76 SDNode *SelectLoadVector(SDNode *N);
77 SDNode *SelectLDGLDUVector(SDNode *N);
78 SDNode *SelectStore(SDNode *N);
79 SDNode *SelectStoreVector(SDNode *N);
81 inline SDValue getI32Imm(unsigned Imm) {
82 return CurDAG->getTargetConstant(Imm, MVT::i32);
85 // Match direct address complex pattern.
86 bool SelectDirectAddr(SDValue N, SDValue &Address);
88 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 SDValue &Offset, MVT mvt);
90 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
92 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
95 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
96 SDValue &Offset, MVT mvt);
97 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
99 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
103 bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const;
105 bool UndefOrImm(SDValue Op, SDValue N, SDValue &Retval);