2 // The LLVM Compiler Infrastructure
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXISelLowering.h"
16 #include "NVPTXTargetMachine.h"
17 #include "NVPTXTargetObjectFile.h"
18 #include "NVPTXUtilities.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
25 #include "llvm/IR/CallSite.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/IntrinsicInst.h"
30 #include "llvm/IR/Intrinsics.h"
31 #include "llvm/IR/Module.h"
32 #include "llvm/MC/MCSectionELF.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
41 #define DEBUG_TYPE "nvptx-lower"
45 static unsigned int uniqueCallSite = 0;
47 static cl::opt<bool> sched4reg(
49 cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
51 static cl::opt<unsigned>
52 FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
53 cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
54 " 1: do it 2: do it aggressively"),
57 static bool IsPTXVectorType(MVT VT) {
58 switch (VT.SimpleTy) {
77 /// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
78 /// EVTs that compose it. Unlike ComputeValueVTs, this will break apart vectors
79 /// into their primitive components.
80 /// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
81 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
82 /// LowerCall, and LowerReturn.
83 static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL,
84 Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
85 SmallVectorImpl<uint64_t> *Offsets = nullptr,
86 uint64_t StartingOffset = 0) {
87 SmallVector<EVT, 16> TempVTs;
88 SmallVector<uint64_t, 16> TempOffsets;
90 ComputeValueVTs(TLI, DL, Ty, TempVTs, &TempOffsets, StartingOffset);
91 for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
93 uint64_t Off = TempOffsets[i];
95 for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
96 ValueVTs.push_back(VT.getVectorElementType());
98 Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
101 ValueVTs.push_back(VT);
103 Offsets->push_back(Off);
108 // NVPTXTargetLowering Constructor.
109 NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
110 const NVPTXSubtarget &STI)
111 : TargetLowering(TM), nvTM(&TM), STI(STI) {
113 // always lower memset, memcpy, and memmove intrinsics to load/store
114 // instructions, rather
115 // then generating calls to memset, mempcy or memmove.
116 MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
117 MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
118 MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
120 setBooleanContents(ZeroOrNegativeOneBooleanContent);
121 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
123 // Jump is Expensive. Don't create extra control flow for 'and', 'or'
124 // condition branches.
125 setJumpIsExpensive(true);
127 // Wide divides are _very_ slow. Try to reduce the width of the divide if
129 addBypassSlowDiv(64, 32);
131 // By default, use the Source scheduling
133 setSchedulingPreference(Sched::RegPressure);
135 setSchedulingPreference(Sched::Source);
137 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
138 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
139 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
140 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
141 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
142 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
144 // Operations not directly supported by NVPTX.
145 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
146 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
147 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
148 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
149 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
150 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
151 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
152 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
153 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
154 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
155 setOperationAction(ISD::BR_CC, MVT::i8, Expand);
156 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
157 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
158 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
159 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
160 // For others we will expand to a SHL/SRA pair.
161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
162 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
163 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
164 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
167 setOperationAction(ISD::SHL_PARTS, MVT::i32 , Custom);
168 setOperationAction(ISD::SRA_PARTS, MVT::i32 , Custom);
169 setOperationAction(ISD::SRL_PARTS, MVT::i32 , Custom);
170 setOperationAction(ISD::SHL_PARTS, MVT::i64 , Custom);
171 setOperationAction(ISD::SRA_PARTS, MVT::i64 , Custom);
172 setOperationAction(ISD::SRL_PARTS, MVT::i64 , Custom);
174 if (STI.hasROT64()) {
175 setOperationAction(ISD::ROTL, MVT::i64, Legal);
176 setOperationAction(ISD::ROTR, MVT::i64, Legal);
178 setOperationAction(ISD::ROTL, MVT::i64, Expand);
179 setOperationAction(ISD::ROTR, MVT::i64, Expand);
181 if (STI.hasROT32()) {
182 setOperationAction(ISD::ROTL, MVT::i32, Legal);
183 setOperationAction(ISD::ROTR, MVT::i32, Legal);
185 setOperationAction(ISD::ROTL, MVT::i32, Expand);
186 setOperationAction(ISD::ROTR, MVT::i32, Expand);
189 setOperationAction(ISD::ROTL, MVT::i16, Expand);
190 setOperationAction(ISD::ROTR, MVT::i16, Expand);
191 setOperationAction(ISD::ROTL, MVT::i8, Expand);
192 setOperationAction(ISD::ROTR, MVT::i8, Expand);
193 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
194 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
195 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
197 // Indirect branch is not supported.
198 // This also disables Jump Table creation.
199 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
200 setOperationAction(ISD::BRIND, MVT::Other, Expand);
202 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
203 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
205 // We want to legalize constant related memmove and memcopy
207 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
209 // Turn FP extload into load/fextend
210 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
211 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
212 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
213 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
214 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
215 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
216 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
217 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
218 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
219 // Turn FP truncstore into trunc + store.
220 // FIXME: vector types should also be expanded
221 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
222 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
223 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
225 // PTX does not support load / store predicate registers
226 setOperationAction(ISD::LOAD, MVT::i1, Custom);
227 setOperationAction(ISD::STORE, MVT::i1, Custom);
229 for (MVT VT : MVT::integer_valuetypes()) {
230 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
231 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
232 setTruncStoreAction(VT, MVT::i1, Expand);
235 // This is legal in NVPTX
236 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
237 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
239 // TRAP can be lowered to PTX trap
240 setOperationAction(ISD::TRAP, MVT::Other, Legal);
242 setOperationAction(ISD::ADDC, MVT::i64, Expand);
243 setOperationAction(ISD::ADDE, MVT::i64, Expand);
245 // Register custom handling for vector loads/stores
246 for (MVT VT : MVT::vector_valuetypes()) {
247 if (IsPTXVectorType(VT)) {
248 setOperationAction(ISD::LOAD, VT, Custom);
249 setOperationAction(ISD::STORE, VT, Custom);
250 setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
254 // Custom handling for i8 intrinsics
255 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
257 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
258 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
259 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
260 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal);
261 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
262 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
263 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
264 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
265 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
266 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
267 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
268 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
269 setOperationAction(ISD::CTPOP, MVT::i16, Legal);
270 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
271 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
273 // PTX does not directly support SELP of i1, so promote to i32 first
274 setOperationAction(ISD::SELECT, MVT::i1, Custom);
276 // We have some custom DAG combine patterns for these nodes
277 setTargetDAGCombine(ISD::ADD);
278 setTargetDAGCombine(ISD::AND);
279 setTargetDAGCombine(ISD::FADD);
280 setTargetDAGCombine(ISD::MUL);
281 setTargetDAGCombine(ISD::SHL);
282 setTargetDAGCombine(ISD::SELECT);
284 // Now deduce the information based on the above mentioned
286 computeRegisterProperties(STI.getRegisterInfo());
289 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
290 switch ((NVPTXISD::NodeType)Opcode) {
291 case NVPTXISD::FIRST_NUMBER:
294 return "NVPTXISD::CALL";
295 case NVPTXISD::RET_FLAG:
296 return "NVPTXISD::RET_FLAG";
297 case NVPTXISD::LOAD_PARAM:
298 return "NVPTXISD::LOAD_PARAM";
299 case NVPTXISD::Wrapper:
300 return "NVPTXISD::Wrapper";
301 case NVPTXISD::DeclareParam:
302 return "NVPTXISD::DeclareParam";
303 case NVPTXISD::DeclareScalarParam:
304 return "NVPTXISD::DeclareScalarParam";
305 case NVPTXISD::DeclareRet:
306 return "NVPTXISD::DeclareRet";
307 case NVPTXISD::DeclareScalarRet:
308 return "NVPTXISD::DeclareScalarRet";
309 case NVPTXISD::DeclareRetParam:
310 return "NVPTXISD::DeclareRetParam";
311 case NVPTXISD::PrintCall:
312 return "NVPTXISD::PrintCall";
313 case NVPTXISD::PrintCallUni:
314 return "NVPTXISD::PrintCallUni";
315 case NVPTXISD::LoadParam:
316 return "NVPTXISD::LoadParam";
317 case NVPTXISD::LoadParamV2:
318 return "NVPTXISD::LoadParamV2";
319 case NVPTXISD::LoadParamV4:
320 return "NVPTXISD::LoadParamV4";
321 case NVPTXISD::StoreParam:
322 return "NVPTXISD::StoreParam";
323 case NVPTXISD::StoreParamV2:
324 return "NVPTXISD::StoreParamV2";
325 case NVPTXISD::StoreParamV4:
326 return "NVPTXISD::StoreParamV4";
327 case NVPTXISD::StoreParamS32:
328 return "NVPTXISD::StoreParamS32";
329 case NVPTXISD::StoreParamU32:
330 return "NVPTXISD::StoreParamU32";
331 case NVPTXISD::CallArgBegin:
332 return "NVPTXISD::CallArgBegin";
333 case NVPTXISD::CallArg:
334 return "NVPTXISD::CallArg";
335 case NVPTXISD::LastCallArg:
336 return "NVPTXISD::LastCallArg";
337 case NVPTXISD::CallArgEnd:
338 return "NVPTXISD::CallArgEnd";
339 case NVPTXISD::CallVoid:
340 return "NVPTXISD::CallVoid";
341 case NVPTXISD::CallVal:
342 return "NVPTXISD::CallVal";
343 case NVPTXISD::CallSymbol:
344 return "NVPTXISD::CallSymbol";
345 case NVPTXISD::Prototype:
346 return "NVPTXISD::Prototype";
347 case NVPTXISD::MoveParam:
348 return "NVPTXISD::MoveParam";
349 case NVPTXISD::StoreRetval:
350 return "NVPTXISD::StoreRetval";
351 case NVPTXISD::StoreRetvalV2:
352 return "NVPTXISD::StoreRetvalV2";
353 case NVPTXISD::StoreRetvalV4:
354 return "NVPTXISD::StoreRetvalV4";
355 case NVPTXISD::PseudoUseParam:
356 return "NVPTXISD::PseudoUseParam";
357 case NVPTXISD::RETURN:
358 return "NVPTXISD::RETURN";
359 case NVPTXISD::CallSeqBegin:
360 return "NVPTXISD::CallSeqBegin";
361 case NVPTXISD::CallSeqEnd:
362 return "NVPTXISD::CallSeqEnd";
363 case NVPTXISD::CallPrototype:
364 return "NVPTXISD::CallPrototype";
365 case NVPTXISD::LoadV2:
366 return "NVPTXISD::LoadV2";
367 case NVPTXISD::LoadV4:
368 return "NVPTXISD::LoadV4";
369 case NVPTXISD::LDGV2:
370 return "NVPTXISD::LDGV2";
371 case NVPTXISD::LDGV4:
372 return "NVPTXISD::LDGV4";
373 case NVPTXISD::LDUV2:
374 return "NVPTXISD::LDUV2";
375 case NVPTXISD::LDUV4:
376 return "NVPTXISD::LDUV4";
377 case NVPTXISD::StoreV2:
378 return "NVPTXISD::StoreV2";
379 case NVPTXISD::StoreV4:
380 return "NVPTXISD::StoreV4";
381 case NVPTXISD::FUN_SHFL_CLAMP:
382 return "NVPTXISD::FUN_SHFL_CLAMP";
383 case NVPTXISD::FUN_SHFR_CLAMP:
384 return "NVPTXISD::FUN_SHFR_CLAMP";
386 return "NVPTXISD::IMAD";
387 case NVPTXISD::Dummy:
388 return "NVPTXISD::Dummy";
389 case NVPTXISD::MUL_WIDE_SIGNED:
390 return "NVPTXISD::MUL_WIDE_SIGNED";
391 case NVPTXISD::MUL_WIDE_UNSIGNED:
392 return "NVPTXISD::MUL_WIDE_UNSIGNED";
393 case NVPTXISD::Tex1DFloatS32: return "NVPTXISD::Tex1DFloatS32";
394 case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
395 case NVPTXISD::Tex1DFloatFloatLevel:
396 return "NVPTXISD::Tex1DFloatFloatLevel";
397 case NVPTXISD::Tex1DFloatFloatGrad:
398 return "NVPTXISD::Tex1DFloatFloatGrad";
399 case NVPTXISD::Tex1DS32S32: return "NVPTXISD::Tex1DS32S32";
400 case NVPTXISD::Tex1DS32Float: return "NVPTXISD::Tex1DS32Float";
401 case NVPTXISD::Tex1DS32FloatLevel:
402 return "NVPTXISD::Tex1DS32FloatLevel";
403 case NVPTXISD::Tex1DS32FloatGrad:
404 return "NVPTXISD::Tex1DS32FloatGrad";
405 case NVPTXISD::Tex1DU32S32: return "NVPTXISD::Tex1DU32S32";
406 case NVPTXISD::Tex1DU32Float: return "NVPTXISD::Tex1DU32Float";
407 case NVPTXISD::Tex1DU32FloatLevel:
408 return "NVPTXISD::Tex1DU32FloatLevel";
409 case NVPTXISD::Tex1DU32FloatGrad:
410 return "NVPTXISD::Tex1DU32FloatGrad";
411 case NVPTXISD::Tex1DArrayFloatS32: return "NVPTXISD::Tex1DArrayFloatS32";
412 case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
413 case NVPTXISD::Tex1DArrayFloatFloatLevel:
414 return "NVPTXISD::Tex1DArrayFloatFloatLevel";
415 case NVPTXISD::Tex1DArrayFloatFloatGrad:
416 return "NVPTXISD::Tex1DArrayFloatFloatGrad";
417 case NVPTXISD::Tex1DArrayS32S32: return "NVPTXISD::Tex1DArrayS32S32";
418 case NVPTXISD::Tex1DArrayS32Float: return "NVPTXISD::Tex1DArrayS32Float";
419 case NVPTXISD::Tex1DArrayS32FloatLevel:
420 return "NVPTXISD::Tex1DArrayS32FloatLevel";
421 case NVPTXISD::Tex1DArrayS32FloatGrad:
422 return "NVPTXISD::Tex1DArrayS32FloatGrad";
423 case NVPTXISD::Tex1DArrayU32S32: return "NVPTXISD::Tex1DArrayU32S32";
424 case NVPTXISD::Tex1DArrayU32Float: return "NVPTXISD::Tex1DArrayU32Float";
425 case NVPTXISD::Tex1DArrayU32FloatLevel:
426 return "NVPTXISD::Tex1DArrayU32FloatLevel";
427 case NVPTXISD::Tex1DArrayU32FloatGrad:
428 return "NVPTXISD::Tex1DArrayU32FloatGrad";
429 case NVPTXISD::Tex2DFloatS32: return "NVPTXISD::Tex2DFloatS32";
430 case NVPTXISD::Tex2DFloatFloat: return "NVPTXISD::Tex2DFloatFloat";
431 case NVPTXISD::Tex2DFloatFloatLevel:
432 return "NVPTXISD::Tex2DFloatFloatLevel";
433 case NVPTXISD::Tex2DFloatFloatGrad:
434 return "NVPTXISD::Tex2DFloatFloatGrad";
435 case NVPTXISD::Tex2DS32S32: return "NVPTXISD::Tex2DS32S32";
436 case NVPTXISD::Tex2DS32Float: return "NVPTXISD::Tex2DS32Float";
437 case NVPTXISD::Tex2DS32FloatLevel:
438 return "NVPTXISD::Tex2DS32FloatLevel";
439 case NVPTXISD::Tex2DS32FloatGrad:
440 return "NVPTXISD::Tex2DS32FloatGrad";
441 case NVPTXISD::Tex2DU32S32: return "NVPTXISD::Tex2DU32S32";
442 case NVPTXISD::Tex2DU32Float: return "NVPTXISD::Tex2DU32Float";
443 case NVPTXISD::Tex2DU32FloatLevel:
444 return "NVPTXISD::Tex2DU32FloatLevel";
445 case NVPTXISD::Tex2DU32FloatGrad:
446 return "NVPTXISD::Tex2DU32FloatGrad";
447 case NVPTXISD::Tex2DArrayFloatS32: return "NVPTXISD::Tex2DArrayFloatS32";
448 case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
449 case NVPTXISD::Tex2DArrayFloatFloatLevel:
450 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
451 case NVPTXISD::Tex2DArrayFloatFloatGrad:
452 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
453 case NVPTXISD::Tex2DArrayS32S32: return "NVPTXISD::Tex2DArrayS32S32";
454 case NVPTXISD::Tex2DArrayS32Float: return "NVPTXISD::Tex2DArrayS32Float";
455 case NVPTXISD::Tex2DArrayS32FloatLevel:
456 return "NVPTXISD::Tex2DArrayS32FloatLevel";
457 case NVPTXISD::Tex2DArrayS32FloatGrad:
458 return "NVPTXISD::Tex2DArrayS32FloatGrad";
459 case NVPTXISD::Tex2DArrayU32S32: return "NVPTXISD::Tex2DArrayU32S32";
460 case NVPTXISD::Tex2DArrayU32Float: return "NVPTXISD::Tex2DArrayU32Float";
461 case NVPTXISD::Tex2DArrayU32FloatLevel:
462 return "NVPTXISD::Tex2DArrayU32FloatLevel";
463 case NVPTXISD::Tex2DArrayU32FloatGrad:
464 return "NVPTXISD::Tex2DArrayU32FloatGrad";
465 case NVPTXISD::Tex3DFloatS32: return "NVPTXISD::Tex3DFloatS32";
466 case NVPTXISD::Tex3DFloatFloat: return "NVPTXISD::Tex3DFloatFloat";
467 case NVPTXISD::Tex3DFloatFloatLevel:
468 return "NVPTXISD::Tex3DFloatFloatLevel";
469 case NVPTXISD::Tex3DFloatFloatGrad:
470 return "NVPTXISD::Tex3DFloatFloatGrad";
471 case NVPTXISD::Tex3DS32S32: return "NVPTXISD::Tex3DS32S32";
472 case NVPTXISD::Tex3DS32Float: return "NVPTXISD::Tex3DS32Float";
473 case NVPTXISD::Tex3DS32FloatLevel:
474 return "NVPTXISD::Tex3DS32FloatLevel";
475 case NVPTXISD::Tex3DS32FloatGrad:
476 return "NVPTXISD::Tex3DS32FloatGrad";
477 case NVPTXISD::Tex3DU32S32: return "NVPTXISD::Tex3DU32S32";
478 case NVPTXISD::Tex3DU32Float: return "NVPTXISD::Tex3DU32Float";
479 case NVPTXISD::Tex3DU32FloatLevel:
480 return "NVPTXISD::Tex3DU32FloatLevel";
481 case NVPTXISD::Tex3DU32FloatGrad:
482 return "NVPTXISD::Tex3DU32FloatGrad";
483 case NVPTXISD::TexCubeFloatFloat: return "NVPTXISD::TexCubeFloatFloat";
484 case NVPTXISD::TexCubeFloatFloatLevel:
485 return "NVPTXISD::TexCubeFloatFloatLevel";
486 case NVPTXISD::TexCubeS32Float: return "NVPTXISD::TexCubeS32Float";
487 case NVPTXISD::TexCubeS32FloatLevel:
488 return "NVPTXISD::TexCubeS32FloatLevel";
489 case NVPTXISD::TexCubeU32Float: return "NVPTXISD::TexCubeU32Float";
490 case NVPTXISD::TexCubeU32FloatLevel:
491 return "NVPTXISD::TexCubeU32FloatLevel";
492 case NVPTXISD::TexCubeArrayFloatFloat:
493 return "NVPTXISD::TexCubeArrayFloatFloat";
494 case NVPTXISD::TexCubeArrayFloatFloatLevel:
495 return "NVPTXISD::TexCubeArrayFloatFloatLevel";
496 case NVPTXISD::TexCubeArrayS32Float:
497 return "NVPTXISD::TexCubeArrayS32Float";
498 case NVPTXISD::TexCubeArrayS32FloatLevel:
499 return "NVPTXISD::TexCubeArrayS32FloatLevel";
500 case NVPTXISD::TexCubeArrayU32Float:
501 return "NVPTXISD::TexCubeArrayU32Float";
502 case NVPTXISD::TexCubeArrayU32FloatLevel:
503 return "NVPTXISD::TexCubeArrayU32FloatLevel";
504 case NVPTXISD::Tld4R2DFloatFloat:
505 return "NVPTXISD::Tld4R2DFloatFloat";
506 case NVPTXISD::Tld4G2DFloatFloat:
507 return "NVPTXISD::Tld4G2DFloatFloat";
508 case NVPTXISD::Tld4B2DFloatFloat:
509 return "NVPTXISD::Tld4B2DFloatFloat";
510 case NVPTXISD::Tld4A2DFloatFloat:
511 return "NVPTXISD::Tld4A2DFloatFloat";
512 case NVPTXISD::Tld4R2DS64Float:
513 return "NVPTXISD::Tld4R2DS64Float";
514 case NVPTXISD::Tld4G2DS64Float:
515 return "NVPTXISD::Tld4G2DS64Float";
516 case NVPTXISD::Tld4B2DS64Float:
517 return "NVPTXISD::Tld4B2DS64Float";
518 case NVPTXISD::Tld4A2DS64Float:
519 return "NVPTXISD::Tld4A2DS64Float";
520 case NVPTXISD::Tld4R2DU64Float:
521 return "NVPTXISD::Tld4R2DU64Float";
522 case NVPTXISD::Tld4G2DU64Float:
523 return "NVPTXISD::Tld4G2DU64Float";
524 case NVPTXISD::Tld4B2DU64Float:
525 return "NVPTXISD::Tld4B2DU64Float";
526 case NVPTXISD::Tld4A2DU64Float:
527 return "NVPTXISD::Tld4A2DU64Float";
529 case NVPTXISD::TexUnified1DFloatS32:
530 return "NVPTXISD::TexUnified1DFloatS32";
531 case NVPTXISD::TexUnified1DFloatFloat:
532 return "NVPTXISD::TexUnified1DFloatFloat";
533 case NVPTXISD::TexUnified1DFloatFloatLevel:
534 return "NVPTXISD::TexUnified1DFloatFloatLevel";
535 case NVPTXISD::TexUnified1DFloatFloatGrad:
536 return "NVPTXISD::TexUnified1DFloatFloatGrad";
537 case NVPTXISD::TexUnified1DS32S32:
538 return "NVPTXISD::TexUnified1DS32S32";
539 case NVPTXISD::TexUnified1DS32Float:
540 return "NVPTXISD::TexUnified1DS32Float";
541 case NVPTXISD::TexUnified1DS32FloatLevel:
542 return "NVPTXISD::TexUnified1DS32FloatLevel";
543 case NVPTXISD::TexUnified1DS32FloatGrad:
544 return "NVPTXISD::TexUnified1DS32FloatGrad";
545 case NVPTXISD::TexUnified1DU32S32:
546 return "NVPTXISD::TexUnified1DU32S32";
547 case NVPTXISD::TexUnified1DU32Float:
548 return "NVPTXISD::TexUnified1DU32Float";
549 case NVPTXISD::TexUnified1DU32FloatLevel:
550 return "NVPTXISD::TexUnified1DU32FloatLevel";
551 case NVPTXISD::TexUnified1DU32FloatGrad:
552 return "NVPTXISD::TexUnified1DU32FloatGrad";
553 case NVPTXISD::TexUnified1DArrayFloatS32:
554 return "NVPTXISD::TexUnified1DArrayFloatS32";
555 case NVPTXISD::TexUnified1DArrayFloatFloat:
556 return "NVPTXISD::TexUnified1DArrayFloatFloat";
557 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
558 return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
559 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
560 return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
561 case NVPTXISD::TexUnified1DArrayS32S32:
562 return "NVPTXISD::TexUnified1DArrayS32S32";
563 case NVPTXISD::TexUnified1DArrayS32Float:
564 return "NVPTXISD::TexUnified1DArrayS32Float";
565 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
566 return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
567 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
568 return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
569 case NVPTXISD::TexUnified1DArrayU32S32:
570 return "NVPTXISD::TexUnified1DArrayU32S32";
571 case NVPTXISD::TexUnified1DArrayU32Float:
572 return "NVPTXISD::TexUnified1DArrayU32Float";
573 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
574 return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
575 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
576 return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
577 case NVPTXISD::TexUnified2DFloatS32:
578 return "NVPTXISD::TexUnified2DFloatS32";
579 case NVPTXISD::TexUnified2DFloatFloat:
580 return "NVPTXISD::TexUnified2DFloatFloat";
581 case NVPTXISD::TexUnified2DFloatFloatLevel:
582 return "NVPTXISD::TexUnified2DFloatFloatLevel";
583 case NVPTXISD::TexUnified2DFloatFloatGrad:
584 return "NVPTXISD::TexUnified2DFloatFloatGrad";
585 case NVPTXISD::TexUnified2DS32S32:
586 return "NVPTXISD::TexUnified2DS32S32";
587 case NVPTXISD::TexUnified2DS32Float:
588 return "NVPTXISD::TexUnified2DS32Float";
589 case NVPTXISD::TexUnified2DS32FloatLevel:
590 return "NVPTXISD::TexUnified2DS32FloatLevel";
591 case NVPTXISD::TexUnified2DS32FloatGrad:
592 return "NVPTXISD::TexUnified2DS32FloatGrad";
593 case NVPTXISD::TexUnified2DU32S32:
594 return "NVPTXISD::TexUnified2DU32S32";
595 case NVPTXISD::TexUnified2DU32Float:
596 return "NVPTXISD::TexUnified2DU32Float";
597 case NVPTXISD::TexUnified2DU32FloatLevel:
598 return "NVPTXISD::TexUnified2DU32FloatLevel";
599 case NVPTXISD::TexUnified2DU32FloatGrad:
600 return "NVPTXISD::TexUnified2DU32FloatGrad";
601 case NVPTXISD::TexUnified2DArrayFloatS32:
602 return "NVPTXISD::TexUnified2DArrayFloatS32";
603 case NVPTXISD::TexUnified2DArrayFloatFloat:
604 return "NVPTXISD::TexUnified2DArrayFloatFloat";
605 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
606 return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
607 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
608 return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
609 case NVPTXISD::TexUnified2DArrayS32S32:
610 return "NVPTXISD::TexUnified2DArrayS32S32";
611 case NVPTXISD::TexUnified2DArrayS32Float:
612 return "NVPTXISD::TexUnified2DArrayS32Float";
613 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
614 return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
615 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
616 return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
617 case NVPTXISD::TexUnified2DArrayU32S32:
618 return "NVPTXISD::TexUnified2DArrayU32S32";
619 case NVPTXISD::TexUnified2DArrayU32Float:
620 return "NVPTXISD::TexUnified2DArrayU32Float";
621 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
622 return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
623 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
624 return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
625 case NVPTXISD::TexUnified3DFloatS32:
626 return "NVPTXISD::TexUnified3DFloatS32";
627 case NVPTXISD::TexUnified3DFloatFloat:
628 return "NVPTXISD::TexUnified3DFloatFloat";
629 case NVPTXISD::TexUnified3DFloatFloatLevel:
630 return "NVPTXISD::TexUnified3DFloatFloatLevel";
631 case NVPTXISD::TexUnified3DFloatFloatGrad:
632 return "NVPTXISD::TexUnified3DFloatFloatGrad";
633 case NVPTXISD::TexUnified3DS32S32:
634 return "NVPTXISD::TexUnified3DS32S32";
635 case NVPTXISD::TexUnified3DS32Float:
636 return "NVPTXISD::TexUnified3DS32Float";
637 case NVPTXISD::TexUnified3DS32FloatLevel:
638 return "NVPTXISD::TexUnified3DS32FloatLevel";
639 case NVPTXISD::TexUnified3DS32FloatGrad:
640 return "NVPTXISD::TexUnified3DS32FloatGrad";
641 case NVPTXISD::TexUnified3DU32S32:
642 return "NVPTXISD::TexUnified3DU32S32";
643 case NVPTXISD::TexUnified3DU32Float:
644 return "NVPTXISD::TexUnified3DU32Float";
645 case NVPTXISD::TexUnified3DU32FloatLevel:
646 return "NVPTXISD::TexUnified3DU32FloatLevel";
647 case NVPTXISD::TexUnified3DU32FloatGrad:
648 return "NVPTXISD::TexUnified3DU32FloatGrad";
649 case NVPTXISD::TexUnifiedCubeFloatFloat:
650 return "NVPTXISD::TexUnifiedCubeFloatFloat";
651 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
652 return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
653 case NVPTXISD::TexUnifiedCubeS32Float:
654 return "NVPTXISD::TexUnifiedCubeS32Float";
655 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
656 return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
657 case NVPTXISD::TexUnifiedCubeU32Float:
658 return "NVPTXISD::TexUnifiedCubeU32Float";
659 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
660 return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
661 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
662 return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
663 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
664 return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
665 case NVPTXISD::TexUnifiedCubeArrayS32Float:
666 return "NVPTXISD::TexUnifiedCubeArrayS32Float";
667 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
668 return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
669 case NVPTXISD::TexUnifiedCubeArrayU32Float:
670 return "NVPTXISD::TexUnifiedCubeArrayU32Float";
671 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
672 return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
673 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
674 return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
675 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
676 return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
677 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
678 return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
679 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
680 return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
681 case NVPTXISD::Tld4UnifiedR2DS64Float:
682 return "NVPTXISD::Tld4UnifiedR2DS64Float";
683 case NVPTXISD::Tld4UnifiedG2DS64Float:
684 return "NVPTXISD::Tld4UnifiedG2DS64Float";
685 case NVPTXISD::Tld4UnifiedB2DS64Float:
686 return "NVPTXISD::Tld4UnifiedB2DS64Float";
687 case NVPTXISD::Tld4UnifiedA2DS64Float:
688 return "NVPTXISD::Tld4UnifiedA2DS64Float";
689 case NVPTXISD::Tld4UnifiedR2DU64Float:
690 return "NVPTXISD::Tld4UnifiedR2DU64Float";
691 case NVPTXISD::Tld4UnifiedG2DU64Float:
692 return "NVPTXISD::Tld4UnifiedG2DU64Float";
693 case NVPTXISD::Tld4UnifiedB2DU64Float:
694 return "NVPTXISD::Tld4UnifiedB2DU64Float";
695 case NVPTXISD::Tld4UnifiedA2DU64Float:
696 return "NVPTXISD::Tld4UnifiedA2DU64Float";
698 case NVPTXISD::Suld1DI8Clamp: return "NVPTXISD::Suld1DI8Clamp";
699 case NVPTXISD::Suld1DI16Clamp: return "NVPTXISD::Suld1DI16Clamp";
700 case NVPTXISD::Suld1DI32Clamp: return "NVPTXISD::Suld1DI32Clamp";
701 case NVPTXISD::Suld1DI64Clamp: return "NVPTXISD::Suld1DI64Clamp";
702 case NVPTXISD::Suld1DV2I8Clamp: return "NVPTXISD::Suld1DV2I8Clamp";
703 case NVPTXISD::Suld1DV2I16Clamp: return "NVPTXISD::Suld1DV2I16Clamp";
704 case NVPTXISD::Suld1DV2I32Clamp: return "NVPTXISD::Suld1DV2I32Clamp";
705 case NVPTXISD::Suld1DV2I64Clamp: return "NVPTXISD::Suld1DV2I64Clamp";
706 case NVPTXISD::Suld1DV4I8Clamp: return "NVPTXISD::Suld1DV4I8Clamp";
707 case NVPTXISD::Suld1DV4I16Clamp: return "NVPTXISD::Suld1DV4I16Clamp";
708 case NVPTXISD::Suld1DV4I32Clamp: return "NVPTXISD::Suld1DV4I32Clamp";
710 case NVPTXISD::Suld1DArrayI8Clamp: return "NVPTXISD::Suld1DArrayI8Clamp";
711 case NVPTXISD::Suld1DArrayI16Clamp: return "NVPTXISD::Suld1DArrayI16Clamp";
712 case NVPTXISD::Suld1DArrayI32Clamp: return "NVPTXISD::Suld1DArrayI32Clamp";
713 case NVPTXISD::Suld1DArrayI64Clamp: return "NVPTXISD::Suld1DArrayI64Clamp";
714 case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
715 case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
716 case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
717 case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
718 case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
719 case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
720 case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
722 case NVPTXISD::Suld2DI8Clamp: return "NVPTXISD::Suld2DI8Clamp";
723 case NVPTXISD::Suld2DI16Clamp: return "NVPTXISD::Suld2DI16Clamp";
724 case NVPTXISD::Suld2DI32Clamp: return "NVPTXISD::Suld2DI32Clamp";
725 case NVPTXISD::Suld2DI64Clamp: return "NVPTXISD::Suld2DI64Clamp";
726 case NVPTXISD::Suld2DV2I8Clamp: return "NVPTXISD::Suld2DV2I8Clamp";
727 case NVPTXISD::Suld2DV2I16Clamp: return "NVPTXISD::Suld2DV2I16Clamp";
728 case NVPTXISD::Suld2DV2I32Clamp: return "NVPTXISD::Suld2DV2I32Clamp";
729 case NVPTXISD::Suld2DV2I64Clamp: return "NVPTXISD::Suld2DV2I64Clamp";
730 case NVPTXISD::Suld2DV4I8Clamp: return "NVPTXISD::Suld2DV4I8Clamp";
731 case NVPTXISD::Suld2DV4I16Clamp: return "NVPTXISD::Suld2DV4I16Clamp";
732 case NVPTXISD::Suld2DV4I32Clamp: return "NVPTXISD::Suld2DV4I32Clamp";
734 case NVPTXISD::Suld2DArrayI8Clamp: return "NVPTXISD::Suld2DArrayI8Clamp";
735 case NVPTXISD::Suld2DArrayI16Clamp: return "NVPTXISD::Suld2DArrayI16Clamp";
736 case NVPTXISD::Suld2DArrayI32Clamp: return "NVPTXISD::Suld2DArrayI32Clamp";
737 case NVPTXISD::Suld2DArrayI64Clamp: return "NVPTXISD::Suld2DArrayI64Clamp";
738 case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
739 case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
740 case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
741 case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
742 case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
743 case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
744 case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
746 case NVPTXISD::Suld3DI8Clamp: return "NVPTXISD::Suld3DI8Clamp";
747 case NVPTXISD::Suld3DI16Clamp: return "NVPTXISD::Suld3DI16Clamp";
748 case NVPTXISD::Suld3DI32Clamp: return "NVPTXISD::Suld3DI32Clamp";
749 case NVPTXISD::Suld3DI64Clamp: return "NVPTXISD::Suld3DI64Clamp";
750 case NVPTXISD::Suld3DV2I8Clamp: return "NVPTXISD::Suld3DV2I8Clamp";
751 case NVPTXISD::Suld3DV2I16Clamp: return "NVPTXISD::Suld3DV2I16Clamp";
752 case NVPTXISD::Suld3DV2I32Clamp: return "NVPTXISD::Suld3DV2I32Clamp";
753 case NVPTXISD::Suld3DV2I64Clamp: return "NVPTXISD::Suld3DV2I64Clamp";
754 case NVPTXISD::Suld3DV4I8Clamp: return "NVPTXISD::Suld3DV4I8Clamp";
755 case NVPTXISD::Suld3DV4I16Clamp: return "NVPTXISD::Suld3DV4I16Clamp";
756 case NVPTXISD::Suld3DV4I32Clamp: return "NVPTXISD::Suld3DV4I32Clamp";
758 case NVPTXISD::Suld1DI8Trap: return "NVPTXISD::Suld1DI8Trap";
759 case NVPTXISD::Suld1DI16Trap: return "NVPTXISD::Suld1DI16Trap";
760 case NVPTXISD::Suld1DI32Trap: return "NVPTXISD::Suld1DI32Trap";
761 case NVPTXISD::Suld1DI64Trap: return "NVPTXISD::Suld1DI64Trap";
762 case NVPTXISD::Suld1DV2I8Trap: return "NVPTXISD::Suld1DV2I8Trap";
763 case NVPTXISD::Suld1DV2I16Trap: return "NVPTXISD::Suld1DV2I16Trap";
764 case NVPTXISD::Suld1DV2I32Trap: return "NVPTXISD::Suld1DV2I32Trap";
765 case NVPTXISD::Suld1DV2I64Trap: return "NVPTXISD::Suld1DV2I64Trap";
766 case NVPTXISD::Suld1DV4I8Trap: return "NVPTXISD::Suld1DV4I8Trap";
767 case NVPTXISD::Suld1DV4I16Trap: return "NVPTXISD::Suld1DV4I16Trap";
768 case NVPTXISD::Suld1DV4I32Trap: return "NVPTXISD::Suld1DV4I32Trap";
770 case NVPTXISD::Suld1DArrayI8Trap: return "NVPTXISD::Suld1DArrayI8Trap";
771 case NVPTXISD::Suld1DArrayI16Trap: return "NVPTXISD::Suld1DArrayI16Trap";
772 case NVPTXISD::Suld1DArrayI32Trap: return "NVPTXISD::Suld1DArrayI32Trap";
773 case NVPTXISD::Suld1DArrayI64Trap: return "NVPTXISD::Suld1DArrayI64Trap";
774 case NVPTXISD::Suld1DArrayV2I8Trap: return "NVPTXISD::Suld1DArrayV2I8Trap";
775 case NVPTXISD::Suld1DArrayV2I16Trap: return "NVPTXISD::Suld1DArrayV2I16Trap";
776 case NVPTXISD::Suld1DArrayV2I32Trap: return "NVPTXISD::Suld1DArrayV2I32Trap";
777 case NVPTXISD::Suld1DArrayV2I64Trap: return "NVPTXISD::Suld1DArrayV2I64Trap";
778 case NVPTXISD::Suld1DArrayV4I8Trap: return "NVPTXISD::Suld1DArrayV4I8Trap";
779 case NVPTXISD::Suld1DArrayV4I16Trap: return "NVPTXISD::Suld1DArrayV4I16Trap";
780 case NVPTXISD::Suld1DArrayV4I32Trap: return "NVPTXISD::Suld1DArrayV4I32Trap";
782 case NVPTXISD::Suld2DI8Trap: return "NVPTXISD::Suld2DI8Trap";
783 case NVPTXISD::Suld2DI16Trap: return "NVPTXISD::Suld2DI16Trap";
784 case NVPTXISD::Suld2DI32Trap: return "NVPTXISD::Suld2DI32Trap";
785 case NVPTXISD::Suld2DI64Trap: return "NVPTXISD::Suld2DI64Trap";
786 case NVPTXISD::Suld2DV2I8Trap: return "NVPTXISD::Suld2DV2I8Trap";
787 case NVPTXISD::Suld2DV2I16Trap: return "NVPTXISD::Suld2DV2I16Trap";
788 case NVPTXISD::Suld2DV2I32Trap: return "NVPTXISD::Suld2DV2I32Trap";
789 case NVPTXISD::Suld2DV2I64Trap: return "NVPTXISD::Suld2DV2I64Trap";
790 case NVPTXISD::Suld2DV4I8Trap: return "NVPTXISD::Suld2DV4I8Trap";
791 case NVPTXISD::Suld2DV4I16Trap: return "NVPTXISD::Suld2DV4I16Trap";
792 case NVPTXISD::Suld2DV4I32Trap: return "NVPTXISD::Suld2DV4I32Trap";
794 case NVPTXISD::Suld2DArrayI8Trap: return "NVPTXISD::Suld2DArrayI8Trap";
795 case NVPTXISD::Suld2DArrayI16Trap: return "NVPTXISD::Suld2DArrayI16Trap";
796 case NVPTXISD::Suld2DArrayI32Trap: return "NVPTXISD::Suld2DArrayI32Trap";
797 case NVPTXISD::Suld2DArrayI64Trap: return "NVPTXISD::Suld2DArrayI64Trap";
798 case NVPTXISD::Suld2DArrayV2I8Trap: return "NVPTXISD::Suld2DArrayV2I8Trap";
799 case NVPTXISD::Suld2DArrayV2I16Trap: return "NVPTXISD::Suld2DArrayV2I16Trap";
800 case NVPTXISD::Suld2DArrayV2I32Trap: return "NVPTXISD::Suld2DArrayV2I32Trap";
801 case NVPTXISD::Suld2DArrayV2I64Trap: return "NVPTXISD::Suld2DArrayV2I64Trap";
802 case NVPTXISD::Suld2DArrayV4I8Trap: return "NVPTXISD::Suld2DArrayV4I8Trap";
803 case NVPTXISD::Suld2DArrayV4I16Trap: return "NVPTXISD::Suld2DArrayV4I16Trap";
804 case NVPTXISD::Suld2DArrayV4I32Trap: return "NVPTXISD::Suld2DArrayV4I32Trap";
806 case NVPTXISD::Suld3DI8Trap: return "NVPTXISD::Suld3DI8Trap";
807 case NVPTXISD::Suld3DI16Trap: return "NVPTXISD::Suld3DI16Trap";
808 case NVPTXISD::Suld3DI32Trap: return "NVPTXISD::Suld3DI32Trap";
809 case NVPTXISD::Suld3DI64Trap: return "NVPTXISD::Suld3DI64Trap";
810 case NVPTXISD::Suld3DV2I8Trap: return "NVPTXISD::Suld3DV2I8Trap";
811 case NVPTXISD::Suld3DV2I16Trap: return "NVPTXISD::Suld3DV2I16Trap";
812 case NVPTXISD::Suld3DV2I32Trap: return "NVPTXISD::Suld3DV2I32Trap";
813 case NVPTXISD::Suld3DV2I64Trap: return "NVPTXISD::Suld3DV2I64Trap";
814 case NVPTXISD::Suld3DV4I8Trap: return "NVPTXISD::Suld3DV4I8Trap";
815 case NVPTXISD::Suld3DV4I16Trap: return "NVPTXISD::Suld3DV4I16Trap";
816 case NVPTXISD::Suld3DV4I32Trap: return "NVPTXISD::Suld3DV4I32Trap";
818 case NVPTXISD::Suld1DI8Zero: return "NVPTXISD::Suld1DI8Zero";
819 case NVPTXISD::Suld1DI16Zero: return "NVPTXISD::Suld1DI16Zero";
820 case NVPTXISD::Suld1DI32Zero: return "NVPTXISD::Suld1DI32Zero";
821 case NVPTXISD::Suld1DI64Zero: return "NVPTXISD::Suld1DI64Zero";
822 case NVPTXISD::Suld1DV2I8Zero: return "NVPTXISD::Suld1DV2I8Zero";
823 case NVPTXISD::Suld1DV2I16Zero: return "NVPTXISD::Suld1DV2I16Zero";
824 case NVPTXISD::Suld1DV2I32Zero: return "NVPTXISD::Suld1DV2I32Zero";
825 case NVPTXISD::Suld1DV2I64Zero: return "NVPTXISD::Suld1DV2I64Zero";
826 case NVPTXISD::Suld1DV4I8Zero: return "NVPTXISD::Suld1DV4I8Zero";
827 case NVPTXISD::Suld1DV4I16Zero: return "NVPTXISD::Suld1DV4I16Zero";
828 case NVPTXISD::Suld1DV4I32Zero: return "NVPTXISD::Suld1DV4I32Zero";
830 case NVPTXISD::Suld1DArrayI8Zero: return "NVPTXISD::Suld1DArrayI8Zero";
831 case NVPTXISD::Suld1DArrayI16Zero: return "NVPTXISD::Suld1DArrayI16Zero";
832 case NVPTXISD::Suld1DArrayI32Zero: return "NVPTXISD::Suld1DArrayI32Zero";
833 case NVPTXISD::Suld1DArrayI64Zero: return "NVPTXISD::Suld1DArrayI64Zero";
834 case NVPTXISD::Suld1DArrayV2I8Zero: return "NVPTXISD::Suld1DArrayV2I8Zero";
835 case NVPTXISD::Suld1DArrayV2I16Zero: return "NVPTXISD::Suld1DArrayV2I16Zero";
836 case NVPTXISD::Suld1DArrayV2I32Zero: return "NVPTXISD::Suld1DArrayV2I32Zero";
837 case NVPTXISD::Suld1DArrayV2I64Zero: return "NVPTXISD::Suld1DArrayV2I64Zero";
838 case NVPTXISD::Suld1DArrayV4I8Zero: return "NVPTXISD::Suld1DArrayV4I8Zero";
839 case NVPTXISD::Suld1DArrayV4I16Zero: return "NVPTXISD::Suld1DArrayV4I16Zero";
840 case NVPTXISD::Suld1DArrayV4I32Zero: return "NVPTXISD::Suld1DArrayV4I32Zero";
842 case NVPTXISD::Suld2DI8Zero: return "NVPTXISD::Suld2DI8Zero";
843 case NVPTXISD::Suld2DI16Zero: return "NVPTXISD::Suld2DI16Zero";
844 case NVPTXISD::Suld2DI32Zero: return "NVPTXISD::Suld2DI32Zero";
845 case NVPTXISD::Suld2DI64Zero: return "NVPTXISD::Suld2DI64Zero";
846 case NVPTXISD::Suld2DV2I8Zero: return "NVPTXISD::Suld2DV2I8Zero";
847 case NVPTXISD::Suld2DV2I16Zero: return "NVPTXISD::Suld2DV2I16Zero";
848 case NVPTXISD::Suld2DV2I32Zero: return "NVPTXISD::Suld2DV2I32Zero";
849 case NVPTXISD::Suld2DV2I64Zero: return "NVPTXISD::Suld2DV2I64Zero";
850 case NVPTXISD::Suld2DV4I8Zero: return "NVPTXISD::Suld2DV4I8Zero";
851 case NVPTXISD::Suld2DV4I16Zero: return "NVPTXISD::Suld2DV4I16Zero";
852 case NVPTXISD::Suld2DV4I32Zero: return "NVPTXISD::Suld2DV4I32Zero";
854 case NVPTXISD::Suld2DArrayI8Zero: return "NVPTXISD::Suld2DArrayI8Zero";
855 case NVPTXISD::Suld2DArrayI16Zero: return "NVPTXISD::Suld2DArrayI16Zero";
856 case NVPTXISD::Suld2DArrayI32Zero: return "NVPTXISD::Suld2DArrayI32Zero";
857 case NVPTXISD::Suld2DArrayI64Zero: return "NVPTXISD::Suld2DArrayI64Zero";
858 case NVPTXISD::Suld2DArrayV2I8Zero: return "NVPTXISD::Suld2DArrayV2I8Zero";
859 case NVPTXISD::Suld2DArrayV2I16Zero: return "NVPTXISD::Suld2DArrayV2I16Zero";
860 case NVPTXISD::Suld2DArrayV2I32Zero: return "NVPTXISD::Suld2DArrayV2I32Zero";
861 case NVPTXISD::Suld2DArrayV2I64Zero: return "NVPTXISD::Suld2DArrayV2I64Zero";
862 case NVPTXISD::Suld2DArrayV4I8Zero: return "NVPTXISD::Suld2DArrayV4I8Zero";
863 case NVPTXISD::Suld2DArrayV4I16Zero: return "NVPTXISD::Suld2DArrayV4I16Zero";
864 case NVPTXISD::Suld2DArrayV4I32Zero: return "NVPTXISD::Suld2DArrayV4I32Zero";
866 case NVPTXISD::Suld3DI8Zero: return "NVPTXISD::Suld3DI8Zero";
867 case NVPTXISD::Suld3DI16Zero: return "NVPTXISD::Suld3DI16Zero";
868 case NVPTXISD::Suld3DI32Zero: return "NVPTXISD::Suld3DI32Zero";
869 case NVPTXISD::Suld3DI64Zero: return "NVPTXISD::Suld3DI64Zero";
870 case NVPTXISD::Suld3DV2I8Zero: return "NVPTXISD::Suld3DV2I8Zero";
871 case NVPTXISD::Suld3DV2I16Zero: return "NVPTXISD::Suld3DV2I16Zero";
872 case NVPTXISD::Suld3DV2I32Zero: return "NVPTXISD::Suld3DV2I32Zero";
873 case NVPTXISD::Suld3DV2I64Zero: return "NVPTXISD::Suld3DV2I64Zero";
874 case NVPTXISD::Suld3DV4I8Zero: return "NVPTXISD::Suld3DV4I8Zero";
875 case NVPTXISD::Suld3DV4I16Zero: return "NVPTXISD::Suld3DV4I16Zero";
876 case NVPTXISD::Suld3DV4I32Zero: return "NVPTXISD::Suld3DV4I32Zero";
881 TargetLoweringBase::LegalizeTypeAction
882 NVPTXTargetLowering::getPreferredVectorAction(EVT VT) const {
883 if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
884 return TypeSplitVector;
886 return TargetLoweringBase::getPreferredVectorAction(VT);
890 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
892 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
893 auto PtrVT = getPointerTy(DAG.getDataLayout());
894 Op = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
895 return DAG.getNode(NVPTXISD::Wrapper, dl, PtrVT, Op);
898 std::string NVPTXTargetLowering::getPrototype(
899 const DataLayout &DL, Type *retTy, const ArgListTy &Args,
900 const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment,
901 const ImmutableCallSite *CS) const {
902 auto PtrVT = getPointerTy(DL);
904 bool isABI = (STI.getSmVersion() >= 20);
905 assert(isABI && "Non-ABI compilation is not supported");
910 O << "prototype_" << uniqueCallSite << " : .callprototype ";
912 if (retTy->getTypeID() == Type::VoidTyID) {
916 if (retTy->isFloatingPointTy() || retTy->isIntegerTy()) {
918 if (auto *ITy = dyn_cast<IntegerType>(retTy)) {
919 size = ITy->getBitWidth();
923 assert(retTy->isFloatingPointTy() &&
924 "Floating point type expected here");
925 size = retTy->getPrimitiveSizeInBits();
928 O << ".param .b" << size << " _";
929 } else if (isa<PointerType>(retTy)) {
930 O << ".param .b" << PtrVT.getSizeInBits() << " _";
931 } else if ((retTy->getTypeID() == Type::StructTyID) ||
932 isa<VectorType>(retTy)) {
933 auto &DL = CS->getCalledFunction()->getParent()->getDataLayout();
934 O << ".param .align " << retAlignment << " .b8 _["
935 << DL.getTypeAllocSize(retTy) << "]";
937 llvm_unreachable("Unknown return type");
946 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
947 Type *Ty = Args[i].Ty;
953 if (!Outs[OIdx].Flags.isByVal()) {
954 if (Ty->isAggregateType() || Ty->isVectorTy()) {
956 const CallInst *CallI = cast<CallInst>(CS->getInstruction());
957 // +1 because index 0 is reserved for return type alignment
958 if (!llvm::getAlign(*CallI, i + 1, align))
959 align = DL.getABITypeAlignment(Ty);
960 unsigned sz = DL.getTypeAllocSize(Ty);
961 O << ".param .align " << align << " .b8 ";
963 O << "[" << sz << "]";
964 // update the index for Outs
965 SmallVector<EVT, 16> vtparts;
966 ComputeValueVTs(*this, DL, Ty, vtparts);
967 if (unsigned len = vtparts.size())
971 // i8 types in IR will be i16 types in SDAG
972 assert((getValueType(DL, Ty) == Outs[OIdx].VT ||
973 (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
974 "type mismatch between callee prototype and arguments");
977 if (isa<IntegerType>(Ty)) {
978 sz = cast<IntegerType>(Ty)->getBitWidth();
981 } else if (isa<PointerType>(Ty))
982 sz = PtrVT.getSizeInBits();
984 sz = Ty->getPrimitiveSizeInBits();
985 O << ".param .b" << sz << " ";
989 auto *PTy = dyn_cast<PointerType>(Ty);
990 assert(PTy && "Param with byval attribute should be a pointer type");
991 Type *ETy = PTy->getElementType();
993 unsigned align = Outs[OIdx].Flags.getByValAlign();
994 unsigned sz = DL.getTypeAllocSize(ETy);
995 O << ".param .align " << align << " .b8 ";
997 O << "[" << sz << "]";
1004 NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
1005 const ImmutableCallSite *CS,
1007 unsigned Idx) const {
1009 const Value *DirectCallee = CS->getCalledFunction();
1011 if (!DirectCallee) {
1012 // We don't have a direct function symbol, but that may be because of
1013 // constant cast instructions in the call.
1014 const Instruction *CalleeI = CS->getInstruction();
1015 assert(CalleeI && "Call target is not a function or derived value?");
1017 // With bitcast'd call targets, the instruction will be the call
1018 if (isa<CallInst>(CalleeI)) {
1019 // Check if we have call alignment metadata
1020 if (llvm::getAlign(*cast<CallInst>(CalleeI), Idx, Align))
1023 const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
1024 // Ignore any bitcast instructions
1025 while(isa<ConstantExpr>(CalleeV)) {
1026 const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
1029 // Look through the bitcast
1030 CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
1033 // We have now looked past all of the bitcasts. Do we finally have a
1035 if (isa<Function>(CalleeV))
1036 DirectCallee = CalleeV;
1040 // Check for function alignment information if we found that the
1041 // ultimate target is a Function
1043 if (llvm::getAlign(*cast<Function>(DirectCallee), Idx, Align))
1046 // Call is indirect or alignment information is not available, fall back to
1047 // the ABI type alignment
1048 auto &DL = CS->getCaller()->getParent()->getDataLayout();
1049 return DL.getABITypeAlignment(Ty);
1052 SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1053 SmallVectorImpl<SDValue> &InVals) const {
1054 SelectionDAG &DAG = CLI.DAG;
1056 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1057 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1058 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1059 SDValue Chain = CLI.Chain;
1060 SDValue Callee = CLI.Callee;
1061 bool &isTailCall = CLI.IsTailCall;
1062 ArgListTy &Args = CLI.getArgs();
1063 Type *retTy = CLI.RetTy;
1064 ImmutableCallSite *CS = CLI.CS;
1066 bool isABI = (STI.getSmVersion() >= 20);
1067 assert(isABI && "Non-ABI compilation is not supported");
1070 MachineFunction &MF = DAG.getMachineFunction();
1071 const Function *F = MF.getFunction();
1072 auto &DL = MF.getDataLayout();
1074 SDValue tempChain = Chain;
1075 Chain = DAG.getCALLSEQ_START(Chain,
1076 DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1078 SDValue InFlag = Chain.getValue(1);
1080 unsigned paramCount = 0;
1081 // Args.size() and Outs.size() need not match.
1082 // Outs.size() will be larger
1083 // * if there is an aggregate argument with multiple fields (each field
1084 // showing up separately in Outs)
1085 // * if there is a vector argument with more than typical vector-length
1086 // elements (generally if more than 4) where each vector element is
1087 // individually present in Outs.
1088 // So a different index should be used for indexing into Outs/OutVals.
1089 // See similar issue in LowerFormalArguments.
1091 // Declare the .params or .reg need to pass values
1093 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
1094 EVT VT = Outs[OIdx].VT;
1095 Type *Ty = Args[i].Ty;
1097 if (!Outs[OIdx].Flags.isByVal()) {
1098 if (Ty->isAggregateType()) {
1100 SmallVector<EVT, 16> vtparts;
1101 SmallVector<uint64_t, 16> Offsets;
1102 ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts, &Offsets,
1105 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
1106 // declare .param .align <align> .b8 .param<n>[<size>];
1107 unsigned sz = DL.getTypeAllocSize(Ty);
1108 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1109 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, dl,
1111 DAG.getConstant(paramCount, dl, MVT::i32),
1112 DAG.getConstant(sz, dl, MVT::i32),
1114 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1116 InFlag = Chain.getValue(1);
1117 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1118 EVT elemtype = vtparts[j];
1119 unsigned ArgAlign = GreatestCommonDivisor64(align, Offsets[j]);
1120 if (elemtype.isInteger() && (sz < 8))
1122 SDValue StVal = OutVals[OIdx];
1123 if (elemtype.getSizeInBits() < 16) {
1124 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
1126 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1127 SDValue CopyParamOps[] = { Chain,
1128 DAG.getConstant(paramCount, dl, MVT::i32),
1129 DAG.getConstant(Offsets[j], dl, MVT::i32),
1131 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
1132 CopyParamVTs, CopyParamOps,
1133 elemtype, MachinePointerInfo(),
1135 InFlag = Chain.getValue(1);
1138 if (vtparts.size() > 0)
1143 if (Ty->isVectorTy()) {
1144 EVT ObjectVT = getValueType(DL, Ty);
1145 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
1146 // declare .param .align <align> .b8 .param<n>[<size>];
1147 unsigned sz = DL.getTypeAllocSize(Ty);
1148 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1149 SDValue DeclareParamOps[] = { Chain,
1150 DAG.getConstant(align, dl, MVT::i32),
1151 DAG.getConstant(paramCount, dl, MVT::i32),
1152 DAG.getConstant(sz, dl, MVT::i32),
1154 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1156 InFlag = Chain.getValue(1);
1157 unsigned NumElts = ObjectVT.getVectorNumElements();
1158 EVT EltVT = ObjectVT.getVectorElementType();
1160 bool NeedExtend = false;
1161 if (EltVT.getSizeInBits() < 16) {
1168 SDValue Elt = OutVals[OIdx++];
1170 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt);
1172 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1173 SDValue CopyParamOps[] = { Chain,
1174 DAG.getConstant(paramCount, dl, MVT::i32),
1175 DAG.getConstant(0, dl, MVT::i32), Elt,
1177 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
1178 CopyParamVTs, CopyParamOps,
1179 MemVT, MachinePointerInfo());
1180 InFlag = Chain.getValue(1);
1181 } else if (NumElts == 2) {
1182 SDValue Elt0 = OutVals[OIdx++];
1183 SDValue Elt1 = OutVals[OIdx++];
1185 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0);
1186 Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1);
1189 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1190 SDValue CopyParamOps[] = { Chain,
1191 DAG.getConstant(paramCount, dl, MVT::i32),
1192 DAG.getConstant(0, dl, MVT::i32), Elt0,
1194 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
1195 CopyParamVTs, CopyParamOps,
1196 MemVT, MachinePointerInfo());
1197 InFlag = Chain.getValue(1);
1199 unsigned curOffset = 0;
1201 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
1203 // vector will be expanded to a power of 2 elements, so we know we can
1204 // always round up to the next multiple of 4 when creating the vector
1206 // e.g. 4 elem => 1 st.v4
1207 // 6 elem => 2 st.v4
1208 // 8 elem => 2 st.v4
1209 // 11 elem => 3 st.v4
1210 unsigned VecSize = 4;
1211 if (EltVT.getSizeInBits() == 64)
1214 // This is potentially only part of a vector, so assume all elements
1215 // are packed together.
1216 unsigned PerStoreOffset = MemVT.getStoreSizeInBits() / 8 * VecSize;
1218 for (unsigned i = 0; i < NumElts; i += VecSize) {
1221 SmallVector<SDValue, 8> Ops;
1222 Ops.push_back(Chain);
1223 Ops.push_back(DAG.getConstant(paramCount, dl, MVT::i32));
1224 Ops.push_back(DAG.getConstant(curOffset, dl, MVT::i32));
1226 unsigned Opc = NVPTXISD::StoreParamV2;
1228 StoreVal = OutVals[OIdx++];
1230 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1231 Ops.push_back(StoreVal);
1233 if (i + 1 < NumElts) {
1234 StoreVal = OutVals[OIdx++];
1237 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1239 StoreVal = DAG.getUNDEF(EltVT);
1241 Ops.push_back(StoreVal);
1244 Opc = NVPTXISD::StoreParamV4;
1245 if (i + 2 < NumElts) {
1246 StoreVal = OutVals[OIdx++];
1249 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1251 StoreVal = DAG.getUNDEF(EltVT);
1253 Ops.push_back(StoreVal);
1255 if (i + 3 < NumElts) {
1256 StoreVal = OutVals[OIdx++];
1259 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1261 StoreVal = DAG.getUNDEF(EltVT);
1263 Ops.push_back(StoreVal);
1266 Ops.push_back(InFlag);
1268 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1269 Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, Ops,
1270 MemVT, MachinePointerInfo());
1271 InFlag = Chain.getValue(1);
1272 curOffset += PerStoreOffset;
1280 // for ABI, declare .param .b<size> .param<n>;
1281 unsigned sz = VT.getSizeInBits();
1282 bool needExtend = false;
1283 if (VT.isInteger()) {
1289 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1290 SDValue DeclareParamOps[] = { Chain,
1291 DAG.getConstant(paramCount, dl, MVT::i32),
1292 DAG.getConstant(sz, dl, MVT::i32),
1293 DAG.getConstant(0, dl, MVT::i32), InFlag };
1294 Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
1296 InFlag = Chain.getValue(1);
1297 SDValue OutV = OutVals[OIdx];
1299 // zext/sext i1 to i16
1300 unsigned opc = ISD::ZERO_EXTEND;
1301 if (Outs[OIdx].Flags.isSExt())
1302 opc = ISD::SIGN_EXTEND;
1303 OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
1305 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1306 SDValue CopyParamOps[] = { Chain,
1307 DAG.getConstant(paramCount, dl, MVT::i32),
1308 DAG.getConstant(0, dl, MVT::i32), OutV,
1311 unsigned opcode = NVPTXISD::StoreParam;
1312 if (Outs[OIdx].Flags.isZExt())
1313 opcode = NVPTXISD::StoreParamU32;
1314 else if (Outs[OIdx].Flags.isSExt())
1315 opcode = NVPTXISD::StoreParamS32;
1316 Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps,
1317 VT, MachinePointerInfo());
1319 InFlag = Chain.getValue(1);
1324 SmallVector<EVT, 16> vtparts;
1325 SmallVector<uint64_t, 16> Offsets;
1326 auto *PTy = dyn_cast<PointerType>(Args[i].Ty);
1327 assert(PTy && "Type of a byval parameter should be pointer");
1328 ComputePTXValueVTs(*this, DAG.getDataLayout(), PTy->getElementType(),
1329 vtparts, &Offsets, 0);
1331 // declare .param .align <align> .b8 .param<n>[<size>];
1332 unsigned sz = Outs[OIdx].Flags.getByValSize();
1333 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1334 unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
1335 // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
1336 // so we don't need to worry about natural alignment or not.
1337 // See TargetLowering::LowerCallTo().
1338 SDValue DeclareParamOps[] = {
1339 Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), dl, MVT::i32),
1340 DAG.getConstant(paramCount, dl, MVT::i32),
1341 DAG.getConstant(sz, dl, MVT::i32), InFlag
1343 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1345 InFlag = Chain.getValue(1);
1346 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1347 EVT elemtype = vtparts[j];
1348 int curOffset = Offsets[j];
1349 unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset);
1350 auto PtrVT = getPointerTy(DAG.getDataLayout());
1351 SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, OutVals[OIdx],
1352 DAG.getConstant(curOffset, dl, PtrVT));
1353 SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
1354 MachinePointerInfo(), false, false, false,
1356 if (elemtype.getSizeInBits() < 16) {
1357 theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
1359 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1360 SDValue CopyParamOps[] = { Chain,
1361 DAG.getConstant(paramCount, dl, MVT::i32),
1362 DAG.getConstant(curOffset, dl, MVT::i32),
1364 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
1365 CopyParamOps, elemtype,
1366 MachinePointerInfo());
1368 InFlag = Chain.getValue(1);
1373 GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
1374 unsigned retAlignment = 0;
1377 if (Ins.size() > 0) {
1378 SmallVector<EVT, 16> resvtparts;
1379 ComputeValueVTs(*this, DL, retTy, resvtparts);
1382 // .param .align 16 .b8 retval0[<size-in-bytes>], or
1383 // .param .b<size-in-bits> retval0
1384 unsigned resultsz = DL.getTypeAllocSizeInBits(retTy);
1385 // Emit ".param .b<size-in-bits> retval0" instead of byte arrays only for
1386 // these three types to match the logic in
1387 // NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
1388 // Plus, this behavior is consistent with nvcc's.
1389 if (retTy->isFloatingPointTy() || retTy->isIntegerTy() ||
1390 retTy->isPointerTy()) {
1391 // Scalar needs to be at least 32bit wide
1394 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1395 SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1396 DAG.getConstant(resultsz, dl, MVT::i32),
1397 DAG.getConstant(0, dl, MVT::i32), InFlag };
1398 Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
1400 InFlag = Chain.getValue(1);
1402 retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
1403 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1404 SDValue DeclareRetOps[] = { Chain,
1405 DAG.getConstant(retAlignment, dl, MVT::i32),
1406 DAG.getConstant(resultsz / 8, dl, MVT::i32),
1407 DAG.getConstant(0, dl, MVT::i32), InFlag };
1408 Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
1410 InFlag = Chain.getValue(1);
1415 // This is indirect function call case : PTX requires a prototype of the
1417 // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
1418 // to be emitted, and the label has to used as the last arg of call
1420 // The prototype is embedded in a string and put as the operand for a
1421 // CallPrototype SDNode which will print out to the value of the string.
1422 SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1424 getPrototype(DAG.getDataLayout(), retTy, Args, Outs, retAlignment, CS);
1425 const char *ProtoStr =
1426 nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
1427 SDValue ProtoOps[] = {
1428 Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
1430 Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
1431 InFlag = Chain.getValue(1);
1433 // Op to just print "call"
1434 SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1435 SDValue PrintCallOps[] = {
1436 Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, dl, MVT::i32), InFlag
1438 Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
1439 dl, PrintCallVTs, PrintCallOps);
1440 InFlag = Chain.getValue(1);
1442 // Ops to print out the function name
1443 SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1444 SDValue CallVoidOps[] = { Chain, Callee, InFlag };
1445 Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
1446 InFlag = Chain.getValue(1);
1448 // Ops to print out the param list
1449 SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1450 SDValue CallArgBeginOps[] = { Chain, InFlag };
1451 Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
1453 InFlag = Chain.getValue(1);
1455 for (unsigned i = 0, e = paramCount; i != e; ++i) {
1458 opcode = NVPTXISD::LastCallArg;
1460 opcode = NVPTXISD::CallArg;
1461 SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1462 SDValue CallArgOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1463 DAG.getConstant(i, dl, MVT::i32), InFlag };
1464 Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
1465 InFlag = Chain.getValue(1);
1467 SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1468 SDValue CallArgEndOps[] = { Chain,
1469 DAG.getConstant(Func ? 1 : 0, dl, MVT::i32),
1471 Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
1472 InFlag = Chain.getValue(1);
1475 SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1476 SDValue PrototypeOps[] = { Chain,
1477 DAG.getConstant(uniqueCallSite, dl, MVT::i32),
1479 Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
1480 InFlag = Chain.getValue(1);
1483 // Generate loads from param memory/moves from registers for result
1484 if (Ins.size() > 0) {
1485 if (retTy && retTy->isVectorTy()) {
1486 EVT ObjectVT = getValueType(DL, retTy);
1487 unsigned NumElts = ObjectVT.getVectorNumElements();
1488 EVT EltVT = ObjectVT.getVectorElementType();
1489 assert(STI.getTargetLowering()->getNumRegisters(F->getContext(),
1490 ObjectVT) == NumElts &&
1491 "Vector was not scalarized");
1492 unsigned sz = EltVT.getSizeInBits();
1493 bool needTruncate = sz < 8;
1496 // Just a simple load
1497 SmallVector<EVT, 4> LoadRetVTs;
1498 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1499 // If loading i1/i8 result, generate
1503 LoadRetVTs.push_back(MVT::i16);
1505 LoadRetVTs.push_back(EltVT);
1506 LoadRetVTs.push_back(MVT::Other);
1507 LoadRetVTs.push_back(MVT::Glue);
1508 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1509 DAG.getConstant(0, dl, MVT::i32), InFlag};
1510 SDValue retval = DAG.getMemIntrinsicNode(
1511 NVPTXISD::LoadParam, dl,
1512 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
1513 Chain = retval.getValue(1);
1514 InFlag = retval.getValue(2);
1515 SDValue Ret0 = retval;
1517 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0);
1518 InVals.push_back(Ret0);
1519 } else if (NumElts == 2) {
1521 SmallVector<EVT, 4> LoadRetVTs;
1522 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1523 // If loading i1/i8 result, generate
1527 LoadRetVTs.push_back(MVT::i16);
1528 LoadRetVTs.push_back(MVT::i16);
1530 LoadRetVTs.push_back(EltVT);
1531 LoadRetVTs.push_back(EltVT);
1533 LoadRetVTs.push_back(MVT::Other);
1534 LoadRetVTs.push_back(MVT::Glue);
1535 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1536 DAG.getConstant(0, dl, MVT::i32), InFlag};
1537 SDValue retval = DAG.getMemIntrinsicNode(
1538 NVPTXISD::LoadParamV2, dl,
1539 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
1540 Chain = retval.getValue(2);
1541 InFlag = retval.getValue(3);
1542 SDValue Ret0 = retval.getValue(0);
1543 SDValue Ret1 = retval.getValue(1);
1545 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0);
1546 InVals.push_back(Ret0);
1547 Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1);
1548 InVals.push_back(Ret1);
1550 InVals.push_back(Ret0);
1551 InVals.push_back(Ret1);
1554 // Split into N LoadV4
1556 unsigned VecSize = 4;
1557 unsigned Opc = NVPTXISD::LoadParamV4;
1558 if (EltVT.getSizeInBits() == 64) {
1560 Opc = NVPTXISD::LoadParamV2;
1562 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1563 for (unsigned i = 0; i < NumElts; i += VecSize) {
1564 SmallVector<EVT, 8> LoadRetVTs;
1565 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1566 // If loading i1/i8 result, generate
1570 for (unsigned j = 0; j < VecSize; ++j)
1571 LoadRetVTs.push_back(MVT::i16);
1573 for (unsigned j = 0; j < VecSize; ++j)
1574 LoadRetVTs.push_back(EltVT);
1576 LoadRetVTs.push_back(MVT::Other);
1577 LoadRetVTs.push_back(MVT::Glue);
1578 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1579 DAG.getConstant(Ofst, dl, MVT::i32), InFlag};
1580 SDValue retval = DAG.getMemIntrinsicNode(
1581 Opc, dl, DAG.getVTList(LoadRetVTs),
1582 LoadRetOps, EltVT, MachinePointerInfo());
1584 Chain = retval.getValue(2);
1585 InFlag = retval.getValue(3);
1587 Chain = retval.getValue(4);
1588 InFlag = retval.getValue(5);
1591 for (unsigned j = 0; j < VecSize; ++j) {
1592 if (i + j >= NumElts)
1594 SDValue Elt = retval.getValue(j);
1596 Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
1597 InVals.push_back(Elt);
1599 Ofst += DL.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1603 SmallVector<EVT, 16> VTs;
1604 SmallVector<uint64_t, 16> Offsets;
1605 ComputePTXValueVTs(*this, DAG.getDataLayout(), retTy, VTs, &Offsets, 0);
1606 assert(VTs.size() == Ins.size() && "Bad value decomposition");
1607 unsigned RetAlign = getArgumentAlignment(Callee, CS, retTy, 0);
1608 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
1609 unsigned sz = VTs[i].getSizeInBits();
1610 unsigned AlignI = GreatestCommonDivisor64(RetAlign, Offsets[i]);
1611 bool needTruncate = sz < 8;
1612 if (VTs[i].isInteger() && (sz < 8))
1615 SmallVector<EVT, 4> LoadRetVTs;
1616 EVT TheLoadType = VTs[i];
1617 if (retTy->isIntegerTy() && DL.getTypeAllocSizeInBits(retTy) < 32) {
1618 // This is for integer types only, and specifically not for
1620 LoadRetVTs.push_back(MVT::i32);
1621 TheLoadType = MVT::i32;
1622 } else if (sz < 16) {
1623 // If loading i1/i8 result, generate
1625 // trunc i16 to i1/i8
1626 LoadRetVTs.push_back(MVT::i16);
1628 LoadRetVTs.push_back(Ins[i].VT);
1629 LoadRetVTs.push_back(MVT::Other);
1630 LoadRetVTs.push_back(MVT::Glue);
1632 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1633 DAG.getConstant(Offsets[i], dl, MVT::i32),
1635 SDValue retval = DAG.getMemIntrinsicNode(
1636 NVPTXISD::LoadParam, dl,
1637 DAG.getVTList(LoadRetVTs), LoadRetOps,
1638 TheLoadType, MachinePointerInfo(), AlignI);
1639 Chain = retval.getValue(1);
1640 InFlag = retval.getValue(2);
1641 SDValue Ret0 = retval.getValue(0);
1643 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
1644 InVals.push_back(Ret0);
1649 Chain = DAG.getCALLSEQ_END(Chain,
1650 DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1651 DAG.getIntPtrConstant(uniqueCallSite + 1, dl,
1656 // set isTailCall to false for now, until we figure out how to express
1657 // tail call optimization in PTX
1662 // By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
1663 // (see LegalizeDAG.cpp). This is slow and uses local memory.
1664 // We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
1666 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
1667 SDNode *Node = Op.getNode();
1669 SmallVector<SDValue, 8> Ops;
1670 unsigned NumOperands = Node->getNumOperands();
1671 for (unsigned i = 0; i < NumOperands; ++i) {
1672 SDValue SubOp = Node->getOperand(i);
1673 EVT VVT = SubOp.getNode()->getValueType(0);
1674 EVT EltVT = VVT.getVectorElementType();
1675 unsigned NumSubElem = VVT.getVectorNumElements();
1676 for (unsigned j = 0; j < NumSubElem; ++j) {
1677 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1678 DAG.getIntPtrConstant(j, dl)));
1681 return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
1684 /// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
1685 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1687 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1689 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
1690 SelectionDAG &DAG) const {
1691 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1692 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
1694 EVT VT = Op.getValueType();
1695 unsigned VTBits = VT.getSizeInBits();
1697 SDValue ShOpLo = Op.getOperand(0);
1698 SDValue ShOpHi = Op.getOperand(1);
1699 SDValue ShAmt = Op.getOperand(2);
1700 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
1702 if (VTBits == 32 && STI.getSmVersion() >= 35) {
1704 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1705 // {dHi, dLo} = {aHi, aLo} >> Amt
1707 // dLo = shf.r.clamp aLo, aHi, Amt
1709 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1710 SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
1713 SDValue Ops[2] = { Lo, Hi };
1714 return DAG.getMergeValues(Ops, dl);
1718 // {dHi, dLo} = {aHi, aLo} >> Amt
1719 // - if (Amt>=size) then
1720 // dLo = aHi >> (Amt-size)
1721 // dHi = aHi >> Amt (this is either all 0 or all 1)
1723 // dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
1726 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1727 DAG.getConstant(VTBits, dl, MVT::i32),
1729 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
1730 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1731 DAG.getConstant(VTBits, dl, MVT::i32));
1732 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
1733 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1734 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
1736 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1737 DAG.getConstant(VTBits, dl, MVT::i32),
1739 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1740 SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1742 SDValue Ops[2] = { Lo, Hi };
1743 return DAG.getMergeValues(Ops, dl);
1747 /// LowerShiftLeftParts - Lower SHL_PARTS, which
1748 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1750 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1752 SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
1753 SelectionDAG &DAG) const {
1754 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1755 assert(Op.getOpcode() == ISD::SHL_PARTS);
1757 EVT VT = Op.getValueType();
1758 unsigned VTBits = VT.getSizeInBits();
1760 SDValue ShOpLo = Op.getOperand(0);
1761 SDValue ShOpHi = Op.getOperand(1);
1762 SDValue ShAmt = Op.getOperand(2);
1764 if (VTBits == 32 && STI.getSmVersion() >= 35) {
1766 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1767 // {dHi, dLo} = {aHi, aLo} << Amt
1768 // dHi = shf.l.clamp aLo, aHi, Amt
1771 SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
1773 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1775 SDValue Ops[2] = { Lo, Hi };
1776 return DAG.getMergeValues(Ops, dl);
1780 // {dHi, dLo} = {aHi, aLo} << Amt
1781 // - if (Amt>=size) then
1782 // dLo = aLo << Amt (all 0)
1783 // dLo = aLo << (Amt-size)
1786 // dHi = (aHi << Amt) | (aLo >> (size-Amt))
1788 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1789 DAG.getConstant(VTBits, dl, MVT::i32),
1791 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1792 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1793 DAG.getConstant(VTBits, dl, MVT::i32));
1794 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1795 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1796 SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1798 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1799 DAG.getConstant(VTBits, dl, MVT::i32),
1801 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1802 SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1804 SDValue Ops[2] = { Lo, Hi };
1805 return DAG.getMergeValues(Ops, dl);
1810 NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1811 switch (Op.getOpcode()) {
1812 case ISD::RETURNADDR:
1814 case ISD::FRAMEADDR:
1816 case ISD::GlobalAddress:
1817 return LowerGlobalAddress(Op, DAG);
1818 case ISD::INTRINSIC_W_CHAIN:
1820 case ISD::BUILD_VECTOR:
1821 case ISD::EXTRACT_SUBVECTOR:
1823 case ISD::CONCAT_VECTORS:
1824 return LowerCONCAT_VECTORS(Op, DAG);
1826 return LowerSTORE(Op, DAG);
1828 return LowerLOAD(Op, DAG);
1829 case ISD::SHL_PARTS:
1830 return LowerShiftLeftParts(Op, DAG);
1831 case ISD::SRA_PARTS:
1832 case ISD::SRL_PARTS:
1833 return LowerShiftRightParts(Op, DAG);
1835 return LowerSelect(Op, DAG);
1837 llvm_unreachable("Custom lowering not defined for operation");
1841 SDValue NVPTXTargetLowering::LowerSelect(SDValue Op, SelectionDAG &DAG) const {
1842 SDValue Op0 = Op->getOperand(0);
1843 SDValue Op1 = Op->getOperand(1);
1844 SDValue Op2 = Op->getOperand(2);
1845 SDLoc DL(Op.getNode());
1847 assert(Op.getValueType() == MVT::i1 && "Custom lowering enabled only for i1");
1849 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
1850 Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2);
1851 SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2);
1852 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select);
1857 SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1858 if (Op.getValueType() == MVT::i1)
1859 return LowerLOADi1(Op, DAG);
1866 // v1 = ld i8* addr (-> i16)
1867 // v = trunc i16 to i1
1868 SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
1869 SDNode *Node = Op.getNode();
1870 LoadSDNode *LD = cast<LoadSDNode>(Node);
1872 assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
1873 assert(Node->getValueType(0) == MVT::i1 &&
1874 "Custom lowering for i1 load only");
1876 DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
1877 LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(),
1878 LD->isInvariant(), LD->getAlignment());
1879 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
1880 // The legalizer (the caller) is expecting two values from the legalized
1881 // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
1882 // in LegalizeDAG.cpp which also uses MergeValues.
1883 SDValue Ops[] = { result, LD->getChain() };
1884 return DAG.getMergeValues(Ops, dl);
1887 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1888 EVT ValVT = Op.getOperand(1).getValueType();
1889 if (ValVT == MVT::i1)
1890 return LowerSTOREi1(Op, DAG);
1891 else if (ValVT.isVector())
1892 return LowerSTOREVector(Op, DAG);
1898 NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
1899 SDNode *N = Op.getNode();
1900 SDValue Val = N->getOperand(1);
1902 EVT ValVT = Val.getValueType();
1904 if (ValVT.isVector()) {
1905 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
1906 // legal. We can (and should) split that into 2 stores of <2 x double> here
1907 // but I'm leaving that as a TODO for now.
1908 if (!ValVT.isSimple())
1910 switch (ValVT.getSimpleVT().SimpleTy) {
1923 // This is a "native" vector type
1927 MemSDNode *MemSD = cast<MemSDNode>(N);
1928 const DataLayout &TD = DAG.getDataLayout();
1930 unsigned Align = MemSD->getAlignment();
1931 unsigned PrefAlign =
1932 TD.getPrefTypeAlignment(ValVT.getTypeForEVT(*DAG.getContext()));
1933 if (Align < PrefAlign) {
1934 // This store is not sufficiently aligned, so bail out and let this vector
1935 // store be scalarized. Note that we may still be able to emit smaller
1936 // vector stores. For example, if we are storing a <4 x float> with an
1937 // alignment of 8, this check will fail but the legalizer will try again
1938 // with 2 x <2 x float>, which will succeed with an alignment of 8.
1942 unsigned Opcode = 0;
1943 EVT EltVT = ValVT.getVectorElementType();
1944 unsigned NumElts = ValVT.getVectorNumElements();
1946 // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
1947 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
1948 // stored type to i16 and propagate the "real" type as the memory type.
1949 bool NeedExt = false;
1950 if (EltVT.getSizeInBits() < 16)
1957 Opcode = NVPTXISD::StoreV2;
1960 Opcode = NVPTXISD::StoreV4;
1965 SmallVector<SDValue, 8> Ops;
1967 // First is the chain
1968 Ops.push_back(N->getOperand(0));
1970 // Then the split values
1971 for (unsigned i = 0; i < NumElts; ++i) {
1972 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
1973 DAG.getIntPtrConstant(i, DL));
1975 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
1976 Ops.push_back(ExtVal);
1979 // Then any remaining arguments
1980 Ops.append(N->op_begin() + 2, N->op_end());
1982 SDValue NewSt = DAG.getMemIntrinsicNode(
1983 Opcode, DL, DAG.getVTList(MVT::Other), Ops,
1984 MemSD->getMemoryVT(), MemSD->getMemOperand());
1986 //return DCI.CombineTo(N, NewSt, true);
1995 // v1 = zxt v to i16
1997 SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
1998 SDNode *Node = Op.getNode();
2000 StoreSDNode *ST = cast<StoreSDNode>(Node);
2001 SDValue Tmp1 = ST->getChain();
2002 SDValue Tmp2 = ST->getBasePtr();
2003 SDValue Tmp3 = ST->getValue();
2004 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
2005 unsigned Alignment = ST->getAlignment();
2006 bool isVolatile = ST->isVolatile();
2007 bool isNonTemporal = ST->isNonTemporal();
2008 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
2009 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
2010 ST->getPointerInfo(), MVT::i8, isNonTemporal,
2011 isVolatile, Alignment);
2015 SDValue NVPTXTargetLowering::getExtSymb(SelectionDAG &DAG, const char *inname,
2016 int idx, EVT v) const {
2017 std::string *name = nvTM->getManagedStrPool()->getManagedString(inname);
2018 std::stringstream suffix;
2020 *name += suffix.str();
2021 return DAG.getTargetExternalSymbol(name->c_str(), v);
2025 NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
2026 std::string ParamSym;
2027 raw_string_ostream ParamStr(ParamSym);
2029 ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
2032 std::string *SavedStr =
2033 nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
2034 return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
2037 SDValue NVPTXTargetLowering::getParamHelpSymbol(SelectionDAG &DAG, int idx) {
2038 return getExtSymb(DAG, ".HLPPARAM", idx);
2041 // Check to see if the kernel argument is image*_t or sampler_t
2043 bool llvm::isImageOrSamplerVal(const Value *arg, const Module *context) {
2044 static const char *const specialTypes[] = { "struct._image2d_t",
2045 "struct._image3d_t",
2046 "struct._sampler_t" };
2048 Type *Ty = arg->getType();
2049 auto *PTy = dyn_cast<PointerType>(Ty);
2057 auto *STy = dyn_cast<StructType>(PTy->getElementType());
2058 const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : "";
2060 for (int i = 0, e = array_lengthof(specialTypes); i != e; ++i)
2061 if (TypeName == specialTypes[i])
2067 SDValue NVPTXTargetLowering::LowerFormalArguments(
2068 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2069 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2070 SmallVectorImpl<SDValue> &InVals) const {
2071 MachineFunction &MF = DAG.getMachineFunction();
2072 const DataLayout &DL = DAG.getDataLayout();
2073 auto PtrVT = getPointerTy(DAG.getDataLayout());
2075 const Function *F = MF.getFunction();
2076 const AttributeSet &PAL = F->getAttributes();
2077 const TargetLowering *TLI = STI.getTargetLowering();
2079 SDValue Root = DAG.getRoot();
2080 std::vector<SDValue> OutChains;
2082 bool isKernel = llvm::isKernelFunction(*F);
2083 bool isABI = (STI.getSmVersion() >= 20);
2084 assert(isABI && "Non-ABI compilation is not supported");
2088 std::vector<Type *> argTypes;
2089 std::vector<const Argument *> theArgs;
2090 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
2092 theArgs.push_back(I);
2093 argTypes.push_back(I->getType());
2095 // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
2096 // Ins.size() will be larger
2097 // * if there is an aggregate argument with multiple fields (each field
2098 // showing up separately in Ins)
2099 // * if there is a vector argument with more than typical vector-length
2100 // elements (generally if more than 4) where each vector element is
2101 // individually present in Ins.
2102 // So a different index should be used for indexing into Ins.
2103 // See similar issue in LowerCall.
2104 unsigned InsIdx = 0;
2107 for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
2108 Type *Ty = argTypes[i];
2110 // If the kernel argument is image*_t or sampler_t, convert it to
2111 // a i32 constant holding the parameter position. This can later
2112 // matched in the AsmPrinter to output the correct mangled name.
2113 if (isImageOrSamplerVal(
2115 (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
2117 assert(isKernel && "Only kernels can have image/sampler params");
2118 InVals.push_back(DAG.getConstant(i + 1, dl, MVT::i32));
2122 if (theArgs[i]->use_empty()) {
2124 if (Ty->isAggregateType()) {
2125 SmallVector<EVT, 16> vtparts;
2127 ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts);
2128 assert(vtparts.size() > 0 && "empty aggregate type not expected");
2129 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2131 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2134 if (vtparts.size() > 0)
2138 if (Ty->isVectorTy()) {
2139 EVT ObjectVT = getValueType(DL, Ty);
2140 unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
2141 for (unsigned parti = 0; parti < NumRegs; ++parti) {
2142 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2149 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2153 // In the following cases, assign a node order of "idx+1"
2154 // to newly created nodes. The SDNodes for params have to
2155 // appear in the same order as their order of appearance
2156 // in the original function. "idx+1" holds that order.
2157 if (!PAL.hasAttribute(i + 1, Attribute::ByVal)) {
2158 if (Ty->isAggregateType()) {
2159 SmallVector<EVT, 16> vtparts;
2160 SmallVector<uint64_t, 16> offsets;
2162 // NOTE: Here, we lose the ability to issue vector loads for vectors
2163 // that are a part of a struct. This should be investigated in the
2165 ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts, &offsets,
2167 assert(vtparts.size() > 0 && "empty aggregate type not expected");
2168 bool aggregateIsPacked = false;
2169 if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
2170 aggregateIsPacked = STy->isPacked();
2172 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2173 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2175 EVT partVT = vtparts[parti];
2176 Value *srcValue = Constant::getNullValue(
2177 PointerType::get(partVT.getTypeForEVT(F->getContext()),
2178 llvm::ADDRESS_SPACE_PARAM));
2180 DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
2181 DAG.getConstant(offsets[parti], dl, PtrVT));
2182 unsigned partAlign = aggregateIsPacked
2184 : DL.getABITypeAlignment(
2185 partVT.getTypeForEVT(F->getContext()));
2187 if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
2188 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
2189 ISD::SEXTLOAD : ISD::ZEXTLOAD;
2190 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
2191 MachinePointerInfo(srcValue), partVT, false,
2192 false, false, partAlign);
2194 p = DAG.getLoad(partVT, dl, Root, srcAddr,
2195 MachinePointerInfo(srcValue), false, false, false,
2199 p.getNode()->setIROrder(idx + 1);
2200 InVals.push_back(p);
2203 if (vtparts.size() > 0)
2207 if (Ty->isVectorTy()) {
2208 EVT ObjectVT = getValueType(DL, Ty);
2209 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2210 unsigned NumElts = ObjectVT.getVectorNumElements();
2211 assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
2212 "Vector was not scalarized");
2213 EVT EltVT = ObjectVT.getVectorElementType();
2218 // We only have one element, so just directly load it
2219 Value *SrcValue = Constant::getNullValue(PointerType::get(
2220 EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2221 SDValue P = DAG.getLoad(
2222 EltVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false, false,
2224 DL.getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
2226 P.getNode()->setIROrder(idx + 1);
2228 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
2229 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
2230 InVals.push_back(P);
2232 } else if (NumElts == 2) {
2234 // f32,f32 = load ...
2235 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
2236 Value *SrcValue = Constant::getNullValue(PointerType::get(
2237 VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2238 SDValue P = DAG.getLoad(
2239 VecVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false, false,
2241 DL.getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
2243 P.getNode()->setIROrder(idx + 1);
2245 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2246 DAG.getIntPtrConstant(0, dl));
2247 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2248 DAG.getIntPtrConstant(1, dl));
2250 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
2251 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
2252 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
2255 InVals.push_back(Elt0);
2256 InVals.push_back(Elt1);
2260 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
2262 // vector will be expanded to a power of 2 elements, so we know we can
2263 // always round up to the next multiple of 4 when creating the vector
2265 // e.g. 4 elem => 1 ld.v4
2266 // 6 elem => 2 ld.v4
2267 // 8 elem => 2 ld.v4
2268 // 11 elem => 3 ld.v4
2269 unsigned VecSize = 4;
2270 if (EltVT.getSizeInBits() == 64) {
2273 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
2275 for (unsigned i = 0; i < NumElts; i += VecSize) {
2276 Value *SrcValue = Constant::getNullValue(
2277 PointerType::get(VecVT.getTypeForEVT(F->getContext()),
2278 llvm::ADDRESS_SPACE_PARAM));
2279 SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
2280 DAG.getConstant(Ofst, dl, PtrVT));
2281 SDValue P = DAG.getLoad(
2282 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
2284 DL.getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
2286 P.getNode()->setIROrder(idx + 1);
2288 for (unsigned j = 0; j < VecSize; ++j) {
2289 if (i + j >= NumElts)
2291 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2292 DAG.getIntPtrConstant(j, dl));
2293 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
2294 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
2295 InVals.push_back(Elt);
2297 Ofst += DL.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2307 EVT ObjectVT = getValueType(DL, Ty);
2308 // If ABI, load from the param symbol
2309 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2310 Value *srcValue = Constant::getNullValue(PointerType::get(
2311 ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2313 if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
2314 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
2315 ISD::SEXTLOAD : ISD::ZEXTLOAD;
2317 ExtOp, dl, Ins[InsIdx].VT, Root, Arg, MachinePointerInfo(srcValue),
2318 ObjectVT, false, false, false,
2319 DL.getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
2322 Ins[InsIdx].VT, dl, Root, Arg, MachinePointerInfo(srcValue), false,
2324 DL.getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
2327 p.getNode()->setIROrder(idx + 1);
2328 InVals.push_back(p);
2332 // Param has ByVal attribute
2333 // Return MoveParam(param symbol).
2334 // Ideally, the param symbol can be returned directly,
2335 // but when SDNode builder decides to use it in a CopyToReg(),
2336 // machine instruction fails because TargetExternalSymbol
2337 // (not lowered) is target dependent, and CopyToReg assumes
2338 // the source is lowered.
2339 EVT ObjectVT = getValueType(DL, Ty);
2340 assert(ObjectVT == Ins[InsIdx].VT &&
2341 "Ins type did not match function type");
2342 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2343 SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
2345 p.getNode()->setIROrder(idx + 1);
2347 InVals.push_back(p);
2349 SDValue p2 = DAG.getNode(
2350 ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
2351 DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, dl, MVT::i32), p);
2352 InVals.push_back(p2);
2356 // Clang will check explicit VarArg and issue error if any. However, Clang
2357 // will let code with
2358 // implicit var arg like f() pass. See bug 617733.
2359 // We treat this case as if the arg list is empty.
2360 // if (F.isVarArg()) {
2361 // assert(0 && "VarArg not supported yet!");
2364 if (!OutChains.empty())
2365 DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
2372 NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2374 const SmallVectorImpl<ISD::OutputArg> &Outs,
2375 const SmallVectorImpl<SDValue> &OutVals,
2376 SDLoc dl, SelectionDAG &DAG) const {
2377 MachineFunction &MF = DAG.getMachineFunction();
2378 const Function *F = MF.getFunction();
2379 Type *RetTy = F->getReturnType();
2380 const DataLayout &TD = DAG.getDataLayout();
2382 bool isABI = (STI.getSmVersion() >= 20);
2383 assert(isABI && "Non-ABI compilation is not supported");
2387 if (VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
2388 // If we have a vector type, the OutVals array will be the scalarized
2389 // components and we have combine them into 1 or more vector stores.
2390 unsigned NumElts = VTy->getNumElements();
2391 assert(NumElts == Outs.size() && "Bad scalarization of return value");
2393 // const_cast can be removed in later LLVM versions
2394 EVT EltVT = getValueType(TD, RetTy).getVectorElementType();
2395 bool NeedExtend = false;
2396 if (EltVT.getSizeInBits() < 16)
2401 SDValue StoreVal = OutVals[0];
2402 // We only have one element, so just directly store it
2404 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
2405 SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal };
2406 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
2407 DAG.getVTList(MVT::Other), Ops,
2408 EltVT, MachinePointerInfo());
2410 } else if (NumElts == 2) {
2412 SDValue StoreVal0 = OutVals[0];
2413 SDValue StoreVal1 = OutVals[1];
2416 StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal0);
2417 StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
2420 SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal0,
2422 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
2423 DAG.getVTList(MVT::Other), Ops,
2424 EltVT, MachinePointerInfo());
2427 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
2428 // vector will be expanded to a power of 2 elements, so we know we can
2429 // always round up to the next multiple of 4 when creating the vector
2431 // e.g. 4 elem => 1 st.v4
2432 // 6 elem => 2 st.v4
2433 // 8 elem => 2 st.v4
2434 // 11 elem => 3 st.v4
2436 unsigned VecSize = 4;
2437 if (OutVals[0].getValueType().getSizeInBits() == 64)
2440 unsigned Offset = 0;
2443 EVT::getVectorVT(F->getContext(), EltVT, VecSize);
2444 unsigned PerStoreOffset =
2445 TD.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2447 for (unsigned i = 0; i < NumElts; i += VecSize) {
2450 SmallVector<SDValue, 8> Ops;
2451 Ops.push_back(Chain);
2452 Ops.push_back(DAG.getConstant(Offset, dl, MVT::i32));
2453 unsigned Opc = NVPTXISD::StoreRetvalV2;
2454 EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
2456 StoreVal = OutVals[i];
2458 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2459 Ops.push_back(StoreVal);
2461 if (i + 1 < NumElts) {
2462 StoreVal = OutVals[i + 1];
2464 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2466 StoreVal = DAG.getUNDEF(ExtendedVT);
2468 Ops.push_back(StoreVal);
2471 Opc = NVPTXISD::StoreRetvalV4;
2472 if (i + 2 < NumElts) {
2473 StoreVal = OutVals[i + 2];
2476 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2478 StoreVal = DAG.getUNDEF(ExtendedVT);
2480 Ops.push_back(StoreVal);
2482 if (i + 3 < NumElts) {
2483 StoreVal = OutVals[i + 3];
2486 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2488 StoreVal = DAG.getUNDEF(ExtendedVT);
2490 Ops.push_back(StoreVal);
2493 // Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
2495 DAG.getMemIntrinsicNode(Opc, dl, DAG.getVTList(MVT::Other), Ops,
2496 EltVT, MachinePointerInfo());
2497 Offset += PerStoreOffset;
2501 SmallVector<EVT, 16> ValVTs;
2502 SmallVector<uint64_t, 16> Offsets;
2503 ComputePTXValueVTs(*this, DAG.getDataLayout(), RetTy, ValVTs, &Offsets, 0);
2504 assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
2506 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
2507 SDValue theVal = OutVals[i];
2508 EVT TheValType = theVal.getValueType();
2509 unsigned numElems = 1;
2510 if (TheValType.isVector())
2511 numElems = TheValType.getVectorNumElements();
2512 for (unsigned j = 0, je = numElems; j != je; ++j) {
2513 SDValue TmpVal = theVal;
2514 if (TheValType.isVector())
2515 TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2516 TheValType.getVectorElementType(), TmpVal,
2517 DAG.getIntPtrConstant(j, dl));
2518 EVT TheStoreType = ValVTs[i];
2519 if (RetTy->isIntegerTy() && TD.getTypeAllocSizeInBits(RetTy) < 32) {
2520 // The following zero-extension is for integer types only, and
2521 // specifically not for aggregates.
2522 TmpVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, TmpVal);
2523 TheStoreType = MVT::i32;
2525 else if (TmpVal.getValueType().getSizeInBits() < 16)
2526 TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal);
2530 DAG.getConstant(Offsets[i], dl, MVT::i32),
2532 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
2533 DAG.getVTList(MVT::Other), Ops,
2535 MachinePointerInfo());
2540 return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
2544 void NVPTXTargetLowering::LowerAsmOperandForConstraint(
2545 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2546 SelectionDAG &DAG) const {
2547 if (Constraint.length() > 1)
2550 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2553 // NVPTX suuport vector of legal types of any length in Intrinsics because the
2554 // NVPTX specific type legalizer
2555 // will legalize them to the PTX supported length.
2556 bool NVPTXTargetLowering::isTypeSupportedInIntrinsic(MVT VT) const {
2557 if (isTypeLegal(VT))
2559 if (VT.isVector()) {
2560 MVT eVT = VT.getVectorElementType();
2561 if (isTypeLegal(eVT))
2567 static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2568 switch (Intrinsic) {
2572 case Intrinsic::nvvm_tex_1d_v4f32_s32:
2573 return NVPTXISD::Tex1DFloatS32;
2574 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2575 return NVPTXISD::Tex1DFloatFloat;
2576 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2577 return NVPTXISD::Tex1DFloatFloatLevel;
2578 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2579 return NVPTXISD::Tex1DFloatFloatGrad;
2580 case Intrinsic::nvvm_tex_1d_v4s32_s32:
2581 return NVPTXISD::Tex1DS32S32;
2582 case Intrinsic::nvvm_tex_1d_v4s32_f32:
2583 return NVPTXISD::Tex1DS32Float;
2584 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
2585 return NVPTXISD::Tex1DS32FloatLevel;
2586 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
2587 return NVPTXISD::Tex1DS32FloatGrad;
2588 case Intrinsic::nvvm_tex_1d_v4u32_s32:
2589 return NVPTXISD::Tex1DU32S32;
2590 case Intrinsic::nvvm_tex_1d_v4u32_f32:
2591 return NVPTXISD::Tex1DU32Float;
2592 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
2593 return NVPTXISD::Tex1DU32FloatLevel;
2594 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
2595 return NVPTXISD::Tex1DU32FloatGrad;
2597 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
2598 return NVPTXISD::Tex1DArrayFloatS32;
2599 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2600 return NVPTXISD::Tex1DArrayFloatFloat;
2601 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2602 return NVPTXISD::Tex1DArrayFloatFloatLevel;
2603 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2604 return NVPTXISD::Tex1DArrayFloatFloatGrad;
2605 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
2606 return NVPTXISD::Tex1DArrayS32S32;
2607 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
2608 return NVPTXISD::Tex1DArrayS32Float;
2609 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
2610 return NVPTXISD::Tex1DArrayS32FloatLevel;
2611 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
2612 return NVPTXISD::Tex1DArrayS32FloatGrad;
2613 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
2614 return NVPTXISD::Tex1DArrayU32S32;
2615 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
2616 return NVPTXISD::Tex1DArrayU32Float;
2617 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
2618 return NVPTXISD::Tex1DArrayU32FloatLevel;
2619 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
2620 return NVPTXISD::Tex1DArrayU32FloatGrad;
2622 case Intrinsic::nvvm_tex_2d_v4f32_s32:
2623 return NVPTXISD::Tex2DFloatS32;
2624 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2625 return NVPTXISD::Tex2DFloatFloat;
2626 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2627 return NVPTXISD::Tex2DFloatFloatLevel;
2628 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2629 return NVPTXISD::Tex2DFloatFloatGrad;
2630 case Intrinsic::nvvm_tex_2d_v4s32_s32:
2631 return NVPTXISD::Tex2DS32S32;
2632 case Intrinsic::nvvm_tex_2d_v4s32_f32:
2633 return NVPTXISD::Tex2DS32Float;
2634 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
2635 return NVPTXISD::Tex2DS32FloatLevel;
2636 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
2637 return NVPTXISD::Tex2DS32FloatGrad;
2638 case Intrinsic::nvvm_tex_2d_v4u32_s32:
2639 return NVPTXISD::Tex2DU32S32;
2640 case Intrinsic::nvvm_tex_2d_v4u32_f32:
2641 return NVPTXISD::Tex2DU32Float;
2642 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
2643 return NVPTXISD::Tex2DU32FloatLevel;
2644 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
2645 return NVPTXISD::Tex2DU32FloatGrad;
2647 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
2648 return NVPTXISD::Tex2DArrayFloatS32;
2649 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2650 return NVPTXISD::Tex2DArrayFloatFloat;
2651 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2652 return NVPTXISD::Tex2DArrayFloatFloatLevel;
2653 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2654 return NVPTXISD::Tex2DArrayFloatFloatGrad;
2655 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
2656 return NVPTXISD::Tex2DArrayS32S32;
2657 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
2658 return NVPTXISD::Tex2DArrayS32Float;
2659 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
2660 return NVPTXISD::Tex2DArrayS32FloatLevel;
2661 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
2662 return NVPTXISD::Tex2DArrayS32FloatGrad;
2663 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
2664 return NVPTXISD::Tex2DArrayU32S32;
2665 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
2666 return NVPTXISD::Tex2DArrayU32Float;
2667 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
2668 return NVPTXISD::Tex2DArrayU32FloatLevel;
2669 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
2670 return NVPTXISD::Tex2DArrayU32FloatGrad;
2672 case Intrinsic::nvvm_tex_3d_v4f32_s32:
2673 return NVPTXISD::Tex3DFloatS32;
2674 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2675 return NVPTXISD::Tex3DFloatFloat;
2676 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2677 return NVPTXISD::Tex3DFloatFloatLevel;
2678 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2679 return NVPTXISD::Tex3DFloatFloatGrad;
2680 case Intrinsic::nvvm_tex_3d_v4s32_s32:
2681 return NVPTXISD::Tex3DS32S32;
2682 case Intrinsic::nvvm_tex_3d_v4s32_f32:
2683 return NVPTXISD::Tex3DS32Float;
2684 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
2685 return NVPTXISD::Tex3DS32FloatLevel;
2686 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
2687 return NVPTXISD::Tex3DS32FloatGrad;
2688 case Intrinsic::nvvm_tex_3d_v4u32_s32:
2689 return NVPTXISD::Tex3DU32S32;
2690 case Intrinsic::nvvm_tex_3d_v4u32_f32:
2691 return NVPTXISD::Tex3DU32Float;
2692 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
2693 return NVPTXISD::Tex3DU32FloatLevel;
2694 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
2695 return NVPTXISD::Tex3DU32FloatGrad;
2697 case Intrinsic::nvvm_tex_cube_v4f32_f32:
2698 return NVPTXISD::TexCubeFloatFloat;
2699 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
2700 return NVPTXISD::TexCubeFloatFloatLevel;
2701 case Intrinsic::nvvm_tex_cube_v4s32_f32:
2702 return NVPTXISD::TexCubeS32Float;
2703 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
2704 return NVPTXISD::TexCubeS32FloatLevel;
2705 case Intrinsic::nvvm_tex_cube_v4u32_f32:
2706 return NVPTXISD::TexCubeU32Float;
2707 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
2708 return NVPTXISD::TexCubeU32FloatLevel;
2710 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
2711 return NVPTXISD::TexCubeArrayFloatFloat;
2712 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
2713 return NVPTXISD::TexCubeArrayFloatFloatLevel;
2714 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
2715 return NVPTXISD::TexCubeArrayS32Float;
2716 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
2717 return NVPTXISD::TexCubeArrayS32FloatLevel;
2718 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
2719 return NVPTXISD::TexCubeArrayU32Float;
2720 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
2721 return NVPTXISD::TexCubeArrayU32FloatLevel;
2723 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
2724 return NVPTXISD::Tld4R2DFloatFloat;
2725 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
2726 return NVPTXISD::Tld4G2DFloatFloat;
2727 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
2728 return NVPTXISD::Tld4B2DFloatFloat;
2729 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
2730 return NVPTXISD::Tld4A2DFloatFloat;
2731 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
2732 return NVPTXISD::Tld4R2DS64Float;
2733 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
2734 return NVPTXISD::Tld4G2DS64Float;
2735 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
2736 return NVPTXISD::Tld4B2DS64Float;
2737 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
2738 return NVPTXISD::Tld4A2DS64Float;
2739 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
2740 return NVPTXISD::Tld4R2DU64Float;
2741 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
2742 return NVPTXISD::Tld4G2DU64Float;
2743 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
2744 return NVPTXISD::Tld4B2DU64Float;
2745 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
2746 return NVPTXISD::Tld4A2DU64Float;
2748 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
2749 return NVPTXISD::TexUnified1DFloatS32;
2750 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
2751 return NVPTXISD::TexUnified1DFloatFloat;
2752 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
2753 return NVPTXISD::TexUnified1DFloatFloatLevel;
2754 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
2755 return NVPTXISD::TexUnified1DFloatFloatGrad;
2756 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
2757 return NVPTXISD::TexUnified1DS32S32;
2758 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
2759 return NVPTXISD::TexUnified1DS32Float;
2760 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
2761 return NVPTXISD::TexUnified1DS32FloatLevel;
2762 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
2763 return NVPTXISD::TexUnified1DS32FloatGrad;
2764 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
2765 return NVPTXISD::TexUnified1DU32S32;
2766 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
2767 return NVPTXISD::TexUnified1DU32Float;
2768 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
2769 return NVPTXISD::TexUnified1DU32FloatLevel;
2770 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
2771 return NVPTXISD::TexUnified1DU32FloatGrad;
2773 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
2774 return NVPTXISD::TexUnified1DArrayFloatS32;
2775 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
2776 return NVPTXISD::TexUnified1DArrayFloatFloat;
2777 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
2778 return NVPTXISD::TexUnified1DArrayFloatFloatLevel;
2779 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
2780 return NVPTXISD::TexUnified1DArrayFloatFloatGrad;
2781 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
2782 return NVPTXISD::TexUnified1DArrayS32S32;
2783 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
2784 return NVPTXISD::TexUnified1DArrayS32Float;
2785 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
2786 return NVPTXISD::TexUnified1DArrayS32FloatLevel;
2787 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
2788 return NVPTXISD::TexUnified1DArrayS32FloatGrad;
2789 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
2790 return NVPTXISD::TexUnified1DArrayU32S32;
2791 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
2792 return NVPTXISD::TexUnified1DArrayU32Float;
2793 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
2794 return NVPTXISD::TexUnified1DArrayU32FloatLevel;
2795 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
2796 return NVPTXISD::TexUnified1DArrayU32FloatGrad;
2798 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
2799 return NVPTXISD::TexUnified2DFloatS32;
2800 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
2801 return NVPTXISD::TexUnified2DFloatFloat;
2802 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
2803 return NVPTXISD::TexUnified2DFloatFloatLevel;
2804 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
2805 return NVPTXISD::TexUnified2DFloatFloatGrad;
2806 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
2807 return NVPTXISD::TexUnified2DS32S32;
2808 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
2809 return NVPTXISD::TexUnified2DS32Float;
2810 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
2811 return NVPTXISD::TexUnified2DS32FloatLevel;
2812 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
2813 return NVPTXISD::TexUnified2DS32FloatGrad;
2814 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
2815 return NVPTXISD::TexUnified2DU32S32;
2816 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
2817 return NVPTXISD::TexUnified2DU32Float;
2818 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
2819 return NVPTXISD::TexUnified2DU32FloatLevel;
2820 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
2821 return NVPTXISD::TexUnified2DU32FloatGrad;
2823 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
2824 return NVPTXISD::TexUnified2DArrayFloatS32;
2825 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
2826 return NVPTXISD::TexUnified2DArrayFloatFloat;
2827 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
2828 return NVPTXISD::TexUnified2DArrayFloatFloatLevel;
2829 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
2830 return NVPTXISD::TexUnified2DArrayFloatFloatGrad;
2831 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
2832 return NVPTXISD::TexUnified2DArrayS32S32;
2833 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
2834 return NVPTXISD::TexUnified2DArrayS32Float;
2835 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
2836 return NVPTXISD::TexUnified2DArrayS32FloatLevel;
2837 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
2838 return NVPTXISD::TexUnified2DArrayS32FloatGrad;
2839 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
2840 return NVPTXISD::TexUnified2DArrayU32S32;
2841 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
2842 return NVPTXISD::TexUnified2DArrayU32Float;
2843 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
2844 return NVPTXISD::TexUnified2DArrayU32FloatLevel;
2845 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
2846 return NVPTXISD::TexUnified2DArrayU32FloatGrad;
2848 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
2849 return NVPTXISD::TexUnified3DFloatS32;
2850 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
2851 return NVPTXISD::TexUnified3DFloatFloat;
2852 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
2853 return NVPTXISD::TexUnified3DFloatFloatLevel;
2854 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
2855 return NVPTXISD::TexUnified3DFloatFloatGrad;
2856 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
2857 return NVPTXISD::TexUnified3DS32S32;
2858 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
2859 return NVPTXISD::TexUnified3DS32Float;
2860 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
2861 return NVPTXISD::TexUnified3DS32FloatLevel;
2862 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
2863 return NVPTXISD::TexUnified3DS32FloatGrad;
2864 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
2865 return NVPTXISD::TexUnified3DU32S32;
2866 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
2867 return NVPTXISD::TexUnified3DU32Float;
2868 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
2869 return NVPTXISD::TexUnified3DU32FloatLevel;
2870 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
2871 return NVPTXISD::TexUnified3DU32FloatGrad;
2873 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
2874 return NVPTXISD::TexUnifiedCubeFloatFloat;
2875 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
2876 return NVPTXISD::TexUnifiedCubeFloatFloatLevel;
2877 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
2878 return NVPTXISD::TexUnifiedCubeS32Float;
2879 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
2880 return NVPTXISD::TexUnifiedCubeS32FloatLevel;
2881 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
2882 return NVPTXISD::TexUnifiedCubeU32Float;
2883 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
2884 return NVPTXISD::TexUnifiedCubeU32FloatLevel;
2886 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
2887 return NVPTXISD::TexUnifiedCubeArrayFloatFloat;
2888 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
2889 return NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel;
2890 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
2891 return NVPTXISD::TexUnifiedCubeArrayS32Float;
2892 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
2893 return NVPTXISD::TexUnifiedCubeArrayS32FloatLevel;
2894 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
2895 return NVPTXISD::TexUnifiedCubeArrayU32Float;
2896 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
2897 return NVPTXISD::TexUnifiedCubeArrayU32FloatLevel;
2899 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
2900 return NVPTXISD::Tld4UnifiedR2DFloatFloat;
2901 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
2902 return NVPTXISD::Tld4UnifiedG2DFloatFloat;
2903 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
2904 return NVPTXISD::Tld4UnifiedB2DFloatFloat;
2905 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
2906 return NVPTXISD::Tld4UnifiedA2DFloatFloat;
2907 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
2908 return NVPTXISD::Tld4UnifiedR2DS64Float;
2909 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
2910 return NVPTXISD::Tld4UnifiedG2DS64Float;
2911 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
2912 return NVPTXISD::Tld4UnifiedB2DS64Float;
2913 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
2914 return NVPTXISD::Tld4UnifiedA2DS64Float;
2915 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
2916 return NVPTXISD::Tld4UnifiedR2DU64Float;
2917 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
2918 return NVPTXISD::Tld4UnifiedG2DU64Float;
2919 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
2920 return NVPTXISD::Tld4UnifiedB2DU64Float;
2921 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
2922 return NVPTXISD::Tld4UnifiedA2DU64Float;
2926 static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
2927 switch (Intrinsic) {
2930 case Intrinsic::nvvm_suld_1d_i8_clamp:
2931 return NVPTXISD::Suld1DI8Clamp;
2932 case Intrinsic::nvvm_suld_1d_i16_clamp:
2933 return NVPTXISD::Suld1DI16Clamp;
2934 case Intrinsic::nvvm_suld_1d_i32_clamp:
2935 return NVPTXISD::Suld1DI32Clamp;
2936 case Intrinsic::nvvm_suld_1d_i64_clamp:
2937 return NVPTXISD::Suld1DI64Clamp;
2938 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
2939 return NVPTXISD::Suld1DV2I8Clamp;
2940 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
2941 return NVPTXISD::Suld1DV2I16Clamp;
2942 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
2943 return NVPTXISD::Suld1DV2I32Clamp;
2944 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
2945 return NVPTXISD::Suld1DV2I64Clamp;
2946 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
2947 return NVPTXISD::Suld1DV4I8Clamp;
2948 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
2949 return NVPTXISD::Suld1DV4I16Clamp;
2950 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
2951 return NVPTXISD::Suld1DV4I32Clamp;
2952 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
2953 return NVPTXISD::Suld1DArrayI8Clamp;
2954 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
2955 return NVPTXISD::Suld1DArrayI16Clamp;
2956 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
2957 return NVPTXISD::Suld1DArrayI32Clamp;
2958 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
2959 return NVPTXISD::Suld1DArrayI64Clamp;
2960 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
2961 return NVPTXISD::Suld1DArrayV2I8Clamp;
2962 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
2963 return NVPTXISD::Suld1DArrayV2I16Clamp;
2964 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
2965 return NVPTXISD::Suld1DArrayV2I32Clamp;
2966 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
2967 return NVPTXISD::Suld1DArrayV2I64Clamp;
2968 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
2969 return NVPTXISD::Suld1DArrayV4I8Clamp;
2970 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
2971 return NVPTXISD::Suld1DArrayV4I16Clamp;
2972 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
2973 return NVPTXISD::Suld1DArrayV4I32Clamp;
2974 case Intrinsic::nvvm_suld_2d_i8_clamp:
2975 return NVPTXISD::Suld2DI8Clamp;
2976 case Intrinsic::nvvm_suld_2d_i16_clamp:
2977 return NVPTXISD::Suld2DI16Clamp;
2978 case Intrinsic::nvvm_suld_2d_i32_clamp:
2979 return NVPTXISD::Suld2DI32Clamp;
2980 case Intrinsic::nvvm_suld_2d_i64_clamp:
2981 return NVPTXISD::Suld2DI64Clamp;
2982 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
2983 return NVPTXISD::Suld2DV2I8Clamp;
2984 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
2985 return NVPTXISD::Suld2DV2I16Clamp;
2986 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
2987 return NVPTXISD::Suld2DV2I32Clamp;
2988 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
2989 return NVPTXISD::Suld2DV2I64Clamp;
2990 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
2991 return NVPTXISD::Suld2DV4I8Clamp;
2992 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
2993 return NVPTXISD::Suld2DV4I16Clamp;
2994 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
2995 return NVPTXISD::Suld2DV4I32Clamp;
2996 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
2997 return NVPTXISD::Suld2DArrayI8Clamp;
2998 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
2999 return NVPTXISD::Suld2DArrayI16Clamp;
3000 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3001 return NVPTXISD::Suld2DArrayI32Clamp;
3002 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3003 return NVPTXISD::Suld2DArrayI64Clamp;
3004 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3005 return NVPTXISD::Suld2DArrayV2I8Clamp;
3006 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3007 return NVPTXISD::Suld2DArrayV2I16Clamp;
3008 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3009 return NVPTXISD::Suld2DArrayV2I32Clamp;
3010 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3011 return NVPTXISD::Suld2DArrayV2I64Clamp;
3012 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3013 return NVPTXISD::Suld2DArrayV4I8Clamp;
3014 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3015 return NVPTXISD::Suld2DArrayV4I16Clamp;
3016 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3017 return NVPTXISD::Suld2DArrayV4I32Clamp;
3018 case Intrinsic::nvvm_suld_3d_i8_clamp:
3019 return NVPTXISD::Suld3DI8Clamp;
3020 case Intrinsic::nvvm_suld_3d_i16_clamp:
3021 return NVPTXISD::Suld3DI16Clamp;
3022 case Intrinsic::nvvm_suld_3d_i32_clamp:
3023 return NVPTXISD::Suld3DI32Clamp;
3024 case Intrinsic::nvvm_suld_3d_i64_clamp:
3025 return NVPTXISD::Suld3DI64Clamp;
3026 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3027 return NVPTXISD::Suld3DV2I8Clamp;
3028 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3029 return NVPTXISD::Suld3DV2I16Clamp;
3030 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3031 return NVPTXISD::Suld3DV2I32Clamp;
3032 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3033 return NVPTXISD::Suld3DV2I64Clamp;
3034 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3035 return NVPTXISD::Suld3DV4I8Clamp;
3036 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3037 return NVPTXISD::Suld3DV4I16Clamp;
3038 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3039 return NVPTXISD::Suld3DV4I32Clamp;
3040 case Intrinsic::nvvm_suld_1d_i8_trap:
3041 return NVPTXISD::Suld1DI8Trap;
3042 case Intrinsic::nvvm_suld_1d_i16_trap:
3043 return NVPTXISD::Suld1DI16Trap;
3044 case Intrinsic::nvvm_suld_1d_i32_trap:
3045 return NVPTXISD::Suld1DI32Trap;
3046 case Intrinsic::nvvm_suld_1d_i64_trap:
3047 return NVPTXISD::Suld1DI64Trap;
3048 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3049 return NVPTXISD::Suld1DV2I8Trap;
3050 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3051 return NVPTXISD::Suld1DV2I16Trap;
3052 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3053 return NVPTXISD::Suld1DV2I32Trap;
3054 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3055 return NVPTXISD::Suld1DV2I64Trap;
3056 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3057 return NVPTXISD::Suld1DV4I8Trap;
3058 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3059 return NVPTXISD::Suld1DV4I16Trap;
3060 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3061 return NVPTXISD::Suld1DV4I32Trap;
3062 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3063 return NVPTXISD::Suld1DArrayI8Trap;
3064 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3065 return NVPTXISD::Suld1DArrayI16Trap;
3066 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3067 return NVPTXISD::Suld1DArrayI32Trap;
3068 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3069 return NVPTXISD::Suld1DArrayI64Trap;
3070 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3071 return NVPTXISD::Suld1DArrayV2I8Trap;
3072 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3073 return NVPTXISD::Suld1DArrayV2I16Trap;
3074 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3075 return NVPTXISD::Suld1DArrayV2I32Trap;
3076 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3077 return NVPTXISD::Suld1DArrayV2I64Trap;
3078 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3079 return NVPTXISD::Suld1DArrayV4I8Trap;
3080 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3081 return NVPTXISD::Suld1DArrayV4I16Trap;
3082 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3083 return NVPTXISD::Suld1DArrayV4I32Trap;
3084 case Intrinsic::nvvm_suld_2d_i8_trap:
3085 return NVPTXISD::Suld2DI8Trap;
3086 case Intrinsic::nvvm_suld_2d_i16_trap:
3087 return NVPTXISD::Suld2DI16Trap;
3088 case Intrinsic::nvvm_suld_2d_i32_trap:
3089 return NVPTXISD::Suld2DI32Trap;
3090 case Intrinsic::nvvm_suld_2d_i64_trap:
3091 return NVPTXISD::Suld2DI64Trap;
3092 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3093 return NVPTXISD::Suld2DV2I8Trap;
3094 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3095 return NVPTXISD::Suld2DV2I16Trap;
3096 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3097 return NVPTXISD::Suld2DV2I32Trap;
3098 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3099 return NVPTXISD::Suld2DV2I64Trap;
3100 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3101 return NVPTXISD::Suld2DV4I8Trap;
3102 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3103 return NVPTXISD::Suld2DV4I16Trap;
3104 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3105 return NVPTXISD::Suld2DV4I32Trap;
3106 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3107 return NVPTXISD::Suld2DArrayI8Trap;
3108 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3109 return NVPTXISD::Suld2DArrayI16Trap;
3110 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3111 return NVPTXISD::Suld2DArrayI32Trap;
3112 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3113 return NVPTXISD::Suld2DArrayI64Trap;
3114 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3115 return NVPTXISD::Suld2DArrayV2I8Trap;
3116 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3117 return NVPTXISD::Suld2DArrayV2I16Trap;
3118 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3119 return NVPTXISD::Suld2DArrayV2I32Trap;
3120 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3121 return NVPTXISD::Suld2DArrayV2I64Trap;
3122 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3123 return NVPTXISD::Suld2DArrayV4I8Trap;
3124 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3125 return NVPTXISD::Suld2DArrayV4I16Trap;
3126 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3127 return NVPTXISD::Suld2DArrayV4I32Trap;
3128 case Intrinsic::nvvm_suld_3d_i8_trap:
3129 return NVPTXISD::Suld3DI8Trap;
3130 case Intrinsic::nvvm_suld_3d_i16_trap:
3131 return NVPTXISD::Suld3DI16Trap;
3132 case Intrinsic::nvvm_suld_3d_i32_trap:
3133 return NVPTXISD::Suld3DI32Trap;
3134 case Intrinsic::nvvm_suld_3d_i64_trap:
3135 return NVPTXISD::Suld3DI64Trap;
3136 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3137 return NVPTXISD::Suld3DV2I8Trap;
3138 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3139 return NVPTXISD::Suld3DV2I16Trap;
3140 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3141 return NVPTXISD::Suld3DV2I32Trap;
3142 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3143 return NVPTXISD::Suld3DV2I64Trap;
3144 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3145 return NVPTXISD::Suld3DV4I8Trap;
3146 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3147 return NVPTXISD::Suld3DV4I16Trap;
3148 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3149 return NVPTXISD::Suld3DV4I32Trap;
3150 case Intrinsic::nvvm_suld_1d_i8_zero:
3151 return NVPTXISD::Suld1DI8Zero;
3152 case Intrinsic::nvvm_suld_1d_i16_zero:
3153 return NVPTXISD::Suld1DI16Zero;
3154 case Intrinsic::nvvm_suld_1d_i32_zero:
3155 return NVPTXISD::Suld1DI32Zero;
3156 case Intrinsic::nvvm_suld_1d_i64_zero:
3157 return NVPTXISD::Suld1DI64Zero;
3158 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3159 return NVPTXISD::Suld1DV2I8Zero;
3160 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3161 return NVPTXISD::Suld1DV2I16Zero;
3162 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3163 return NVPTXISD::Suld1DV2I32Zero;
3164 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3165 return NVPTXISD::Suld1DV2I64Zero;
3166 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3167 return NVPTXISD::Suld1DV4I8Zero;
3168 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3169 return NVPTXISD::Suld1DV4I16Zero;
3170 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3171 return NVPTXISD::Suld1DV4I32Zero;
3172 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3173 return NVPTXISD::Suld1DArrayI8Zero;
3174 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3175 return NVPTXISD::Suld1DArrayI16Zero;
3176 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3177 return NVPTXISD::Suld1DArrayI32Zero;
3178 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3179 return NVPTXISD::Suld1DArrayI64Zero;
3180 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3181 return NVPTXISD::Suld1DArrayV2I8Zero;
3182 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3183 return NVPTXISD::Suld1DArrayV2I16Zero;
3184 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3185 return NVPTXISD::Suld1DArrayV2I32Zero;
3186 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3187 return NVPTXISD::Suld1DArrayV2I64Zero;
3188 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3189 return NVPTXISD::Suld1DArrayV4I8Zero;
3190 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3191 return NVPTXISD::Suld1DArrayV4I16Zero;
3192 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3193 return NVPTXISD::Suld1DArrayV4I32Zero;
3194 case Intrinsic::nvvm_suld_2d_i8_zero:
3195 return NVPTXISD::Suld2DI8Zero;
3196 case Intrinsic::nvvm_suld_2d_i16_zero:
3197 return NVPTXISD::Suld2DI16Zero;
3198 case Intrinsic::nvvm_suld_2d_i32_zero:
3199 return NVPTXISD::Suld2DI32Zero;
3200 case Intrinsic::nvvm_suld_2d_i64_zero:
3201 return NVPTXISD::Suld2DI64Zero;
3202 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3203 return NVPTXISD::Suld2DV2I8Zero;
3204 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3205 return NVPTXISD::Suld2DV2I16Zero;
3206 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3207 return NVPTXISD::Suld2DV2I32Zero;
3208 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3209 return NVPTXISD::Suld2DV2I64Zero;
3210 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3211 return NVPTXISD::Suld2DV4I8Zero;
3212 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3213 return NVPTXISD::Suld2DV4I16Zero;
3214 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3215 return NVPTXISD::Suld2DV4I32Zero;
3216 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3217 return NVPTXISD::Suld2DArrayI8Zero;
3218 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3219 return NVPTXISD::Suld2DArrayI16Zero;
3220 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3221 return NVPTXISD::Suld2DArrayI32Zero;
3222 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3223 return NVPTXISD::Suld2DArrayI64Zero;
3224 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3225 return NVPTXISD::Suld2DArrayV2I8Zero;
3226 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3227 return NVPTXISD::Suld2DArrayV2I16Zero;
3228 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3229 return NVPTXISD::Suld2DArrayV2I32Zero;
3230 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3231 return NVPTXISD::Suld2DArrayV2I64Zero;
3232 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3233 return NVPTXISD::Suld2DArrayV4I8Zero;
3234 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3235 return NVPTXISD::Suld2DArrayV4I16Zero;
3236 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3237 return NVPTXISD::Suld2DArrayV4I32Zero;
3238 case Intrinsic::nvvm_suld_3d_i8_zero:
3239 return NVPTXISD::Suld3DI8Zero;
3240 case Intrinsic::nvvm_suld_3d_i16_zero:
3241 return NVPTXISD::Suld3DI16Zero;
3242 case Intrinsic::nvvm_suld_3d_i32_zero:
3243 return NVPTXISD::Suld3DI32Zero;
3244 case Intrinsic::nvvm_suld_3d_i64_zero:
3245 return NVPTXISD::Suld3DI64Zero;
3246 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3247 return NVPTXISD::Suld3DV2I8Zero;
3248 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3249 return NVPTXISD::Suld3DV2I16Zero;
3250 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3251 return NVPTXISD::Suld3DV2I32Zero;
3252 case Intrinsic::nvvm_suld_3d_v2i64_zero:
3253 return NVPTXISD::Suld3DV2I64Zero;
3254 case Intrinsic::nvvm_suld_3d_v4i8_zero:
3255 return NVPTXISD::Suld3DV4I8Zero;
3256 case Intrinsic::nvvm_suld_3d_v4i16_zero:
3257 return NVPTXISD::Suld3DV4I16Zero;
3258 case Intrinsic::nvvm_suld_3d_v4i32_zero:
3259 return NVPTXISD::Suld3DV4I32Zero;
3263 // llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
3265 // because we need the information that is only available in the "Value" type
3267 // pointer. In particular, the address space information.
3268 bool NVPTXTargetLowering::getTgtMemIntrinsic(
3269 IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
3270 switch (Intrinsic) {
3274 case Intrinsic::nvvm_atomic_load_add_f32:
3275 Info.opc = ISD::INTRINSIC_W_CHAIN;
3276 Info.memVT = MVT::f32;
3277 Info.ptrVal = I.getArgOperand(0);
3280 Info.readMem = true;
3281 Info.writeMem = true;
3285 case Intrinsic::nvvm_atomic_load_inc_32:
3286 case Intrinsic::nvvm_atomic_load_dec_32:
3287 Info.opc = ISD::INTRINSIC_W_CHAIN;
3288 Info.memVT = MVT::i32;
3289 Info.ptrVal = I.getArgOperand(0);
3292 Info.readMem = true;
3293 Info.writeMem = true;
3297 case Intrinsic::nvvm_ldu_global_i:
3298 case Intrinsic::nvvm_ldu_global_f:
3299 case Intrinsic::nvvm_ldu_global_p: {
3300 auto &DL = I.getModule()->getDataLayout();
3301 Info.opc = ISD::INTRINSIC_W_CHAIN;
3302 if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
3303 Info.memVT = getValueType(DL, I.getType());
3304 else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
3305 Info.memVT = getPointerTy(DL);
3307 Info.memVT = getValueType(DL, I.getType());
3308 Info.ptrVal = I.getArgOperand(0);
3311 Info.readMem = true;
3312 Info.writeMem = false;
3313 Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3317 case Intrinsic::nvvm_ldg_global_i:
3318 case Intrinsic::nvvm_ldg_global_f:
3319 case Intrinsic::nvvm_ldg_global_p: {
3320 auto &DL = I.getModule()->getDataLayout();
3322 Info.opc = ISD::INTRINSIC_W_CHAIN;
3323 if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
3324 Info.memVT = getValueType(DL, I.getType());
3325 else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
3326 Info.memVT = getPointerTy(DL);
3328 Info.memVT = getValueType(DL, I.getType());
3329 Info.ptrVal = I.getArgOperand(0);
3332 Info.readMem = true;
3333 Info.writeMem = false;
3334 Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3339 case Intrinsic::nvvm_tex_1d_v4f32_s32:
3340 case Intrinsic::nvvm_tex_1d_v4f32_f32:
3341 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
3342 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
3343 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
3344 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
3345 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
3346 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
3347 case Intrinsic::nvvm_tex_2d_v4f32_s32:
3348 case Intrinsic::nvvm_tex_2d_v4f32_f32:
3349 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
3350 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
3351 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
3352 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
3353 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
3354 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
3355 case Intrinsic::nvvm_tex_3d_v4f32_s32:
3356 case Intrinsic::nvvm_tex_3d_v4f32_f32:
3357 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
3358 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
3359 case Intrinsic::nvvm_tex_cube_v4f32_f32:
3360 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
3361 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
3362 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
3363 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
3364 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
3365 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
3366 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
3367 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
3368 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
3369 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
3370 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
3371 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
3372 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
3373 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
3374 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
3375 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
3376 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
3377 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
3378 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
3379 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3380 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3381 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3382 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3383 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3384 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3385 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3386 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3387 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3388 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3389 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3390 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3391 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3392 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3393 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3394 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32: {
3395 Info.opc = getOpcForTextureInstr(Intrinsic);
3396 Info.memVT = MVT::v4f32;
3397 Info.ptrVal = nullptr;
3400 Info.readMem = true;
3401 Info.writeMem = false;
3405 case Intrinsic::nvvm_tex_1d_v4s32_s32:
3406 case Intrinsic::nvvm_tex_1d_v4s32_f32:
3407 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
3408 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
3409 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
3410 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
3411 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
3412 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
3413 case Intrinsic::nvvm_tex_2d_v4s32_s32:
3414 case Intrinsic::nvvm_tex_2d_v4s32_f32:
3415 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
3416 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
3417 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
3418 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
3419 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
3420 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
3421 case Intrinsic::nvvm_tex_3d_v4s32_s32:
3422 case Intrinsic::nvvm_tex_3d_v4s32_f32:
3423 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
3424 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
3425 case Intrinsic::nvvm_tex_cube_v4s32_f32:
3426 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
3427 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
3428 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
3429 case Intrinsic::nvvm_tex_cube_v4u32_f32:
3430 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
3431 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
3432 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
3433 case Intrinsic::nvvm_tex_1d_v4u32_s32:
3434 case Intrinsic::nvvm_tex_1d_v4u32_f32:
3435 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
3436 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
3437 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
3438 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
3439 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
3440 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
3441 case Intrinsic::nvvm_tex_2d_v4u32_s32:
3442 case Intrinsic::nvvm_tex_2d_v4u32_f32:
3443 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
3444 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
3445 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
3446 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
3447 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
3448 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
3449 case Intrinsic::nvvm_tex_3d_v4u32_s32:
3450 case Intrinsic::nvvm_tex_3d_v4u32_f32:
3451 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
3452 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
3453 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
3454 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
3455 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
3456 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
3457 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
3458 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
3459 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
3460 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
3461 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
3462 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
3463 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
3464 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
3465 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
3466 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
3467 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
3468 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
3469 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
3470 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
3471 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
3472 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3473 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3474 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3475 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3476 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3477 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3478 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3479 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3480 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3481 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
3482 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
3483 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
3484 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
3485 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
3486 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
3487 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
3488 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
3489 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3490 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3491 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3492 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3493 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3494 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3495 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3496 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3497 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3498 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3499 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3500 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3501 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3502 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3503 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3504 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3505 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3506 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3507 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3508 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3509 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3510 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3511 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3512 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
3513 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3514 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3515 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3516 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32: {
3517 Info.opc = getOpcForTextureInstr(Intrinsic);
3518 Info.memVT = MVT::v4i32;
3519 Info.ptrVal = nullptr;
3522 Info.readMem = true;
3523 Info.writeMem = false;
3527 case Intrinsic::nvvm_suld_1d_i8_clamp:
3528 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3529 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3530 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3531 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3532 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3533 case Intrinsic::nvvm_suld_2d_i8_clamp:
3534 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3535 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3536 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3537 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3538 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3539 case Intrinsic::nvvm_suld_3d_i8_clamp:
3540 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3541 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3542 case Intrinsic::nvvm_suld_1d_i8_trap:
3543 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3544 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3545 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3546 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3547 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3548 case Intrinsic::nvvm_suld_2d_i8_trap:
3549 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3550 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3551 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3552 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3553 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3554 case Intrinsic::nvvm_suld_3d_i8_trap:
3555 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3556 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3557 case Intrinsic::nvvm_suld_1d_i8_zero:
3558 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3559 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3560 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3561 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3562 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3563 case Intrinsic::nvvm_suld_2d_i8_zero:
3564 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3565 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3566 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3567 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3568 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3569 case Intrinsic::nvvm_suld_3d_i8_zero:
3570 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3571 case Intrinsic::nvvm_suld_3d_v4i8_zero: {
3572 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3573 Info.memVT = MVT::i8;
3574 Info.ptrVal = nullptr;
3577 Info.readMem = true;
3578 Info.writeMem = false;
3582 case Intrinsic::nvvm_suld_1d_i16_clamp:
3583 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3584 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3585 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3586 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3587 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3588 case Intrinsic::nvvm_suld_2d_i16_clamp:
3589 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3590 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3591 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3592 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3593 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3594 case Intrinsic::nvvm_suld_3d_i16_clamp:
3595 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3596 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3597 case Intrinsic::nvvm_suld_1d_i16_trap:
3598 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3599 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3600 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3601 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3602 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3603 case Intrinsic::nvvm_suld_2d_i16_trap:
3604 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3605 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3606 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3607 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3608 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3609 case Intrinsic::nvvm_suld_3d_i16_trap:
3610 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3611 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3612 case Intrinsic::nvvm_suld_1d_i16_zero:
3613 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3614 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3615 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3616 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3617 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3618 case Intrinsic::nvvm_suld_2d_i16_zero:
3619 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3620 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3621 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3622 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3623 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3624 case Intrinsic::nvvm_suld_3d_i16_zero:
3625 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3626 case Intrinsic::nvvm_suld_3d_v4i16_zero: {
3627 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3628 Info.memVT = MVT::i16;
3629 Info.ptrVal = nullptr;
3632 Info.readMem = true;
3633 Info.writeMem = false;
3637 case Intrinsic::nvvm_suld_1d_i32_clamp:
3638 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3639 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3640 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3641 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3642 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3643 case Intrinsic::nvvm_suld_2d_i32_clamp:
3644 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3645 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3646 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3647 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3648 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3649 case Intrinsic::nvvm_suld_3d_i32_clamp:
3650 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3651 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3652 case Intrinsic::nvvm_suld_1d_i32_trap:
3653 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3654 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3655 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3656 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3657 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3658 case Intrinsic::nvvm_suld_2d_i32_trap:
3659 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3660 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3661 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3662 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3663 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3664 case Intrinsic::nvvm_suld_3d_i32_trap:
3665 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3666 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3667 case Intrinsic::nvvm_suld_1d_i32_zero:
3668 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3669 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3670 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3671 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3672 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3673 case Intrinsic::nvvm_suld_2d_i32_zero:
3674 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3675 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3676 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3677 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3678 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3679 case Intrinsic::nvvm_suld_3d_i32_zero:
3680 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3681 case Intrinsic::nvvm_suld_3d_v4i32_zero: {
3682 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3683 Info.memVT = MVT::i32;
3684 Info.ptrVal = nullptr;
3687 Info.readMem = true;
3688 Info.writeMem = false;
3692 case Intrinsic::nvvm_suld_1d_i64_clamp:
3693 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3694 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3695 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3696 case Intrinsic::nvvm_suld_2d_i64_clamp:
3697 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3698 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3699 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3700 case Intrinsic::nvvm_suld_3d_i64_clamp:
3701 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3702 case Intrinsic::nvvm_suld_1d_i64_trap:
3703 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3704 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3705 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3706 case Intrinsic::nvvm_suld_2d_i64_trap:
3707 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3708 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3709 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3710 case Intrinsic::nvvm_suld_3d_i64_trap:
3711 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3712 case Intrinsic::nvvm_suld_1d_i64_zero:
3713 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3714 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3715 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3716 case Intrinsic::nvvm_suld_2d_i64_zero:
3717 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3718 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3719 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3720 case Intrinsic::nvvm_suld_3d_i64_zero:
3721 case Intrinsic::nvvm_suld_3d_v2i64_zero: {
3722 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3723 Info.memVT = MVT::i64;
3724 Info.ptrVal = nullptr;
3727 Info.readMem = true;
3728 Info.writeMem = false;
3736 /// isLegalAddressingMode - Return true if the addressing mode represented
3737 /// by AM is legal for this target, for a load/store of the specified type.
3738 /// Used to guide target specific optimizations, like loop strength reduction
3739 /// (LoopStrengthReduce.cpp) and memory optimization for address mode
3740 /// (CodeGenPrepare.cpp)
3741 bool NVPTXTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3742 const AddrMode &AM, Type *Ty,
3743 unsigned AS) const {
3745 // AddrMode - This represents an addressing mode of:
3746 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
3748 // The legal address modes are
3755 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale;
3759 case 0: // "r", "r+i" or "i" is allowed
3762 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
3764 // Otherwise we have r+i.
3767 // No scale > 1 is allowed
3773 //===----------------------------------------------------------------------===//
3774 // NVPTX Inline Assembly Support
3775 //===----------------------------------------------------------------------===//
3777 /// getConstraintType - Given a constraint letter, return the type of
3778 /// constraint it is for this target.
3779 NVPTXTargetLowering::ConstraintType
3780 NVPTXTargetLowering::getConstraintType(StringRef Constraint) const {
3781 if (Constraint.size() == 1) {
3782 switch (Constraint[0]) {
3794 return C_RegisterClass;
3797 return TargetLowering::getConstraintType(Constraint);
3800 std::pair<unsigned, const TargetRegisterClass *>
3801 NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3802 StringRef Constraint,
3804 if (Constraint.size() == 1) {
3805 switch (Constraint[0]) {
3807 return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
3809 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3811 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3813 return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
3816 return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
3818 return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
3820 return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
3823 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3826 /// getFunctionAlignment - Return the Log2 alignment of this function.
3827 unsigned NVPTXTargetLowering::getFunctionAlignment(const Function *) const {
3831 //===----------------------------------------------------------------------===//
3832 // NVPTX DAG Combining
3833 //===----------------------------------------------------------------------===//
3835 bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
3836 CodeGenOpt::Level OptLevel) const {
3837 const Function *F = MF.getFunction();
3838 const TargetOptions &TO = MF.getTarget().Options;
3840 // Always honor command-line argument
3841 if (FMAContractLevelOpt.getNumOccurrences() > 0) {
3842 return FMAContractLevelOpt > 0;
3843 } else if (OptLevel == 0) {
3844 // Do not contract if we're not optimizing the code
3846 } else if (TO.AllowFPOpFusion == FPOpFusion::Fast || TO.UnsafeFPMath) {
3847 // Honor TargetOptions flags that explicitly say fusion is okay
3849 } else if (F->hasFnAttribute("unsafe-fp-math")) {
3850 // Check for unsafe-fp-math=true coming from Clang
3851 Attribute Attr = F->getFnAttribute("unsafe-fp-math");
3852 StringRef Val = Attr.getValueAsString();
3857 // We did not have a clear indication that fusion is allowed, so assume not
3861 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
3862 /// operands N0 and N1. This is a helper for PerformADDCombine that is
3863 /// called with the default operands, and if that fails, with commuted
3865 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
3866 TargetLowering::DAGCombinerInfo &DCI,
3867 const NVPTXSubtarget &Subtarget,
3868 CodeGenOpt::Level OptLevel) {
3869 SelectionDAG &DAG = DCI.DAG;
3870 // Skip non-integer, non-scalar case
3871 EVT VT=N0.getValueType();
3875 // fold (add (mul a, b), c) -> (mad a, b, c)
3877 if (N0.getOpcode() == ISD::MUL) {
3878 assert (VT.isInteger());
3880 // Since integer multiply-add costs the same as integer multiply
3881 // but is more costly than integer add, do the fusion only when
3882 // the mul is only used in the add.
3883 if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
3884 !N0.getNode()->hasOneUse())
3888 return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
3889 N0.getOperand(0), N0.getOperand(1), N1);
3891 else if (N0.getOpcode() == ISD::FMUL) {
3892 if (VT == MVT::f32 || VT == MVT::f64) {
3893 const auto *TLI = static_cast<const NVPTXTargetLowering *>(
3894 &DAG.getTargetLoweringInfo());
3895 if (!TLI->allowFMA(DAG.getMachineFunction(), OptLevel))
3898 // For floating point:
3899 // Do the fusion only when the mul has less than 5 uses and all
3901 // The heuristic is that if a use is not an add, then that use
3902 // cannot be fused into fma, therefore mul is still needed anyway.
3903 // If there are more than 4 uses, even if they are all add, fusing
3904 // them will increase register pressue.
3907 int nonAddCount = 0;
3908 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3909 UE = N0.getNode()->use_end();
3913 if (User->getOpcode() != ISD::FADD)
3919 int orderNo = N->getIROrder();
3920 int orderNo2 = N0.getNode()->getIROrder();
3921 // simple heuristics here for considering potential register
3922 // pressure, the logics here is that the differnce are used
3923 // to measure the distance between def and use, the longer distance
3924 // more likely cause register pressure.
3925 if (orderNo - orderNo2 < 500)
3928 // Now, check if at least one of the FMUL's operands is live beyond the node N,
3929 // which guarantees that the FMA will not increase register pressure at node N.
3930 bool opIsLive = false;
3931 const SDNode *left = N0.getOperand(0).getNode();
3932 const SDNode *right = N0.getOperand(1).getNode();
3934 if (isa<ConstantSDNode>(left) || isa<ConstantSDNode>(right))
3938 for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
3940 int orderNo3 = User->getIROrder();
3941 if (orderNo3 > orderNo) {
3948 for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
3950 int orderNo3 = User->getIROrder();
3951 if (orderNo3 > orderNo) {
3961 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
3962 N0.getOperand(0), N0.getOperand(1), N1);
3969 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3971 static SDValue PerformADDCombine(SDNode *N,
3972 TargetLowering::DAGCombinerInfo &DCI,
3973 const NVPTXSubtarget &Subtarget,
3974 CodeGenOpt::Level OptLevel) {
3975 SDValue N0 = N->getOperand(0);
3976 SDValue N1 = N->getOperand(1);
3978 // First try with the default operand order.
3979 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget,
3981 if (Result.getNode())
3984 // If that didn't work, try again with the operands commuted.
3985 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
3988 static SDValue PerformANDCombine(SDNode *N,
3989 TargetLowering::DAGCombinerInfo &DCI) {
3990 // The type legalizer turns a vector load of i8 values into a zextload to i16
3991 // registers, optionally ANY_EXTENDs it (if target type is integer),
3992 // and ANDs off the high 8 bits. Since we turn this load into a
3993 // target-specific DAG node, the DAG combiner fails to eliminate these AND
3994 // nodes. Do that here.
3995 SDValue Val = N->getOperand(0);
3996 SDValue Mask = N->getOperand(1);
3998 if (isa<ConstantSDNode>(Val)) {
3999 std::swap(Val, Mask);
4003 // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
4004 if (Val.getOpcode() == ISD::ANY_EXTEND) {
4006 Val = Val->getOperand(0);
4009 if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
4010 Val = Val->getOperand(0);
4013 if (Val->getOpcode() == NVPTXISD::LoadV2 ||
4014 Val->getOpcode() == NVPTXISD::LoadV4) {
4015 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
4017 // Not an AND with a constant
4021 uint64_t MaskVal = MaskCnst->getZExtValue();
4022 if (MaskVal != 0xff) {
4023 // Not an AND that chops off top 8 bits
4027 MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
4029 // Not a MemSDNode?!?
4033 EVT MemVT = Mem->getMemoryVT();
4034 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
4035 // We only handle the i8 case
4040 cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
4042 if (ExtType == ISD::SEXTLOAD) {
4043 // If for some reason the load is a sextload, the and is needed to zero
4044 // out the high 8 bits
4049 if (AExt.getNode() != 0) {
4050 // Re-insert the ext as a zext.
4051 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
4052 AExt.getValueType(), Val);
4056 // If we get here, the AND is unnecessary. Just replace it with the load
4057 DCI.CombineTo(N, Val, AddTo);
4063 static SDValue PerformSELECTCombine(SDNode *N,
4064 TargetLowering::DAGCombinerInfo &DCI) {
4065 // Currently this detects patterns for integer min and max and
4066 // lowers them to PTX-specific intrinsics that enable hardware
4069 const SDValue Cond = N->getOperand(0);
4070 if (Cond.getOpcode() != ISD::SETCC) return SDValue();
4072 const SDValue LHS = Cond.getOperand(0);
4073 const SDValue RHS = Cond.getOperand(1);
4074 const SDValue True = N->getOperand(1);
4075 const SDValue False = N->getOperand(2);
4076 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
4079 const EVT VT = N->getValueType(0);
4080 if (VT != MVT::i32 && VT != MVT::i64) return SDValue();
4082 const ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
4083 SDValue Larger; // The larger of LHS and RHS when condition is true.
4102 const bool IsMax = (Larger == True);
4103 const bool IsSigned = ISD::isSignedIntSetCC(CC);
4105 unsigned IntrinsicId;
4106 if (VT == MVT::i32) {
4108 IntrinsicId = IsMax ? Intrinsic::nvvm_max_i : Intrinsic::nvvm_min_i;
4110 IntrinsicId = IsMax ? Intrinsic::nvvm_max_ui : Intrinsic::nvvm_min_ui;
4112 assert(VT == MVT::i64);
4114 IntrinsicId = IsMax ? Intrinsic::nvvm_max_ll : Intrinsic::nvvm_min_ll;
4116 IntrinsicId = IsMax ? Intrinsic::nvvm_max_ull : Intrinsic::nvvm_min_ull;
4120 return DCI.DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
4121 DCI.DAG.getConstant(IntrinsicId, DL, VT), LHS, RHS);
4124 enum OperandSignedness {
4130 /// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
4131 /// that can be demoted to \p OptSize bits without loss of information. The
4132 /// signedness of the operand, if determinable, is placed in \p S.
4133 static bool IsMulWideOperandDemotable(SDValue Op,
4135 OperandSignedness &S) {
4138 if (Op.getOpcode() == ISD::SIGN_EXTEND ||
4139 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
4140 EVT OrigVT = Op.getOperand(0).getValueType();
4141 if (OrigVT.getSizeInBits() <= OptSize) {
4145 } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
4146 EVT OrigVT = Op.getOperand(0).getValueType();
4147 if (OrigVT.getSizeInBits() <= OptSize) {
4156 /// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
4157 /// be demoted to \p OptSize bits without loss of information. If the operands
4158 /// contain a constant, it should appear as the RHS operand. The signedness of
4159 /// the operands is placed in \p IsSigned.
4160 static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
4164 OperandSignedness LHSSign;
4166 // The LHS operand must be a demotable op
4167 if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
4170 // We should have been able to determine the signedness from the LHS
4171 if (LHSSign == Unknown)
4174 IsSigned = (LHSSign == Signed);
4176 // The RHS can be a demotable op or a constant
4177 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
4178 APInt Val = CI->getAPIntValue();
4179 if (LHSSign == Unsigned) {
4180 return Val.isIntN(OptSize);
4182 return Val.isSignedIntN(OptSize);
4185 OperandSignedness RHSSign;
4186 if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
4189 return LHSSign == RHSSign;
4193 /// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
4194 /// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
4195 /// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
4197 static SDValue TryMULWIDECombine(SDNode *N,
4198 TargetLowering::DAGCombinerInfo &DCI) {
4199 EVT MulType = N->getValueType(0);
4200 if (MulType != MVT::i32 && MulType != MVT::i64) {
4205 unsigned OptSize = MulType.getSizeInBits() >> 1;
4206 SDValue LHS = N->getOperand(0);
4207 SDValue RHS = N->getOperand(1);
4209 // Canonicalize the multiply so the constant (if any) is on the right
4210 if (N->getOpcode() == ISD::MUL) {
4211 if (isa<ConstantSDNode>(LHS)) {
4212 std::swap(LHS, RHS);
4216 // If we have a SHL, determine the actual multiply amount
4217 if (N->getOpcode() == ISD::SHL) {
4218 ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
4223 APInt ShiftAmt = ShlRHS->getAPIntValue();
4224 unsigned BitWidth = MulType.getSizeInBits();
4225 if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
4226 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
4227 RHS = DCI.DAG.getConstant(MulVal, DL, MulType);
4234 // Verify that our operands are demotable
4235 if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
4240 if (MulType == MVT::i32) {
4241 DemotedVT = MVT::i16;
4243 DemotedVT = MVT::i32;
4246 // Truncate the operands to the correct size. Note that these are just for
4247 // type consistency and will (likely) be eliminated in later phases.
4249 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS);
4251 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS);
4255 Opc = NVPTXISD::MUL_WIDE_SIGNED;
4257 Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
4260 return DCI.DAG.getNode(Opc, DL, MulType, TruncLHS, TruncRHS);
4263 /// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
4264 static SDValue PerformMULCombine(SDNode *N,
4265 TargetLowering::DAGCombinerInfo &DCI,
4266 CodeGenOpt::Level OptLevel) {
4268 // Try mul.wide combining at OptLevel > 0
4269 SDValue Ret = TryMULWIDECombine(N, DCI);
4277 /// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
4278 static SDValue PerformSHLCombine(SDNode *N,
4279 TargetLowering::DAGCombinerInfo &DCI,
4280 CodeGenOpt::Level OptLevel) {
4282 // Try mul.wide combining at OptLevel > 0
4283 SDValue Ret = TryMULWIDECombine(N, DCI);
4291 SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
4292 DAGCombinerInfo &DCI) const {
4293 CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
4294 switch (N->getOpcode()) {
4298 return PerformADDCombine(N, DCI, STI, OptLevel);
4300 return PerformMULCombine(N, DCI, OptLevel);
4302 return PerformSHLCombine(N, DCI, OptLevel);
4304 return PerformANDCombine(N, DCI);
4306 return PerformSELECTCombine(N, DCI);
4311 /// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
4312 static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
4313 SmallVectorImpl<SDValue> &Results) {
4314 EVT ResVT = N->getValueType(0);
4317 assert(ResVT.isVector() && "Vector load must have vector type");
4319 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
4320 // legal. We can (and should) split that into 2 loads of <2 x double> here
4321 // but I'm leaving that as a TODO for now.
4322 assert(ResVT.isSimple() && "Can only handle simple types");
4323 switch (ResVT.getSimpleVT().SimpleTy) {
4336 // This is a "native" vector type
4340 LoadSDNode *LD = cast<LoadSDNode>(N);
4342 unsigned Align = LD->getAlignment();
4343 auto &TD = DAG.getDataLayout();
4344 unsigned PrefAlign =
4345 TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext()));
4346 if (Align < PrefAlign) {
4347 // This load is not sufficiently aligned, so bail out and let this vector
4348 // load be scalarized. Note that we may still be able to emit smaller
4349 // vector loads. For example, if we are loading a <4 x float> with an
4350 // alignment of 8, this check will fail but the legalizer will try again
4351 // with 2 x <2 x float>, which will succeed with an alignment of 8.
4355 EVT EltVT = ResVT.getVectorElementType();
4356 unsigned NumElts = ResVT.getVectorNumElements();
4358 // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
4359 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4360 // loaded type to i16 and propagate the "real" type as the memory type.
4361 bool NeedTrunc = false;
4362 if (EltVT.getSizeInBits() < 16) {
4367 unsigned Opcode = 0;
4374 Opcode = NVPTXISD::LoadV2;
4375 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4378 Opcode = NVPTXISD::LoadV4;
4379 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4380 LdResVTs = DAG.getVTList(ListVTs);
4385 // Copy regular operands
4386 SmallVector<SDValue, 8> OtherOps(N->op_begin(), N->op_end());
4388 // The select routine does not have access to the LoadSDNode instance, so
4389 // pass along the extension information
4390 OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType(), DL));
4392 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4394 LD->getMemOperand());
4396 SmallVector<SDValue, 4> ScalarRes;
4398 for (unsigned i = 0; i < NumElts; ++i) {
4399 SDValue Res = NewLD.getValue(i);
4401 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4402 ScalarRes.push_back(Res);
4405 SDValue LoadChain = NewLD.getValue(NumElts);
4407 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
4409 Results.push_back(BuildVec);
4410 Results.push_back(LoadChain);
4413 static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
4414 SmallVectorImpl<SDValue> &Results) {
4415 SDValue Chain = N->getOperand(0);
4416 SDValue Intrin = N->getOperand(1);
4419 // Get the intrinsic ID
4420 unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
4424 case Intrinsic::nvvm_ldg_global_i:
4425 case Intrinsic::nvvm_ldg_global_f:
4426 case Intrinsic::nvvm_ldg_global_p:
4427 case Intrinsic::nvvm_ldu_global_i:
4428 case Intrinsic::nvvm_ldu_global_f:
4429 case Intrinsic::nvvm_ldu_global_p: {
4430 EVT ResVT = N->getValueType(0);
4432 if (ResVT.isVector()) {
4435 unsigned NumElts = ResVT.getVectorNumElements();
4436 EVT EltVT = ResVT.getVectorElementType();
4438 // Since LDU/LDG are target nodes, we cannot rely on DAG type
4440 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4441 // loaded type to i16 and propagate the "real" type as the memory type.
4442 bool NeedTrunc = false;
4443 if (EltVT.getSizeInBits() < 16) {
4448 unsigned Opcode = 0;
4458 case Intrinsic::nvvm_ldg_global_i:
4459 case Intrinsic::nvvm_ldg_global_f:
4460 case Intrinsic::nvvm_ldg_global_p:
4461 Opcode = NVPTXISD::LDGV2;
4463 case Intrinsic::nvvm_ldu_global_i:
4464 case Intrinsic::nvvm_ldu_global_f:
4465 case Intrinsic::nvvm_ldu_global_p:
4466 Opcode = NVPTXISD::LDUV2;
4469 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4475 case Intrinsic::nvvm_ldg_global_i:
4476 case Intrinsic::nvvm_ldg_global_f:
4477 case Intrinsic::nvvm_ldg_global_p:
4478 Opcode = NVPTXISD::LDGV4;
4480 case Intrinsic::nvvm_ldu_global_i:
4481 case Intrinsic::nvvm_ldu_global_f:
4482 case Intrinsic::nvvm_ldu_global_p:
4483 Opcode = NVPTXISD::LDUV4;
4486 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4487 LdResVTs = DAG.getVTList(ListVTs);
4492 SmallVector<SDValue, 8> OtherOps;
4494 // Copy regular operands
4496 OtherOps.push_back(Chain); // Chain
4497 // Skip operand 1 (intrinsic ID)
4499 OtherOps.append(N->op_begin() + 2, N->op_end());
4501 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4503 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4504 MemSD->getMemoryVT(),
4505 MemSD->getMemOperand());
4507 SmallVector<SDValue, 4> ScalarRes;
4509 for (unsigned i = 0; i < NumElts; ++i) {
4510 SDValue Res = NewLD.getValue(i);
4513 DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4514 ScalarRes.push_back(Res);
4517 SDValue LoadChain = NewLD.getValue(NumElts);
4520 DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
4522 Results.push_back(BuildVec);
4523 Results.push_back(LoadChain);
4526 assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
4527 "Custom handling of non-i8 ldu/ldg?");
4529 // Just copy all operands as-is
4530 SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
4532 // Force output to i16
4533 SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
4535 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4537 // We make sure the memory type is i8, which will be used during isel
4538 // to select the proper instruction.
4540 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
4541 MVT::i8, MemSD->getMemOperand());
4543 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
4544 NewLD.getValue(0)));
4545 Results.push_back(NewLD.getValue(1));
4551 void NVPTXTargetLowering::ReplaceNodeResults(
4552 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
4553 switch (N->getOpcode()) {
4555 report_fatal_error("Unhandled custom legalization");
4557 ReplaceLoadVector(N, DAG, Results);
4559 case ISD::INTRINSIC_W_CHAIN:
4560 ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
4565 // Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
4566 void NVPTXSection::anchor() {}
4568 NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
4572 delete ReadOnlySection;
4574 delete StaticCtorSection;
4575 delete StaticDtorSection;
4577 delete EHFrameSection;
4578 delete DwarfAbbrevSection;
4579 delete DwarfInfoSection;
4580 delete DwarfLineSection;
4581 delete DwarfFrameSection;
4582 delete DwarfPubTypesSection;
4583 delete DwarfDebugInlineSection;
4584 delete DwarfStrSection;
4585 delete DwarfLocSection;
4586 delete DwarfARangesSection;
4587 delete DwarfRangesSection;
4591 NVPTXTargetObjectFile::SelectSectionForGlobal(const GlobalValue *GV,
4592 SectionKind Kind, Mangler &Mang,
4593 const TargetMachine &TM) const {
4594 return getDataSection();