2 // The LLVM Compiler Infrastructure
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXISelLowering.h"
16 #include "NVPTXTargetMachine.h"
17 #include "NVPTXTargetObjectFile.h"
18 #include "NVPTXUtilities.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
25 #include "llvm/IR/CallSite.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/IntrinsicInst.h"
30 #include "llvm/IR/Intrinsics.h"
31 #include "llvm/IR/Module.h"
32 #include "llvm/MC/MCSectionELF.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
41 #define DEBUG_TYPE "nvptx-lower"
45 static unsigned int uniqueCallSite = 0;
47 static cl::opt<bool> sched4reg(
49 cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
51 static cl::opt<unsigned>
52 FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
53 cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
54 " 1: do it 2: do it aggressively"),
57 static bool IsPTXVectorType(MVT VT) {
58 switch (VT.SimpleTy) {
77 /// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
78 /// EVTs that compose it. Unlike ComputeValueVTs, this will break apart vectors
79 /// into their primitive components.
80 /// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
81 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
82 /// LowerCall, and LowerReturn.
83 static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL,
84 Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
85 SmallVectorImpl<uint64_t> *Offsets = nullptr,
86 uint64_t StartingOffset = 0) {
87 SmallVector<EVT, 16> TempVTs;
88 SmallVector<uint64_t, 16> TempOffsets;
90 ComputeValueVTs(TLI, DL, Ty, TempVTs, &TempOffsets, StartingOffset);
91 for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
93 uint64_t Off = TempOffsets[i];
95 for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
96 ValueVTs.push_back(VT.getVectorElementType());
98 Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
101 ValueVTs.push_back(VT);
103 Offsets->push_back(Off);
108 // NVPTXTargetLowering Constructor.
109 NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
110 const NVPTXSubtarget &STI)
111 : TargetLowering(TM), nvTM(&TM), STI(STI) {
113 // always lower memset, memcpy, and memmove intrinsics to load/store
114 // instructions, rather
115 // then generating calls to memset, mempcy or memmove.
116 MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
117 MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
118 MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
120 setBooleanContents(ZeroOrNegativeOneBooleanContent);
121 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
123 // Jump is Expensive. Don't create extra control flow for 'and', 'or'
124 // condition branches.
125 setJumpIsExpensive(true);
127 // By default, use the Source scheduling
129 setSchedulingPreference(Sched::RegPressure);
131 setSchedulingPreference(Sched::Source);
133 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
134 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
135 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
136 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
137 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
138 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
140 // Operations not directly supported by NVPTX.
141 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
143 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
144 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
145 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
146 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
147 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
148 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
149 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
150 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
151 setOperationAction(ISD::BR_CC, MVT::i8, Expand);
152 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
153 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
154 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
155 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
156 // For others we will expand to a SHL/SRA pair.
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
163 setOperationAction(ISD::SHL_PARTS, MVT::i32 , Custom);
164 setOperationAction(ISD::SRA_PARTS, MVT::i32 , Custom);
165 setOperationAction(ISD::SRL_PARTS, MVT::i32 , Custom);
166 setOperationAction(ISD::SHL_PARTS, MVT::i64 , Custom);
167 setOperationAction(ISD::SRA_PARTS, MVT::i64 , Custom);
168 setOperationAction(ISD::SRL_PARTS, MVT::i64 , Custom);
170 if (STI.hasROT64()) {
171 setOperationAction(ISD::ROTL, MVT::i64, Legal);
172 setOperationAction(ISD::ROTR, MVT::i64, Legal);
174 setOperationAction(ISD::ROTL, MVT::i64, Expand);
175 setOperationAction(ISD::ROTR, MVT::i64, Expand);
177 if (STI.hasROT32()) {
178 setOperationAction(ISD::ROTL, MVT::i32, Legal);
179 setOperationAction(ISD::ROTR, MVT::i32, Legal);
181 setOperationAction(ISD::ROTL, MVT::i32, Expand);
182 setOperationAction(ISD::ROTR, MVT::i32, Expand);
185 setOperationAction(ISD::ROTL, MVT::i16, Expand);
186 setOperationAction(ISD::ROTR, MVT::i16, Expand);
187 setOperationAction(ISD::ROTL, MVT::i8, Expand);
188 setOperationAction(ISD::ROTR, MVT::i8, Expand);
189 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
190 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
191 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
193 // Indirect branch is not supported.
194 // This also disables Jump Table creation.
195 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
196 setOperationAction(ISD::BRIND, MVT::Other, Expand);
198 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
199 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
201 // We want to legalize constant related memmove and memcopy
203 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
205 // Turn FP extload into load/fextend
206 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
207 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
208 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
209 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
210 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
211 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
212 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
213 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
214 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
215 // Turn FP truncstore into trunc + store.
216 // FIXME: vector types should also be expanded
217 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
218 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
219 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
221 // PTX does not support load / store predicate registers
222 setOperationAction(ISD::LOAD, MVT::i1, Custom);
223 setOperationAction(ISD::STORE, MVT::i1, Custom);
225 for (MVT VT : MVT::integer_valuetypes()) {
226 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
227 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
228 setTruncStoreAction(VT, MVT::i1, Expand);
231 // This is legal in NVPTX
232 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
233 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
235 // TRAP can be lowered to PTX trap
236 setOperationAction(ISD::TRAP, MVT::Other, Legal);
238 setOperationAction(ISD::ADDC, MVT::i64, Expand);
239 setOperationAction(ISD::ADDE, MVT::i64, Expand);
241 // Register custom handling for vector loads/stores
242 for (MVT VT : MVT::vector_valuetypes()) {
243 if (IsPTXVectorType(VT)) {
244 setOperationAction(ISD::LOAD, VT, Custom);
245 setOperationAction(ISD::STORE, VT, Custom);
246 setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
250 // Custom handling for i8 intrinsics
251 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
253 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
254 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
255 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
256 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal);
257 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
258 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
259 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
260 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
261 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
262 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
263 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
264 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
265 setOperationAction(ISD::CTPOP, MVT::i16, Legal);
266 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
267 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
269 // PTX does not directly support SELP of i1, so promote to i32 first
270 setOperationAction(ISD::SELECT, MVT::i1, Custom);
272 // We have some custom DAG combine patterns for these nodes
273 setTargetDAGCombine(ISD::ADD);
274 setTargetDAGCombine(ISD::AND);
275 setTargetDAGCombine(ISD::FADD);
276 setTargetDAGCombine(ISD::MUL);
277 setTargetDAGCombine(ISD::SHL);
279 // Now deduce the information based on the above mentioned
281 computeRegisterProperties(STI.getRegisterInfo());
284 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
285 switch ((NVPTXISD::NodeType)Opcode) {
286 case NVPTXISD::FIRST_NUMBER:
289 return "NVPTXISD::CALL";
290 case NVPTXISD::RET_FLAG:
291 return "NVPTXISD::RET_FLAG";
292 case NVPTXISD::LOAD_PARAM:
293 return "NVPTXISD::LOAD_PARAM";
294 case NVPTXISD::Wrapper:
295 return "NVPTXISD::Wrapper";
296 case NVPTXISD::DeclareParam:
297 return "NVPTXISD::DeclareParam";
298 case NVPTXISD::DeclareScalarParam:
299 return "NVPTXISD::DeclareScalarParam";
300 case NVPTXISD::DeclareRet:
301 return "NVPTXISD::DeclareRet";
302 case NVPTXISD::DeclareScalarRet:
303 return "NVPTXISD::DeclareScalarRet";
304 case NVPTXISD::DeclareRetParam:
305 return "NVPTXISD::DeclareRetParam";
306 case NVPTXISD::PrintCall:
307 return "NVPTXISD::PrintCall";
308 case NVPTXISD::PrintCallUni:
309 return "NVPTXISD::PrintCallUni";
310 case NVPTXISD::LoadParam:
311 return "NVPTXISD::LoadParam";
312 case NVPTXISD::LoadParamV2:
313 return "NVPTXISD::LoadParamV2";
314 case NVPTXISD::LoadParamV4:
315 return "NVPTXISD::LoadParamV4";
316 case NVPTXISD::StoreParam:
317 return "NVPTXISD::StoreParam";
318 case NVPTXISD::StoreParamV2:
319 return "NVPTXISD::StoreParamV2";
320 case NVPTXISD::StoreParamV4:
321 return "NVPTXISD::StoreParamV4";
322 case NVPTXISD::StoreParamS32:
323 return "NVPTXISD::StoreParamS32";
324 case NVPTXISD::StoreParamU32:
325 return "NVPTXISD::StoreParamU32";
326 case NVPTXISD::CallArgBegin:
327 return "NVPTXISD::CallArgBegin";
328 case NVPTXISD::CallArg:
329 return "NVPTXISD::CallArg";
330 case NVPTXISD::LastCallArg:
331 return "NVPTXISD::LastCallArg";
332 case NVPTXISD::CallArgEnd:
333 return "NVPTXISD::CallArgEnd";
334 case NVPTXISD::CallVoid:
335 return "NVPTXISD::CallVoid";
336 case NVPTXISD::CallVal:
337 return "NVPTXISD::CallVal";
338 case NVPTXISD::CallSymbol:
339 return "NVPTXISD::CallSymbol";
340 case NVPTXISD::Prototype:
341 return "NVPTXISD::Prototype";
342 case NVPTXISD::MoveParam:
343 return "NVPTXISD::MoveParam";
344 case NVPTXISD::StoreRetval:
345 return "NVPTXISD::StoreRetval";
346 case NVPTXISD::StoreRetvalV2:
347 return "NVPTXISD::StoreRetvalV2";
348 case NVPTXISD::StoreRetvalV4:
349 return "NVPTXISD::StoreRetvalV4";
350 case NVPTXISD::PseudoUseParam:
351 return "NVPTXISD::PseudoUseParam";
352 case NVPTXISD::RETURN:
353 return "NVPTXISD::RETURN";
354 case NVPTXISD::CallSeqBegin:
355 return "NVPTXISD::CallSeqBegin";
356 case NVPTXISD::CallSeqEnd:
357 return "NVPTXISD::CallSeqEnd";
358 case NVPTXISD::CallPrototype:
359 return "NVPTXISD::CallPrototype";
360 case NVPTXISD::LoadV2:
361 return "NVPTXISD::LoadV2";
362 case NVPTXISD::LoadV4:
363 return "NVPTXISD::LoadV4";
364 case NVPTXISD::LDGV2:
365 return "NVPTXISD::LDGV2";
366 case NVPTXISD::LDGV4:
367 return "NVPTXISD::LDGV4";
368 case NVPTXISD::LDUV2:
369 return "NVPTXISD::LDUV2";
370 case NVPTXISD::LDUV4:
371 return "NVPTXISD::LDUV4";
372 case NVPTXISD::StoreV2:
373 return "NVPTXISD::StoreV2";
374 case NVPTXISD::StoreV4:
375 return "NVPTXISD::StoreV4";
376 case NVPTXISD::FUN_SHFL_CLAMP:
377 return "NVPTXISD::FUN_SHFL_CLAMP";
378 case NVPTXISD::FUN_SHFR_CLAMP:
379 return "NVPTXISD::FUN_SHFR_CLAMP";
381 return "NVPTXISD::IMAD";
382 case NVPTXISD::Dummy:
383 return "NVPTXISD::Dummy";
384 case NVPTXISD::MUL_WIDE_SIGNED:
385 return "NVPTXISD::MUL_WIDE_SIGNED";
386 case NVPTXISD::MUL_WIDE_UNSIGNED:
387 return "NVPTXISD::MUL_WIDE_UNSIGNED";
388 case NVPTXISD::Tex1DFloatS32: return "NVPTXISD::Tex1DFloatS32";
389 case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
390 case NVPTXISD::Tex1DFloatFloatLevel:
391 return "NVPTXISD::Tex1DFloatFloatLevel";
392 case NVPTXISD::Tex1DFloatFloatGrad:
393 return "NVPTXISD::Tex1DFloatFloatGrad";
394 case NVPTXISD::Tex1DS32S32: return "NVPTXISD::Tex1DS32S32";
395 case NVPTXISD::Tex1DS32Float: return "NVPTXISD::Tex1DS32Float";
396 case NVPTXISD::Tex1DS32FloatLevel:
397 return "NVPTXISD::Tex1DS32FloatLevel";
398 case NVPTXISD::Tex1DS32FloatGrad:
399 return "NVPTXISD::Tex1DS32FloatGrad";
400 case NVPTXISD::Tex1DU32S32: return "NVPTXISD::Tex1DU32S32";
401 case NVPTXISD::Tex1DU32Float: return "NVPTXISD::Tex1DU32Float";
402 case NVPTXISD::Tex1DU32FloatLevel:
403 return "NVPTXISD::Tex1DU32FloatLevel";
404 case NVPTXISD::Tex1DU32FloatGrad:
405 return "NVPTXISD::Tex1DU32FloatGrad";
406 case NVPTXISD::Tex1DArrayFloatS32: return "NVPTXISD::Tex1DArrayFloatS32";
407 case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
408 case NVPTXISD::Tex1DArrayFloatFloatLevel:
409 return "NVPTXISD::Tex1DArrayFloatFloatLevel";
410 case NVPTXISD::Tex1DArrayFloatFloatGrad:
411 return "NVPTXISD::Tex1DArrayFloatFloatGrad";
412 case NVPTXISD::Tex1DArrayS32S32: return "NVPTXISD::Tex1DArrayS32S32";
413 case NVPTXISD::Tex1DArrayS32Float: return "NVPTXISD::Tex1DArrayS32Float";
414 case NVPTXISD::Tex1DArrayS32FloatLevel:
415 return "NVPTXISD::Tex1DArrayS32FloatLevel";
416 case NVPTXISD::Tex1DArrayS32FloatGrad:
417 return "NVPTXISD::Tex1DArrayS32FloatGrad";
418 case NVPTXISD::Tex1DArrayU32S32: return "NVPTXISD::Tex1DArrayU32S32";
419 case NVPTXISD::Tex1DArrayU32Float: return "NVPTXISD::Tex1DArrayU32Float";
420 case NVPTXISD::Tex1DArrayU32FloatLevel:
421 return "NVPTXISD::Tex1DArrayU32FloatLevel";
422 case NVPTXISD::Tex1DArrayU32FloatGrad:
423 return "NVPTXISD::Tex1DArrayU32FloatGrad";
424 case NVPTXISD::Tex2DFloatS32: return "NVPTXISD::Tex2DFloatS32";
425 case NVPTXISD::Tex2DFloatFloat: return "NVPTXISD::Tex2DFloatFloat";
426 case NVPTXISD::Tex2DFloatFloatLevel:
427 return "NVPTXISD::Tex2DFloatFloatLevel";
428 case NVPTXISD::Tex2DFloatFloatGrad:
429 return "NVPTXISD::Tex2DFloatFloatGrad";
430 case NVPTXISD::Tex2DS32S32: return "NVPTXISD::Tex2DS32S32";
431 case NVPTXISD::Tex2DS32Float: return "NVPTXISD::Tex2DS32Float";
432 case NVPTXISD::Tex2DS32FloatLevel:
433 return "NVPTXISD::Tex2DS32FloatLevel";
434 case NVPTXISD::Tex2DS32FloatGrad:
435 return "NVPTXISD::Tex2DS32FloatGrad";
436 case NVPTXISD::Tex2DU32S32: return "NVPTXISD::Tex2DU32S32";
437 case NVPTXISD::Tex2DU32Float: return "NVPTXISD::Tex2DU32Float";
438 case NVPTXISD::Tex2DU32FloatLevel:
439 return "NVPTXISD::Tex2DU32FloatLevel";
440 case NVPTXISD::Tex2DU32FloatGrad:
441 return "NVPTXISD::Tex2DU32FloatGrad";
442 case NVPTXISD::Tex2DArrayFloatS32: return "NVPTXISD::Tex2DArrayFloatS32";
443 case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
444 case NVPTXISD::Tex2DArrayFloatFloatLevel:
445 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
446 case NVPTXISD::Tex2DArrayFloatFloatGrad:
447 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
448 case NVPTXISD::Tex2DArrayS32S32: return "NVPTXISD::Tex2DArrayS32S32";
449 case NVPTXISD::Tex2DArrayS32Float: return "NVPTXISD::Tex2DArrayS32Float";
450 case NVPTXISD::Tex2DArrayS32FloatLevel:
451 return "NVPTXISD::Tex2DArrayS32FloatLevel";
452 case NVPTXISD::Tex2DArrayS32FloatGrad:
453 return "NVPTXISD::Tex2DArrayS32FloatGrad";
454 case NVPTXISD::Tex2DArrayU32S32: return "NVPTXISD::Tex2DArrayU32S32";
455 case NVPTXISD::Tex2DArrayU32Float: return "NVPTXISD::Tex2DArrayU32Float";
456 case NVPTXISD::Tex2DArrayU32FloatLevel:
457 return "NVPTXISD::Tex2DArrayU32FloatLevel";
458 case NVPTXISD::Tex2DArrayU32FloatGrad:
459 return "NVPTXISD::Tex2DArrayU32FloatGrad";
460 case NVPTXISD::Tex3DFloatS32: return "NVPTXISD::Tex3DFloatS32";
461 case NVPTXISD::Tex3DFloatFloat: return "NVPTXISD::Tex3DFloatFloat";
462 case NVPTXISD::Tex3DFloatFloatLevel:
463 return "NVPTXISD::Tex3DFloatFloatLevel";
464 case NVPTXISD::Tex3DFloatFloatGrad:
465 return "NVPTXISD::Tex3DFloatFloatGrad";
466 case NVPTXISD::Tex3DS32S32: return "NVPTXISD::Tex3DS32S32";
467 case NVPTXISD::Tex3DS32Float: return "NVPTXISD::Tex3DS32Float";
468 case NVPTXISD::Tex3DS32FloatLevel:
469 return "NVPTXISD::Tex3DS32FloatLevel";
470 case NVPTXISD::Tex3DS32FloatGrad:
471 return "NVPTXISD::Tex3DS32FloatGrad";
472 case NVPTXISD::Tex3DU32S32: return "NVPTXISD::Tex3DU32S32";
473 case NVPTXISD::Tex3DU32Float: return "NVPTXISD::Tex3DU32Float";
474 case NVPTXISD::Tex3DU32FloatLevel:
475 return "NVPTXISD::Tex3DU32FloatLevel";
476 case NVPTXISD::Tex3DU32FloatGrad:
477 return "NVPTXISD::Tex3DU32FloatGrad";
478 case NVPTXISD::TexCubeFloatFloat: return "NVPTXISD::TexCubeFloatFloat";
479 case NVPTXISD::TexCubeFloatFloatLevel:
480 return "NVPTXISD::TexCubeFloatFloatLevel";
481 case NVPTXISD::TexCubeS32Float: return "NVPTXISD::TexCubeS32Float";
482 case NVPTXISD::TexCubeS32FloatLevel:
483 return "NVPTXISD::TexCubeS32FloatLevel";
484 case NVPTXISD::TexCubeU32Float: return "NVPTXISD::TexCubeU32Float";
485 case NVPTXISD::TexCubeU32FloatLevel:
486 return "NVPTXISD::TexCubeU32FloatLevel";
487 case NVPTXISD::TexCubeArrayFloatFloat:
488 return "NVPTXISD::TexCubeArrayFloatFloat";
489 case NVPTXISD::TexCubeArrayFloatFloatLevel:
490 return "NVPTXISD::TexCubeArrayFloatFloatLevel";
491 case NVPTXISD::TexCubeArrayS32Float:
492 return "NVPTXISD::TexCubeArrayS32Float";
493 case NVPTXISD::TexCubeArrayS32FloatLevel:
494 return "NVPTXISD::TexCubeArrayS32FloatLevel";
495 case NVPTXISD::TexCubeArrayU32Float:
496 return "NVPTXISD::TexCubeArrayU32Float";
497 case NVPTXISD::TexCubeArrayU32FloatLevel:
498 return "NVPTXISD::TexCubeArrayU32FloatLevel";
499 case NVPTXISD::Tld4R2DFloatFloat:
500 return "NVPTXISD::Tld4R2DFloatFloat";
501 case NVPTXISD::Tld4G2DFloatFloat:
502 return "NVPTXISD::Tld4G2DFloatFloat";
503 case NVPTXISD::Tld4B2DFloatFloat:
504 return "NVPTXISD::Tld4B2DFloatFloat";
505 case NVPTXISD::Tld4A2DFloatFloat:
506 return "NVPTXISD::Tld4A2DFloatFloat";
507 case NVPTXISD::Tld4R2DS64Float:
508 return "NVPTXISD::Tld4R2DS64Float";
509 case NVPTXISD::Tld4G2DS64Float:
510 return "NVPTXISD::Tld4G2DS64Float";
511 case NVPTXISD::Tld4B2DS64Float:
512 return "NVPTXISD::Tld4B2DS64Float";
513 case NVPTXISD::Tld4A2DS64Float:
514 return "NVPTXISD::Tld4A2DS64Float";
515 case NVPTXISD::Tld4R2DU64Float:
516 return "NVPTXISD::Tld4R2DU64Float";
517 case NVPTXISD::Tld4G2DU64Float:
518 return "NVPTXISD::Tld4G2DU64Float";
519 case NVPTXISD::Tld4B2DU64Float:
520 return "NVPTXISD::Tld4B2DU64Float";
521 case NVPTXISD::Tld4A2DU64Float:
522 return "NVPTXISD::Tld4A2DU64Float";
524 case NVPTXISD::TexUnified1DFloatS32:
525 return "NVPTXISD::TexUnified1DFloatS32";
526 case NVPTXISD::TexUnified1DFloatFloat:
527 return "NVPTXISD::TexUnified1DFloatFloat";
528 case NVPTXISD::TexUnified1DFloatFloatLevel:
529 return "NVPTXISD::TexUnified1DFloatFloatLevel";
530 case NVPTXISD::TexUnified1DFloatFloatGrad:
531 return "NVPTXISD::TexUnified1DFloatFloatGrad";
532 case NVPTXISD::TexUnified1DS32S32:
533 return "NVPTXISD::TexUnified1DS32S32";
534 case NVPTXISD::TexUnified1DS32Float:
535 return "NVPTXISD::TexUnified1DS32Float";
536 case NVPTXISD::TexUnified1DS32FloatLevel:
537 return "NVPTXISD::TexUnified1DS32FloatLevel";
538 case NVPTXISD::TexUnified1DS32FloatGrad:
539 return "NVPTXISD::TexUnified1DS32FloatGrad";
540 case NVPTXISD::TexUnified1DU32S32:
541 return "NVPTXISD::TexUnified1DU32S32";
542 case NVPTXISD::TexUnified1DU32Float:
543 return "NVPTXISD::TexUnified1DU32Float";
544 case NVPTXISD::TexUnified1DU32FloatLevel:
545 return "NVPTXISD::TexUnified1DU32FloatLevel";
546 case NVPTXISD::TexUnified1DU32FloatGrad:
547 return "NVPTXISD::TexUnified1DU32FloatGrad";
548 case NVPTXISD::TexUnified1DArrayFloatS32:
549 return "NVPTXISD::TexUnified1DArrayFloatS32";
550 case NVPTXISD::TexUnified1DArrayFloatFloat:
551 return "NVPTXISD::TexUnified1DArrayFloatFloat";
552 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
553 return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
554 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
555 return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
556 case NVPTXISD::TexUnified1DArrayS32S32:
557 return "NVPTXISD::TexUnified1DArrayS32S32";
558 case NVPTXISD::TexUnified1DArrayS32Float:
559 return "NVPTXISD::TexUnified1DArrayS32Float";
560 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
561 return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
562 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
563 return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
564 case NVPTXISD::TexUnified1DArrayU32S32:
565 return "NVPTXISD::TexUnified1DArrayU32S32";
566 case NVPTXISD::TexUnified1DArrayU32Float:
567 return "NVPTXISD::TexUnified1DArrayU32Float";
568 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
569 return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
570 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
571 return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
572 case NVPTXISD::TexUnified2DFloatS32:
573 return "NVPTXISD::TexUnified2DFloatS32";
574 case NVPTXISD::TexUnified2DFloatFloat:
575 return "NVPTXISD::TexUnified2DFloatFloat";
576 case NVPTXISD::TexUnified2DFloatFloatLevel:
577 return "NVPTXISD::TexUnified2DFloatFloatLevel";
578 case NVPTXISD::TexUnified2DFloatFloatGrad:
579 return "NVPTXISD::TexUnified2DFloatFloatGrad";
580 case NVPTXISD::TexUnified2DS32S32:
581 return "NVPTXISD::TexUnified2DS32S32";
582 case NVPTXISD::TexUnified2DS32Float:
583 return "NVPTXISD::TexUnified2DS32Float";
584 case NVPTXISD::TexUnified2DS32FloatLevel:
585 return "NVPTXISD::TexUnified2DS32FloatLevel";
586 case NVPTXISD::TexUnified2DS32FloatGrad:
587 return "NVPTXISD::TexUnified2DS32FloatGrad";
588 case NVPTXISD::TexUnified2DU32S32:
589 return "NVPTXISD::TexUnified2DU32S32";
590 case NVPTXISD::TexUnified2DU32Float:
591 return "NVPTXISD::TexUnified2DU32Float";
592 case NVPTXISD::TexUnified2DU32FloatLevel:
593 return "NVPTXISD::TexUnified2DU32FloatLevel";
594 case NVPTXISD::TexUnified2DU32FloatGrad:
595 return "NVPTXISD::TexUnified2DU32FloatGrad";
596 case NVPTXISD::TexUnified2DArrayFloatS32:
597 return "NVPTXISD::TexUnified2DArrayFloatS32";
598 case NVPTXISD::TexUnified2DArrayFloatFloat:
599 return "NVPTXISD::TexUnified2DArrayFloatFloat";
600 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
601 return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
602 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
603 return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
604 case NVPTXISD::TexUnified2DArrayS32S32:
605 return "NVPTXISD::TexUnified2DArrayS32S32";
606 case NVPTXISD::TexUnified2DArrayS32Float:
607 return "NVPTXISD::TexUnified2DArrayS32Float";
608 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
609 return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
610 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
611 return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
612 case NVPTXISD::TexUnified2DArrayU32S32:
613 return "NVPTXISD::TexUnified2DArrayU32S32";
614 case NVPTXISD::TexUnified2DArrayU32Float:
615 return "NVPTXISD::TexUnified2DArrayU32Float";
616 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
617 return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
618 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
619 return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
620 case NVPTXISD::TexUnified3DFloatS32:
621 return "NVPTXISD::TexUnified3DFloatS32";
622 case NVPTXISD::TexUnified3DFloatFloat:
623 return "NVPTXISD::TexUnified3DFloatFloat";
624 case NVPTXISD::TexUnified3DFloatFloatLevel:
625 return "NVPTXISD::TexUnified3DFloatFloatLevel";
626 case NVPTXISD::TexUnified3DFloatFloatGrad:
627 return "NVPTXISD::TexUnified3DFloatFloatGrad";
628 case NVPTXISD::TexUnified3DS32S32:
629 return "NVPTXISD::TexUnified3DS32S32";
630 case NVPTXISD::TexUnified3DS32Float:
631 return "NVPTXISD::TexUnified3DS32Float";
632 case NVPTXISD::TexUnified3DS32FloatLevel:
633 return "NVPTXISD::TexUnified3DS32FloatLevel";
634 case NVPTXISD::TexUnified3DS32FloatGrad:
635 return "NVPTXISD::TexUnified3DS32FloatGrad";
636 case NVPTXISD::TexUnified3DU32S32:
637 return "NVPTXISD::TexUnified3DU32S32";
638 case NVPTXISD::TexUnified3DU32Float:
639 return "NVPTXISD::TexUnified3DU32Float";
640 case NVPTXISD::TexUnified3DU32FloatLevel:
641 return "NVPTXISD::TexUnified3DU32FloatLevel";
642 case NVPTXISD::TexUnified3DU32FloatGrad:
643 return "NVPTXISD::TexUnified3DU32FloatGrad";
644 case NVPTXISD::TexUnifiedCubeFloatFloat:
645 return "NVPTXISD::TexUnifiedCubeFloatFloat";
646 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
647 return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
648 case NVPTXISD::TexUnifiedCubeS32Float:
649 return "NVPTXISD::TexUnifiedCubeS32Float";
650 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
651 return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
652 case NVPTXISD::TexUnifiedCubeU32Float:
653 return "NVPTXISD::TexUnifiedCubeU32Float";
654 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
655 return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
656 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
657 return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
658 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
659 return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
660 case NVPTXISD::TexUnifiedCubeArrayS32Float:
661 return "NVPTXISD::TexUnifiedCubeArrayS32Float";
662 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
663 return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
664 case NVPTXISD::TexUnifiedCubeArrayU32Float:
665 return "NVPTXISD::TexUnifiedCubeArrayU32Float";
666 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
667 return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
668 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
669 return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
670 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
671 return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
672 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
673 return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
674 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
675 return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
676 case NVPTXISD::Tld4UnifiedR2DS64Float:
677 return "NVPTXISD::Tld4UnifiedR2DS64Float";
678 case NVPTXISD::Tld4UnifiedG2DS64Float:
679 return "NVPTXISD::Tld4UnifiedG2DS64Float";
680 case NVPTXISD::Tld4UnifiedB2DS64Float:
681 return "NVPTXISD::Tld4UnifiedB2DS64Float";
682 case NVPTXISD::Tld4UnifiedA2DS64Float:
683 return "NVPTXISD::Tld4UnifiedA2DS64Float";
684 case NVPTXISD::Tld4UnifiedR2DU64Float:
685 return "NVPTXISD::Tld4UnifiedR2DU64Float";
686 case NVPTXISD::Tld4UnifiedG2DU64Float:
687 return "NVPTXISD::Tld4UnifiedG2DU64Float";
688 case NVPTXISD::Tld4UnifiedB2DU64Float:
689 return "NVPTXISD::Tld4UnifiedB2DU64Float";
690 case NVPTXISD::Tld4UnifiedA2DU64Float:
691 return "NVPTXISD::Tld4UnifiedA2DU64Float";
693 case NVPTXISD::Suld1DI8Clamp: return "NVPTXISD::Suld1DI8Clamp";
694 case NVPTXISD::Suld1DI16Clamp: return "NVPTXISD::Suld1DI16Clamp";
695 case NVPTXISD::Suld1DI32Clamp: return "NVPTXISD::Suld1DI32Clamp";
696 case NVPTXISD::Suld1DI64Clamp: return "NVPTXISD::Suld1DI64Clamp";
697 case NVPTXISD::Suld1DV2I8Clamp: return "NVPTXISD::Suld1DV2I8Clamp";
698 case NVPTXISD::Suld1DV2I16Clamp: return "NVPTXISD::Suld1DV2I16Clamp";
699 case NVPTXISD::Suld1DV2I32Clamp: return "NVPTXISD::Suld1DV2I32Clamp";
700 case NVPTXISD::Suld1DV2I64Clamp: return "NVPTXISD::Suld1DV2I64Clamp";
701 case NVPTXISD::Suld1DV4I8Clamp: return "NVPTXISD::Suld1DV4I8Clamp";
702 case NVPTXISD::Suld1DV4I16Clamp: return "NVPTXISD::Suld1DV4I16Clamp";
703 case NVPTXISD::Suld1DV4I32Clamp: return "NVPTXISD::Suld1DV4I32Clamp";
705 case NVPTXISD::Suld1DArrayI8Clamp: return "NVPTXISD::Suld1DArrayI8Clamp";
706 case NVPTXISD::Suld1DArrayI16Clamp: return "NVPTXISD::Suld1DArrayI16Clamp";
707 case NVPTXISD::Suld1DArrayI32Clamp: return "NVPTXISD::Suld1DArrayI32Clamp";
708 case NVPTXISD::Suld1DArrayI64Clamp: return "NVPTXISD::Suld1DArrayI64Clamp";
709 case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
710 case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
711 case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
712 case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
713 case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
714 case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
715 case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
717 case NVPTXISD::Suld2DI8Clamp: return "NVPTXISD::Suld2DI8Clamp";
718 case NVPTXISD::Suld2DI16Clamp: return "NVPTXISD::Suld2DI16Clamp";
719 case NVPTXISD::Suld2DI32Clamp: return "NVPTXISD::Suld2DI32Clamp";
720 case NVPTXISD::Suld2DI64Clamp: return "NVPTXISD::Suld2DI64Clamp";
721 case NVPTXISD::Suld2DV2I8Clamp: return "NVPTXISD::Suld2DV2I8Clamp";
722 case NVPTXISD::Suld2DV2I16Clamp: return "NVPTXISD::Suld2DV2I16Clamp";
723 case NVPTXISD::Suld2DV2I32Clamp: return "NVPTXISD::Suld2DV2I32Clamp";
724 case NVPTXISD::Suld2DV2I64Clamp: return "NVPTXISD::Suld2DV2I64Clamp";
725 case NVPTXISD::Suld2DV4I8Clamp: return "NVPTXISD::Suld2DV4I8Clamp";
726 case NVPTXISD::Suld2DV4I16Clamp: return "NVPTXISD::Suld2DV4I16Clamp";
727 case NVPTXISD::Suld2DV4I32Clamp: return "NVPTXISD::Suld2DV4I32Clamp";
729 case NVPTXISD::Suld2DArrayI8Clamp: return "NVPTXISD::Suld2DArrayI8Clamp";
730 case NVPTXISD::Suld2DArrayI16Clamp: return "NVPTXISD::Suld2DArrayI16Clamp";
731 case NVPTXISD::Suld2DArrayI32Clamp: return "NVPTXISD::Suld2DArrayI32Clamp";
732 case NVPTXISD::Suld2DArrayI64Clamp: return "NVPTXISD::Suld2DArrayI64Clamp";
733 case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
734 case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
735 case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
736 case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
737 case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
738 case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
739 case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
741 case NVPTXISD::Suld3DI8Clamp: return "NVPTXISD::Suld3DI8Clamp";
742 case NVPTXISD::Suld3DI16Clamp: return "NVPTXISD::Suld3DI16Clamp";
743 case NVPTXISD::Suld3DI32Clamp: return "NVPTXISD::Suld3DI32Clamp";
744 case NVPTXISD::Suld3DI64Clamp: return "NVPTXISD::Suld3DI64Clamp";
745 case NVPTXISD::Suld3DV2I8Clamp: return "NVPTXISD::Suld3DV2I8Clamp";
746 case NVPTXISD::Suld3DV2I16Clamp: return "NVPTXISD::Suld3DV2I16Clamp";
747 case NVPTXISD::Suld3DV2I32Clamp: return "NVPTXISD::Suld3DV2I32Clamp";
748 case NVPTXISD::Suld3DV2I64Clamp: return "NVPTXISD::Suld3DV2I64Clamp";
749 case NVPTXISD::Suld3DV4I8Clamp: return "NVPTXISD::Suld3DV4I8Clamp";
750 case NVPTXISD::Suld3DV4I16Clamp: return "NVPTXISD::Suld3DV4I16Clamp";
751 case NVPTXISD::Suld3DV4I32Clamp: return "NVPTXISD::Suld3DV4I32Clamp";
753 case NVPTXISD::Suld1DI8Trap: return "NVPTXISD::Suld1DI8Trap";
754 case NVPTXISD::Suld1DI16Trap: return "NVPTXISD::Suld1DI16Trap";
755 case NVPTXISD::Suld1DI32Trap: return "NVPTXISD::Suld1DI32Trap";
756 case NVPTXISD::Suld1DI64Trap: return "NVPTXISD::Suld1DI64Trap";
757 case NVPTXISD::Suld1DV2I8Trap: return "NVPTXISD::Suld1DV2I8Trap";
758 case NVPTXISD::Suld1DV2I16Trap: return "NVPTXISD::Suld1DV2I16Trap";
759 case NVPTXISD::Suld1DV2I32Trap: return "NVPTXISD::Suld1DV2I32Trap";
760 case NVPTXISD::Suld1DV2I64Trap: return "NVPTXISD::Suld1DV2I64Trap";
761 case NVPTXISD::Suld1DV4I8Trap: return "NVPTXISD::Suld1DV4I8Trap";
762 case NVPTXISD::Suld1DV4I16Trap: return "NVPTXISD::Suld1DV4I16Trap";
763 case NVPTXISD::Suld1DV4I32Trap: return "NVPTXISD::Suld1DV4I32Trap";
765 case NVPTXISD::Suld1DArrayI8Trap: return "NVPTXISD::Suld1DArrayI8Trap";
766 case NVPTXISD::Suld1DArrayI16Trap: return "NVPTXISD::Suld1DArrayI16Trap";
767 case NVPTXISD::Suld1DArrayI32Trap: return "NVPTXISD::Suld1DArrayI32Trap";
768 case NVPTXISD::Suld1DArrayI64Trap: return "NVPTXISD::Suld1DArrayI64Trap";
769 case NVPTXISD::Suld1DArrayV2I8Trap: return "NVPTXISD::Suld1DArrayV2I8Trap";
770 case NVPTXISD::Suld1DArrayV2I16Trap: return "NVPTXISD::Suld1DArrayV2I16Trap";
771 case NVPTXISD::Suld1DArrayV2I32Trap: return "NVPTXISD::Suld1DArrayV2I32Trap";
772 case NVPTXISD::Suld1DArrayV2I64Trap: return "NVPTXISD::Suld1DArrayV2I64Trap";
773 case NVPTXISD::Suld1DArrayV4I8Trap: return "NVPTXISD::Suld1DArrayV4I8Trap";
774 case NVPTXISD::Suld1DArrayV4I16Trap: return "NVPTXISD::Suld1DArrayV4I16Trap";
775 case NVPTXISD::Suld1DArrayV4I32Trap: return "NVPTXISD::Suld1DArrayV4I32Trap";
777 case NVPTXISD::Suld2DI8Trap: return "NVPTXISD::Suld2DI8Trap";
778 case NVPTXISD::Suld2DI16Trap: return "NVPTXISD::Suld2DI16Trap";
779 case NVPTXISD::Suld2DI32Trap: return "NVPTXISD::Suld2DI32Trap";
780 case NVPTXISD::Suld2DI64Trap: return "NVPTXISD::Suld2DI64Trap";
781 case NVPTXISD::Suld2DV2I8Trap: return "NVPTXISD::Suld2DV2I8Trap";
782 case NVPTXISD::Suld2DV2I16Trap: return "NVPTXISD::Suld2DV2I16Trap";
783 case NVPTXISD::Suld2DV2I32Trap: return "NVPTXISD::Suld2DV2I32Trap";
784 case NVPTXISD::Suld2DV2I64Trap: return "NVPTXISD::Suld2DV2I64Trap";
785 case NVPTXISD::Suld2DV4I8Trap: return "NVPTXISD::Suld2DV4I8Trap";
786 case NVPTXISD::Suld2DV4I16Trap: return "NVPTXISD::Suld2DV4I16Trap";
787 case NVPTXISD::Suld2DV4I32Trap: return "NVPTXISD::Suld2DV4I32Trap";
789 case NVPTXISD::Suld2DArrayI8Trap: return "NVPTXISD::Suld2DArrayI8Trap";
790 case NVPTXISD::Suld2DArrayI16Trap: return "NVPTXISD::Suld2DArrayI16Trap";
791 case NVPTXISD::Suld2DArrayI32Trap: return "NVPTXISD::Suld2DArrayI32Trap";
792 case NVPTXISD::Suld2DArrayI64Trap: return "NVPTXISD::Suld2DArrayI64Trap";
793 case NVPTXISD::Suld2DArrayV2I8Trap: return "NVPTXISD::Suld2DArrayV2I8Trap";
794 case NVPTXISD::Suld2DArrayV2I16Trap: return "NVPTXISD::Suld2DArrayV2I16Trap";
795 case NVPTXISD::Suld2DArrayV2I32Trap: return "NVPTXISD::Suld2DArrayV2I32Trap";
796 case NVPTXISD::Suld2DArrayV2I64Trap: return "NVPTXISD::Suld2DArrayV2I64Trap";
797 case NVPTXISD::Suld2DArrayV4I8Trap: return "NVPTXISD::Suld2DArrayV4I8Trap";
798 case NVPTXISD::Suld2DArrayV4I16Trap: return "NVPTXISD::Suld2DArrayV4I16Trap";
799 case NVPTXISD::Suld2DArrayV4I32Trap: return "NVPTXISD::Suld2DArrayV4I32Trap";
801 case NVPTXISD::Suld3DI8Trap: return "NVPTXISD::Suld3DI8Trap";
802 case NVPTXISD::Suld3DI16Trap: return "NVPTXISD::Suld3DI16Trap";
803 case NVPTXISD::Suld3DI32Trap: return "NVPTXISD::Suld3DI32Trap";
804 case NVPTXISD::Suld3DI64Trap: return "NVPTXISD::Suld3DI64Trap";
805 case NVPTXISD::Suld3DV2I8Trap: return "NVPTXISD::Suld3DV2I8Trap";
806 case NVPTXISD::Suld3DV2I16Trap: return "NVPTXISD::Suld3DV2I16Trap";
807 case NVPTXISD::Suld3DV2I32Trap: return "NVPTXISD::Suld3DV2I32Trap";
808 case NVPTXISD::Suld3DV2I64Trap: return "NVPTXISD::Suld3DV2I64Trap";
809 case NVPTXISD::Suld3DV4I8Trap: return "NVPTXISD::Suld3DV4I8Trap";
810 case NVPTXISD::Suld3DV4I16Trap: return "NVPTXISD::Suld3DV4I16Trap";
811 case NVPTXISD::Suld3DV4I32Trap: return "NVPTXISD::Suld3DV4I32Trap";
813 case NVPTXISD::Suld1DI8Zero: return "NVPTXISD::Suld1DI8Zero";
814 case NVPTXISD::Suld1DI16Zero: return "NVPTXISD::Suld1DI16Zero";
815 case NVPTXISD::Suld1DI32Zero: return "NVPTXISD::Suld1DI32Zero";
816 case NVPTXISD::Suld1DI64Zero: return "NVPTXISD::Suld1DI64Zero";
817 case NVPTXISD::Suld1DV2I8Zero: return "NVPTXISD::Suld1DV2I8Zero";
818 case NVPTXISD::Suld1DV2I16Zero: return "NVPTXISD::Suld1DV2I16Zero";
819 case NVPTXISD::Suld1DV2I32Zero: return "NVPTXISD::Suld1DV2I32Zero";
820 case NVPTXISD::Suld1DV2I64Zero: return "NVPTXISD::Suld1DV2I64Zero";
821 case NVPTXISD::Suld1DV4I8Zero: return "NVPTXISD::Suld1DV4I8Zero";
822 case NVPTXISD::Suld1DV4I16Zero: return "NVPTXISD::Suld1DV4I16Zero";
823 case NVPTXISD::Suld1DV4I32Zero: return "NVPTXISD::Suld1DV4I32Zero";
825 case NVPTXISD::Suld1DArrayI8Zero: return "NVPTXISD::Suld1DArrayI8Zero";
826 case NVPTXISD::Suld1DArrayI16Zero: return "NVPTXISD::Suld1DArrayI16Zero";
827 case NVPTXISD::Suld1DArrayI32Zero: return "NVPTXISD::Suld1DArrayI32Zero";
828 case NVPTXISD::Suld1DArrayI64Zero: return "NVPTXISD::Suld1DArrayI64Zero";
829 case NVPTXISD::Suld1DArrayV2I8Zero: return "NVPTXISD::Suld1DArrayV2I8Zero";
830 case NVPTXISD::Suld1DArrayV2I16Zero: return "NVPTXISD::Suld1DArrayV2I16Zero";
831 case NVPTXISD::Suld1DArrayV2I32Zero: return "NVPTXISD::Suld1DArrayV2I32Zero";
832 case NVPTXISD::Suld1DArrayV2I64Zero: return "NVPTXISD::Suld1DArrayV2I64Zero";
833 case NVPTXISD::Suld1DArrayV4I8Zero: return "NVPTXISD::Suld1DArrayV4I8Zero";
834 case NVPTXISD::Suld1DArrayV4I16Zero: return "NVPTXISD::Suld1DArrayV4I16Zero";
835 case NVPTXISD::Suld1DArrayV4I32Zero: return "NVPTXISD::Suld1DArrayV4I32Zero";
837 case NVPTXISD::Suld2DI8Zero: return "NVPTXISD::Suld2DI8Zero";
838 case NVPTXISD::Suld2DI16Zero: return "NVPTXISD::Suld2DI16Zero";
839 case NVPTXISD::Suld2DI32Zero: return "NVPTXISD::Suld2DI32Zero";
840 case NVPTXISD::Suld2DI64Zero: return "NVPTXISD::Suld2DI64Zero";
841 case NVPTXISD::Suld2DV2I8Zero: return "NVPTXISD::Suld2DV2I8Zero";
842 case NVPTXISD::Suld2DV2I16Zero: return "NVPTXISD::Suld2DV2I16Zero";
843 case NVPTXISD::Suld2DV2I32Zero: return "NVPTXISD::Suld2DV2I32Zero";
844 case NVPTXISD::Suld2DV2I64Zero: return "NVPTXISD::Suld2DV2I64Zero";
845 case NVPTXISD::Suld2DV4I8Zero: return "NVPTXISD::Suld2DV4I8Zero";
846 case NVPTXISD::Suld2DV4I16Zero: return "NVPTXISD::Suld2DV4I16Zero";
847 case NVPTXISD::Suld2DV4I32Zero: return "NVPTXISD::Suld2DV4I32Zero";
849 case NVPTXISD::Suld2DArrayI8Zero: return "NVPTXISD::Suld2DArrayI8Zero";
850 case NVPTXISD::Suld2DArrayI16Zero: return "NVPTXISD::Suld2DArrayI16Zero";
851 case NVPTXISD::Suld2DArrayI32Zero: return "NVPTXISD::Suld2DArrayI32Zero";
852 case NVPTXISD::Suld2DArrayI64Zero: return "NVPTXISD::Suld2DArrayI64Zero";
853 case NVPTXISD::Suld2DArrayV2I8Zero: return "NVPTXISD::Suld2DArrayV2I8Zero";
854 case NVPTXISD::Suld2DArrayV2I16Zero: return "NVPTXISD::Suld2DArrayV2I16Zero";
855 case NVPTXISD::Suld2DArrayV2I32Zero: return "NVPTXISD::Suld2DArrayV2I32Zero";
856 case NVPTXISD::Suld2DArrayV2I64Zero: return "NVPTXISD::Suld2DArrayV2I64Zero";
857 case NVPTXISD::Suld2DArrayV4I8Zero: return "NVPTXISD::Suld2DArrayV4I8Zero";
858 case NVPTXISD::Suld2DArrayV4I16Zero: return "NVPTXISD::Suld2DArrayV4I16Zero";
859 case NVPTXISD::Suld2DArrayV4I32Zero: return "NVPTXISD::Suld2DArrayV4I32Zero";
861 case NVPTXISD::Suld3DI8Zero: return "NVPTXISD::Suld3DI8Zero";
862 case NVPTXISD::Suld3DI16Zero: return "NVPTXISD::Suld3DI16Zero";
863 case NVPTXISD::Suld3DI32Zero: return "NVPTXISD::Suld3DI32Zero";
864 case NVPTXISD::Suld3DI64Zero: return "NVPTXISD::Suld3DI64Zero";
865 case NVPTXISD::Suld3DV2I8Zero: return "NVPTXISD::Suld3DV2I8Zero";
866 case NVPTXISD::Suld3DV2I16Zero: return "NVPTXISD::Suld3DV2I16Zero";
867 case NVPTXISD::Suld3DV2I32Zero: return "NVPTXISD::Suld3DV2I32Zero";
868 case NVPTXISD::Suld3DV2I64Zero: return "NVPTXISD::Suld3DV2I64Zero";
869 case NVPTXISD::Suld3DV4I8Zero: return "NVPTXISD::Suld3DV4I8Zero";
870 case NVPTXISD::Suld3DV4I16Zero: return "NVPTXISD::Suld3DV4I16Zero";
871 case NVPTXISD::Suld3DV4I32Zero: return "NVPTXISD::Suld3DV4I32Zero";
876 TargetLoweringBase::LegalizeTypeAction
877 NVPTXTargetLowering::getPreferredVectorAction(EVT VT) const {
878 if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
879 return TypeSplitVector;
881 return TargetLoweringBase::getPreferredVectorAction(VT);
885 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
887 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
888 auto PtrVT = getPointerTy(DAG.getDataLayout());
889 Op = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
890 return DAG.getNode(NVPTXISD::Wrapper, dl, PtrVT, Op);
893 std::string NVPTXTargetLowering::getPrototype(
894 const DataLayout &DL, Type *retTy, const ArgListTy &Args,
895 const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment,
896 const ImmutableCallSite *CS) const {
897 auto PtrVT = getPointerTy(DL);
899 bool isABI = (STI.getSmVersion() >= 20);
900 assert(isABI && "Non-ABI compilation is not supported");
905 O << "prototype_" << uniqueCallSite << " : .callprototype ";
907 if (retTy->getTypeID() == Type::VoidTyID) {
911 if (retTy->isFloatingPointTy() || retTy->isIntegerTy()) {
913 if (const IntegerType *ITy = dyn_cast<IntegerType>(retTy)) {
914 size = ITy->getBitWidth();
918 assert(retTy->isFloatingPointTy() &&
919 "Floating point type expected here");
920 size = retTy->getPrimitiveSizeInBits();
923 O << ".param .b" << size << " _";
924 } else if (isa<PointerType>(retTy)) {
925 O << ".param .b" << PtrVT.getSizeInBits() << " _";
926 } else if ((retTy->getTypeID() == Type::StructTyID) ||
927 isa<VectorType>(retTy)) {
928 auto &DL = CS->getCalledFunction()->getParent()->getDataLayout();
929 O << ".param .align " << retAlignment << " .b8 _["
930 << DL.getTypeAllocSize(retTy) << "]";
932 llvm_unreachable("Unknown return type");
941 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
942 Type *Ty = Args[i].Ty;
948 if (!Outs[OIdx].Flags.isByVal()) {
949 if (Ty->isAggregateType() || Ty->isVectorTy()) {
951 const CallInst *CallI = cast<CallInst>(CS->getInstruction());
952 // +1 because index 0 is reserved for return type alignment
953 if (!llvm::getAlign(*CallI, i + 1, align))
954 align = DL.getABITypeAlignment(Ty);
955 unsigned sz = DL.getTypeAllocSize(Ty);
956 O << ".param .align " << align << " .b8 ";
958 O << "[" << sz << "]";
959 // update the index for Outs
960 SmallVector<EVT, 16> vtparts;
961 ComputeValueVTs(*this, DL, Ty, vtparts);
962 if (unsigned len = vtparts.size())
966 // i8 types in IR will be i16 types in SDAG
967 assert((getValueType(DL, Ty) == Outs[OIdx].VT ||
968 (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
969 "type mismatch between callee prototype and arguments");
972 if (isa<IntegerType>(Ty)) {
973 sz = cast<IntegerType>(Ty)->getBitWidth();
976 } else if (isa<PointerType>(Ty))
977 sz = PtrVT.getSizeInBits();
979 sz = Ty->getPrimitiveSizeInBits();
980 O << ".param .b" << sz << " ";
984 const PointerType *PTy = dyn_cast<PointerType>(Ty);
985 assert(PTy && "Param with byval attribute should be a pointer type");
986 Type *ETy = PTy->getElementType();
988 unsigned align = Outs[OIdx].Flags.getByValAlign();
989 unsigned sz = DL.getTypeAllocSize(ETy);
990 O << ".param .align " << align << " .b8 ";
992 O << "[" << sz << "]";
999 NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
1000 const ImmutableCallSite *CS,
1002 unsigned Idx) const {
1004 const Value *DirectCallee = CS->getCalledFunction();
1006 if (!DirectCallee) {
1007 // We don't have a direct function symbol, but that may be because of
1008 // constant cast instructions in the call.
1009 const Instruction *CalleeI = CS->getInstruction();
1010 assert(CalleeI && "Call target is not a function or derived value?");
1012 // With bitcast'd call targets, the instruction will be the call
1013 if (isa<CallInst>(CalleeI)) {
1014 // Check if we have call alignment metadata
1015 if (llvm::getAlign(*cast<CallInst>(CalleeI), Idx, Align))
1018 const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
1019 // Ignore any bitcast instructions
1020 while(isa<ConstantExpr>(CalleeV)) {
1021 const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
1024 // Look through the bitcast
1025 CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
1028 // We have now looked past all of the bitcasts. Do we finally have a
1030 if (isa<Function>(CalleeV))
1031 DirectCallee = CalleeV;
1035 // Check for function alignment information if we found that the
1036 // ultimate target is a Function
1038 if (llvm::getAlign(*cast<Function>(DirectCallee), Idx, Align))
1041 // Call is indirect or alignment information is not available, fall back to
1042 // the ABI type alignment
1043 auto &DL = CS->getCaller()->getParent()->getDataLayout();
1044 return DL.getABITypeAlignment(Ty);
1047 SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1048 SmallVectorImpl<SDValue> &InVals) const {
1049 SelectionDAG &DAG = CLI.DAG;
1051 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1052 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1053 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1054 SDValue Chain = CLI.Chain;
1055 SDValue Callee = CLI.Callee;
1056 bool &isTailCall = CLI.IsTailCall;
1057 ArgListTy &Args = CLI.getArgs();
1058 Type *retTy = CLI.RetTy;
1059 ImmutableCallSite *CS = CLI.CS;
1061 bool isABI = (STI.getSmVersion() >= 20);
1062 assert(isABI && "Non-ABI compilation is not supported");
1065 MachineFunction &MF = DAG.getMachineFunction();
1066 const Function *F = MF.getFunction();
1067 auto &DL = MF.getDataLayout();
1069 SDValue tempChain = Chain;
1070 Chain = DAG.getCALLSEQ_START(Chain,
1071 DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1073 SDValue InFlag = Chain.getValue(1);
1075 unsigned paramCount = 0;
1076 // Args.size() and Outs.size() need not match.
1077 // Outs.size() will be larger
1078 // * if there is an aggregate argument with multiple fields (each field
1079 // showing up separately in Outs)
1080 // * if there is a vector argument with more than typical vector-length
1081 // elements (generally if more than 4) where each vector element is
1082 // individually present in Outs.
1083 // So a different index should be used for indexing into Outs/OutVals.
1084 // See similar issue in LowerFormalArguments.
1086 // Declare the .params or .reg need to pass values
1088 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
1089 EVT VT = Outs[OIdx].VT;
1090 Type *Ty = Args[i].Ty;
1092 if (!Outs[OIdx].Flags.isByVal()) {
1093 if (Ty->isAggregateType()) {
1095 SmallVector<EVT, 16> vtparts;
1096 SmallVector<uint64_t, 16> Offsets;
1097 ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts, &Offsets,
1100 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
1101 // declare .param .align <align> .b8 .param<n>[<size>];
1102 unsigned sz = DL.getTypeAllocSize(Ty);
1103 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1104 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, dl,
1106 DAG.getConstant(paramCount, dl, MVT::i32),
1107 DAG.getConstant(sz, dl, MVT::i32),
1109 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1111 InFlag = Chain.getValue(1);
1112 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1113 EVT elemtype = vtparts[j];
1114 unsigned ArgAlign = GreatestCommonDivisor64(align, Offsets[j]);
1115 if (elemtype.isInteger() && (sz < 8))
1117 SDValue StVal = OutVals[OIdx];
1118 if (elemtype.getSizeInBits() < 16) {
1119 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
1121 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1122 SDValue CopyParamOps[] = { Chain,
1123 DAG.getConstant(paramCount, dl, MVT::i32),
1124 DAG.getConstant(Offsets[j], dl, MVT::i32),
1126 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
1127 CopyParamVTs, CopyParamOps,
1128 elemtype, MachinePointerInfo(),
1130 InFlag = Chain.getValue(1);
1133 if (vtparts.size() > 0)
1138 if (Ty->isVectorTy()) {
1139 EVT ObjectVT = getValueType(DL, Ty);
1140 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
1141 // declare .param .align <align> .b8 .param<n>[<size>];
1142 unsigned sz = DL.getTypeAllocSize(Ty);
1143 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1144 SDValue DeclareParamOps[] = { Chain,
1145 DAG.getConstant(align, dl, MVT::i32),
1146 DAG.getConstant(paramCount, dl, MVT::i32),
1147 DAG.getConstant(sz, dl, MVT::i32),
1149 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1151 InFlag = Chain.getValue(1);
1152 unsigned NumElts = ObjectVT.getVectorNumElements();
1153 EVT EltVT = ObjectVT.getVectorElementType();
1155 bool NeedExtend = false;
1156 if (EltVT.getSizeInBits() < 16) {
1163 SDValue Elt = OutVals[OIdx++];
1165 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt);
1167 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1168 SDValue CopyParamOps[] = { Chain,
1169 DAG.getConstant(paramCount, dl, MVT::i32),
1170 DAG.getConstant(0, dl, MVT::i32), Elt,
1172 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
1173 CopyParamVTs, CopyParamOps,
1174 MemVT, MachinePointerInfo());
1175 InFlag = Chain.getValue(1);
1176 } else if (NumElts == 2) {
1177 SDValue Elt0 = OutVals[OIdx++];
1178 SDValue Elt1 = OutVals[OIdx++];
1180 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0);
1181 Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1);
1184 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1185 SDValue CopyParamOps[] = { Chain,
1186 DAG.getConstant(paramCount, dl, MVT::i32),
1187 DAG.getConstant(0, dl, MVT::i32), Elt0,
1189 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
1190 CopyParamVTs, CopyParamOps,
1191 MemVT, MachinePointerInfo());
1192 InFlag = Chain.getValue(1);
1194 unsigned curOffset = 0;
1196 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
1198 // vector will be expanded to a power of 2 elements, so we know we can
1199 // always round up to the next multiple of 4 when creating the vector
1201 // e.g. 4 elem => 1 st.v4
1202 // 6 elem => 2 st.v4
1203 // 8 elem => 2 st.v4
1204 // 11 elem => 3 st.v4
1205 unsigned VecSize = 4;
1206 if (EltVT.getSizeInBits() == 64)
1209 // This is potentially only part of a vector, so assume all elements
1210 // are packed together.
1211 unsigned PerStoreOffset = MemVT.getStoreSizeInBits() / 8 * VecSize;
1213 for (unsigned i = 0; i < NumElts; i += VecSize) {
1216 SmallVector<SDValue, 8> Ops;
1217 Ops.push_back(Chain);
1218 Ops.push_back(DAG.getConstant(paramCount, dl, MVT::i32));
1219 Ops.push_back(DAG.getConstant(curOffset, dl, MVT::i32));
1221 unsigned Opc = NVPTXISD::StoreParamV2;
1223 StoreVal = OutVals[OIdx++];
1225 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1226 Ops.push_back(StoreVal);
1228 if (i + 1 < NumElts) {
1229 StoreVal = OutVals[OIdx++];
1232 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1234 StoreVal = DAG.getUNDEF(EltVT);
1236 Ops.push_back(StoreVal);
1239 Opc = NVPTXISD::StoreParamV4;
1240 if (i + 2 < NumElts) {
1241 StoreVal = OutVals[OIdx++];
1244 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1246 StoreVal = DAG.getUNDEF(EltVT);
1248 Ops.push_back(StoreVal);
1250 if (i + 3 < NumElts) {
1251 StoreVal = OutVals[OIdx++];
1254 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1256 StoreVal = DAG.getUNDEF(EltVT);
1258 Ops.push_back(StoreVal);
1261 Ops.push_back(InFlag);
1263 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1264 Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, Ops,
1265 MemVT, MachinePointerInfo());
1266 InFlag = Chain.getValue(1);
1267 curOffset += PerStoreOffset;
1275 // for ABI, declare .param .b<size> .param<n>;
1276 unsigned sz = VT.getSizeInBits();
1277 bool needExtend = false;
1278 if (VT.isInteger()) {
1284 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1285 SDValue DeclareParamOps[] = { Chain,
1286 DAG.getConstant(paramCount, dl, MVT::i32),
1287 DAG.getConstant(sz, dl, MVT::i32),
1288 DAG.getConstant(0, dl, MVT::i32), InFlag };
1289 Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
1291 InFlag = Chain.getValue(1);
1292 SDValue OutV = OutVals[OIdx];
1294 // zext/sext i1 to i16
1295 unsigned opc = ISD::ZERO_EXTEND;
1296 if (Outs[OIdx].Flags.isSExt())
1297 opc = ISD::SIGN_EXTEND;
1298 OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
1300 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1301 SDValue CopyParamOps[] = { Chain,
1302 DAG.getConstant(paramCount, dl, MVT::i32),
1303 DAG.getConstant(0, dl, MVT::i32), OutV,
1306 unsigned opcode = NVPTXISD::StoreParam;
1307 if (Outs[OIdx].Flags.isZExt())
1308 opcode = NVPTXISD::StoreParamU32;
1309 else if (Outs[OIdx].Flags.isSExt())
1310 opcode = NVPTXISD::StoreParamS32;
1311 Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps,
1312 VT, MachinePointerInfo());
1314 InFlag = Chain.getValue(1);
1319 SmallVector<EVT, 16> vtparts;
1320 SmallVector<uint64_t, 16> Offsets;
1321 const PointerType *PTy = dyn_cast<PointerType>(Args[i].Ty);
1322 assert(PTy && "Type of a byval parameter should be pointer");
1323 ComputePTXValueVTs(*this, DAG.getDataLayout(), PTy->getElementType(),
1324 vtparts, &Offsets, 0);
1326 // declare .param .align <align> .b8 .param<n>[<size>];
1327 unsigned sz = Outs[OIdx].Flags.getByValSize();
1328 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1329 unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
1330 // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
1331 // so we don't need to worry about natural alignment or not.
1332 // See TargetLowering::LowerCallTo().
1333 SDValue DeclareParamOps[] = {
1334 Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), dl, MVT::i32),
1335 DAG.getConstant(paramCount, dl, MVT::i32),
1336 DAG.getConstant(sz, dl, MVT::i32), InFlag
1338 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1340 InFlag = Chain.getValue(1);
1341 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1342 EVT elemtype = vtparts[j];
1343 int curOffset = Offsets[j];
1344 unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset);
1345 auto PtrVT = getPointerTy(DAG.getDataLayout());
1346 SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, OutVals[OIdx],
1347 DAG.getConstant(curOffset, dl, PtrVT));
1348 SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
1349 MachinePointerInfo(), false, false, false,
1351 if (elemtype.getSizeInBits() < 16) {
1352 theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
1354 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1355 SDValue CopyParamOps[] = { Chain,
1356 DAG.getConstant(paramCount, dl, MVT::i32),
1357 DAG.getConstant(curOffset, dl, MVT::i32),
1359 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
1360 CopyParamOps, elemtype,
1361 MachinePointerInfo());
1363 InFlag = Chain.getValue(1);
1368 GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
1369 unsigned retAlignment = 0;
1372 if (Ins.size() > 0) {
1373 SmallVector<EVT, 16> resvtparts;
1374 ComputeValueVTs(*this, DL, retTy, resvtparts);
1377 // .param .align 16 .b8 retval0[<size-in-bytes>], or
1378 // .param .b<size-in-bits> retval0
1379 unsigned resultsz = DL.getTypeAllocSizeInBits(retTy);
1380 // Emit ".param .b<size-in-bits> retval0" instead of byte arrays only for
1381 // these three types to match the logic in
1382 // NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
1383 // Plus, this behavior is consistent with nvcc's.
1384 if (retTy->isFloatingPointTy() || retTy->isIntegerTy() ||
1385 retTy->isPointerTy()) {
1386 // Scalar needs to be at least 32bit wide
1389 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1390 SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1391 DAG.getConstant(resultsz, dl, MVT::i32),
1392 DAG.getConstant(0, dl, MVT::i32), InFlag };
1393 Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
1395 InFlag = Chain.getValue(1);
1397 retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
1398 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1399 SDValue DeclareRetOps[] = { Chain,
1400 DAG.getConstant(retAlignment, dl, MVT::i32),
1401 DAG.getConstant(resultsz / 8, dl, MVT::i32),
1402 DAG.getConstant(0, dl, MVT::i32), InFlag };
1403 Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
1405 InFlag = Chain.getValue(1);
1410 // This is indirect function call case : PTX requires a prototype of the
1412 // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
1413 // to be emitted, and the label has to used as the last arg of call
1415 // The prototype is embedded in a string and put as the operand for a
1416 // CallPrototype SDNode which will print out to the value of the string.
1417 SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1419 getPrototype(DAG.getDataLayout(), retTy, Args, Outs, retAlignment, CS);
1420 const char *ProtoStr =
1421 nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
1422 SDValue ProtoOps[] = {
1423 Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
1425 Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
1426 InFlag = Chain.getValue(1);
1428 // Op to just print "call"
1429 SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1430 SDValue PrintCallOps[] = {
1431 Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, dl, MVT::i32), InFlag
1433 Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
1434 dl, PrintCallVTs, PrintCallOps);
1435 InFlag = Chain.getValue(1);
1437 // Ops to print out the function name
1438 SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1439 SDValue CallVoidOps[] = { Chain, Callee, InFlag };
1440 Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
1441 InFlag = Chain.getValue(1);
1443 // Ops to print out the param list
1444 SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1445 SDValue CallArgBeginOps[] = { Chain, InFlag };
1446 Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
1448 InFlag = Chain.getValue(1);
1450 for (unsigned i = 0, e = paramCount; i != e; ++i) {
1453 opcode = NVPTXISD::LastCallArg;
1455 opcode = NVPTXISD::CallArg;
1456 SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1457 SDValue CallArgOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1458 DAG.getConstant(i, dl, MVT::i32), InFlag };
1459 Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
1460 InFlag = Chain.getValue(1);
1462 SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1463 SDValue CallArgEndOps[] = { Chain,
1464 DAG.getConstant(Func ? 1 : 0, dl, MVT::i32),
1466 Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
1467 InFlag = Chain.getValue(1);
1470 SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1471 SDValue PrototypeOps[] = { Chain,
1472 DAG.getConstant(uniqueCallSite, dl, MVT::i32),
1474 Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
1475 InFlag = Chain.getValue(1);
1478 // Generate loads from param memory/moves from registers for result
1479 if (Ins.size() > 0) {
1480 if (retTy && retTy->isVectorTy()) {
1481 EVT ObjectVT = getValueType(DL, retTy);
1482 unsigned NumElts = ObjectVT.getVectorNumElements();
1483 EVT EltVT = ObjectVT.getVectorElementType();
1484 assert(STI.getTargetLowering()->getNumRegisters(F->getContext(),
1485 ObjectVT) == NumElts &&
1486 "Vector was not scalarized");
1487 unsigned sz = EltVT.getSizeInBits();
1488 bool needTruncate = sz < 8;
1491 // Just a simple load
1492 SmallVector<EVT, 4> LoadRetVTs;
1493 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1494 // If loading i1/i8 result, generate
1498 LoadRetVTs.push_back(MVT::i16);
1500 LoadRetVTs.push_back(EltVT);
1501 LoadRetVTs.push_back(MVT::Other);
1502 LoadRetVTs.push_back(MVT::Glue);
1503 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1504 DAG.getConstant(0, dl, MVT::i32), InFlag};
1505 SDValue retval = DAG.getMemIntrinsicNode(
1506 NVPTXISD::LoadParam, dl,
1507 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
1508 Chain = retval.getValue(1);
1509 InFlag = retval.getValue(2);
1510 SDValue Ret0 = retval;
1512 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0);
1513 InVals.push_back(Ret0);
1514 } else if (NumElts == 2) {
1516 SmallVector<EVT, 4> LoadRetVTs;
1517 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1518 // If loading i1/i8 result, generate
1522 LoadRetVTs.push_back(MVT::i16);
1523 LoadRetVTs.push_back(MVT::i16);
1525 LoadRetVTs.push_back(EltVT);
1526 LoadRetVTs.push_back(EltVT);
1528 LoadRetVTs.push_back(MVT::Other);
1529 LoadRetVTs.push_back(MVT::Glue);
1530 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1531 DAG.getConstant(0, dl, MVT::i32), InFlag};
1532 SDValue retval = DAG.getMemIntrinsicNode(
1533 NVPTXISD::LoadParamV2, dl,
1534 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
1535 Chain = retval.getValue(2);
1536 InFlag = retval.getValue(3);
1537 SDValue Ret0 = retval.getValue(0);
1538 SDValue Ret1 = retval.getValue(1);
1540 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0);
1541 InVals.push_back(Ret0);
1542 Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1);
1543 InVals.push_back(Ret1);
1545 InVals.push_back(Ret0);
1546 InVals.push_back(Ret1);
1549 // Split into N LoadV4
1551 unsigned VecSize = 4;
1552 unsigned Opc = NVPTXISD::LoadParamV4;
1553 if (EltVT.getSizeInBits() == 64) {
1555 Opc = NVPTXISD::LoadParamV2;
1557 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1558 for (unsigned i = 0; i < NumElts; i += VecSize) {
1559 SmallVector<EVT, 8> LoadRetVTs;
1560 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1561 // If loading i1/i8 result, generate
1565 for (unsigned j = 0; j < VecSize; ++j)
1566 LoadRetVTs.push_back(MVT::i16);
1568 for (unsigned j = 0; j < VecSize; ++j)
1569 LoadRetVTs.push_back(EltVT);
1571 LoadRetVTs.push_back(MVT::Other);
1572 LoadRetVTs.push_back(MVT::Glue);
1573 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1574 DAG.getConstant(Ofst, dl, MVT::i32), InFlag};
1575 SDValue retval = DAG.getMemIntrinsicNode(
1576 Opc, dl, DAG.getVTList(LoadRetVTs),
1577 LoadRetOps, EltVT, MachinePointerInfo());
1579 Chain = retval.getValue(2);
1580 InFlag = retval.getValue(3);
1582 Chain = retval.getValue(4);
1583 InFlag = retval.getValue(5);
1586 for (unsigned j = 0; j < VecSize; ++j) {
1587 if (i + j >= NumElts)
1589 SDValue Elt = retval.getValue(j);
1591 Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
1592 InVals.push_back(Elt);
1594 Ofst += DL.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1598 SmallVector<EVT, 16> VTs;
1599 SmallVector<uint64_t, 16> Offsets;
1600 ComputePTXValueVTs(*this, DAG.getDataLayout(), retTy, VTs, &Offsets, 0);
1601 assert(VTs.size() == Ins.size() && "Bad value decomposition");
1602 unsigned RetAlign = getArgumentAlignment(Callee, CS, retTy, 0);
1603 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
1604 unsigned sz = VTs[i].getSizeInBits();
1605 unsigned AlignI = GreatestCommonDivisor64(RetAlign, Offsets[i]);
1606 bool needTruncate = sz < 8;
1607 if (VTs[i].isInteger() && (sz < 8))
1610 SmallVector<EVT, 4> LoadRetVTs;
1611 EVT TheLoadType = VTs[i];
1612 if (retTy->isIntegerTy() && DL.getTypeAllocSizeInBits(retTy) < 32) {
1613 // This is for integer types only, and specifically not for
1615 LoadRetVTs.push_back(MVT::i32);
1616 TheLoadType = MVT::i32;
1617 } else if (sz < 16) {
1618 // If loading i1/i8 result, generate
1620 // trunc i16 to i1/i8
1621 LoadRetVTs.push_back(MVT::i16);
1623 LoadRetVTs.push_back(Ins[i].VT);
1624 LoadRetVTs.push_back(MVT::Other);
1625 LoadRetVTs.push_back(MVT::Glue);
1627 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1628 DAG.getConstant(Offsets[i], dl, MVT::i32),
1630 SDValue retval = DAG.getMemIntrinsicNode(
1631 NVPTXISD::LoadParam, dl,
1632 DAG.getVTList(LoadRetVTs), LoadRetOps,
1633 TheLoadType, MachinePointerInfo(), AlignI);
1634 Chain = retval.getValue(1);
1635 InFlag = retval.getValue(2);
1636 SDValue Ret0 = retval.getValue(0);
1638 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
1639 InVals.push_back(Ret0);
1644 Chain = DAG.getCALLSEQ_END(Chain,
1645 DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1646 DAG.getIntPtrConstant(uniqueCallSite + 1, dl,
1651 // set isTailCall to false for now, until we figure out how to express
1652 // tail call optimization in PTX
1657 // By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
1658 // (see LegalizeDAG.cpp). This is slow and uses local memory.
1659 // We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
1661 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
1662 SDNode *Node = Op.getNode();
1664 SmallVector<SDValue, 8> Ops;
1665 unsigned NumOperands = Node->getNumOperands();
1666 for (unsigned i = 0; i < NumOperands; ++i) {
1667 SDValue SubOp = Node->getOperand(i);
1668 EVT VVT = SubOp.getNode()->getValueType(0);
1669 EVT EltVT = VVT.getVectorElementType();
1670 unsigned NumSubElem = VVT.getVectorNumElements();
1671 for (unsigned j = 0; j < NumSubElem; ++j) {
1672 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1673 DAG.getIntPtrConstant(j, dl)));
1676 return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
1679 /// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
1680 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1682 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1684 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
1685 SelectionDAG &DAG) const {
1686 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1687 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
1689 EVT VT = Op.getValueType();
1690 unsigned VTBits = VT.getSizeInBits();
1692 SDValue ShOpLo = Op.getOperand(0);
1693 SDValue ShOpHi = Op.getOperand(1);
1694 SDValue ShAmt = Op.getOperand(2);
1695 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
1697 if (VTBits == 32 && STI.getSmVersion() >= 35) {
1699 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1700 // {dHi, dLo} = {aHi, aLo} >> Amt
1702 // dLo = shf.r.clamp aLo, aHi, Amt
1704 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1705 SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
1708 SDValue Ops[2] = { Lo, Hi };
1709 return DAG.getMergeValues(Ops, dl);
1713 // {dHi, dLo} = {aHi, aLo} >> Amt
1714 // - if (Amt>=size) then
1715 // dLo = aHi >> (Amt-size)
1716 // dHi = aHi >> Amt (this is either all 0 or all 1)
1718 // dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
1721 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1722 DAG.getConstant(VTBits, dl, MVT::i32),
1724 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
1725 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1726 DAG.getConstant(VTBits, dl, MVT::i32));
1727 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
1728 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1729 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
1731 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1732 DAG.getConstant(VTBits, dl, MVT::i32),
1734 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1735 SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1737 SDValue Ops[2] = { Lo, Hi };
1738 return DAG.getMergeValues(Ops, dl);
1742 /// LowerShiftLeftParts - Lower SHL_PARTS, which
1743 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1745 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1747 SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
1748 SelectionDAG &DAG) const {
1749 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1750 assert(Op.getOpcode() == ISD::SHL_PARTS);
1752 EVT VT = Op.getValueType();
1753 unsigned VTBits = VT.getSizeInBits();
1755 SDValue ShOpLo = Op.getOperand(0);
1756 SDValue ShOpHi = Op.getOperand(1);
1757 SDValue ShAmt = Op.getOperand(2);
1759 if (VTBits == 32 && STI.getSmVersion() >= 35) {
1761 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1762 // {dHi, dLo} = {aHi, aLo} << Amt
1763 // dHi = shf.l.clamp aLo, aHi, Amt
1766 SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
1768 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1770 SDValue Ops[2] = { Lo, Hi };
1771 return DAG.getMergeValues(Ops, dl);
1775 // {dHi, dLo} = {aHi, aLo} << Amt
1776 // - if (Amt>=size) then
1777 // dLo = aLo << Amt (all 0)
1778 // dLo = aLo << (Amt-size)
1781 // dHi = (aHi << Amt) | (aLo >> (size-Amt))
1783 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1784 DAG.getConstant(VTBits, dl, MVT::i32),
1786 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1787 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1788 DAG.getConstant(VTBits, dl, MVT::i32));
1789 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1790 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1791 SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1793 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1794 DAG.getConstant(VTBits, dl, MVT::i32),
1796 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1797 SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1799 SDValue Ops[2] = { Lo, Hi };
1800 return DAG.getMergeValues(Ops, dl);
1805 NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1806 switch (Op.getOpcode()) {
1807 case ISD::RETURNADDR:
1809 case ISD::FRAMEADDR:
1811 case ISD::GlobalAddress:
1812 return LowerGlobalAddress(Op, DAG);
1813 case ISD::INTRINSIC_W_CHAIN:
1815 case ISD::BUILD_VECTOR:
1816 case ISD::EXTRACT_SUBVECTOR:
1818 case ISD::CONCAT_VECTORS:
1819 return LowerCONCAT_VECTORS(Op, DAG);
1821 return LowerSTORE(Op, DAG);
1823 return LowerLOAD(Op, DAG);
1824 case ISD::SHL_PARTS:
1825 return LowerShiftLeftParts(Op, DAG);
1826 case ISD::SRA_PARTS:
1827 case ISD::SRL_PARTS:
1828 return LowerShiftRightParts(Op, DAG);
1830 return LowerSelect(Op, DAG);
1832 llvm_unreachable("Custom lowering not defined for operation");
1836 SDValue NVPTXTargetLowering::LowerSelect(SDValue Op, SelectionDAG &DAG) const {
1837 SDValue Op0 = Op->getOperand(0);
1838 SDValue Op1 = Op->getOperand(1);
1839 SDValue Op2 = Op->getOperand(2);
1840 SDLoc DL(Op.getNode());
1842 assert(Op.getValueType() == MVT::i1 && "Custom lowering enabled only for i1");
1844 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
1845 Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2);
1846 SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2);
1847 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select);
1852 SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1853 if (Op.getValueType() == MVT::i1)
1854 return LowerLOADi1(Op, DAG);
1861 // v1 = ld i8* addr (-> i16)
1862 // v = trunc i16 to i1
1863 SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
1864 SDNode *Node = Op.getNode();
1865 LoadSDNode *LD = cast<LoadSDNode>(Node);
1867 assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
1868 assert(Node->getValueType(0) == MVT::i1 &&
1869 "Custom lowering for i1 load only");
1871 DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
1872 LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(),
1873 LD->isInvariant(), LD->getAlignment());
1874 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
1875 // The legalizer (the caller) is expecting two values from the legalized
1876 // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
1877 // in LegalizeDAG.cpp which also uses MergeValues.
1878 SDValue Ops[] = { result, LD->getChain() };
1879 return DAG.getMergeValues(Ops, dl);
1882 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1883 EVT ValVT = Op.getOperand(1).getValueType();
1884 if (ValVT == MVT::i1)
1885 return LowerSTOREi1(Op, DAG);
1886 else if (ValVT.isVector())
1887 return LowerSTOREVector(Op, DAG);
1893 NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
1894 SDNode *N = Op.getNode();
1895 SDValue Val = N->getOperand(1);
1897 EVT ValVT = Val.getValueType();
1899 if (ValVT.isVector()) {
1900 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
1901 // legal. We can (and should) split that into 2 stores of <2 x double> here
1902 // but I'm leaving that as a TODO for now.
1903 if (!ValVT.isSimple())
1905 switch (ValVT.getSimpleVT().SimpleTy) {
1918 // This is a "native" vector type
1922 MemSDNode *MemSD = cast<MemSDNode>(N);
1923 const DataLayout &TD = DAG.getDataLayout();
1925 unsigned Align = MemSD->getAlignment();
1926 unsigned PrefAlign =
1927 TD.getPrefTypeAlignment(ValVT.getTypeForEVT(*DAG.getContext()));
1928 if (Align < PrefAlign) {
1929 // This store is not sufficiently aligned, so bail out and let this vector
1930 // store be scalarized. Note that we may still be able to emit smaller
1931 // vector stores. For example, if we are storing a <4 x float> with an
1932 // alignment of 8, this check will fail but the legalizer will try again
1933 // with 2 x <2 x float>, which will succeed with an alignment of 8.
1937 unsigned Opcode = 0;
1938 EVT EltVT = ValVT.getVectorElementType();
1939 unsigned NumElts = ValVT.getVectorNumElements();
1941 // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
1942 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
1943 // stored type to i16 and propagate the "real" type as the memory type.
1944 bool NeedExt = false;
1945 if (EltVT.getSizeInBits() < 16)
1952 Opcode = NVPTXISD::StoreV2;
1955 Opcode = NVPTXISD::StoreV4;
1960 SmallVector<SDValue, 8> Ops;
1962 // First is the chain
1963 Ops.push_back(N->getOperand(0));
1965 // Then the split values
1966 for (unsigned i = 0; i < NumElts; ++i) {
1967 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
1968 DAG.getIntPtrConstant(i, DL));
1970 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
1971 Ops.push_back(ExtVal);
1974 // Then any remaining arguments
1975 Ops.append(N->op_begin() + 2, N->op_end());
1977 SDValue NewSt = DAG.getMemIntrinsicNode(
1978 Opcode, DL, DAG.getVTList(MVT::Other), Ops,
1979 MemSD->getMemoryVT(), MemSD->getMemOperand());
1981 //return DCI.CombineTo(N, NewSt, true);
1990 // v1 = zxt v to i16
1992 SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
1993 SDNode *Node = Op.getNode();
1995 StoreSDNode *ST = cast<StoreSDNode>(Node);
1996 SDValue Tmp1 = ST->getChain();
1997 SDValue Tmp2 = ST->getBasePtr();
1998 SDValue Tmp3 = ST->getValue();
1999 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
2000 unsigned Alignment = ST->getAlignment();
2001 bool isVolatile = ST->isVolatile();
2002 bool isNonTemporal = ST->isNonTemporal();
2003 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
2004 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
2005 ST->getPointerInfo(), MVT::i8, isNonTemporal,
2006 isVolatile, Alignment);
2010 SDValue NVPTXTargetLowering::getExtSymb(SelectionDAG &DAG, const char *inname,
2011 int idx, EVT v) const {
2012 std::string *name = nvTM->getManagedStrPool()->getManagedString(inname);
2013 std::stringstream suffix;
2015 *name += suffix.str();
2016 return DAG.getTargetExternalSymbol(name->c_str(), v);
2020 NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
2021 std::string ParamSym;
2022 raw_string_ostream ParamStr(ParamSym);
2024 ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
2027 std::string *SavedStr =
2028 nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
2029 return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
2032 SDValue NVPTXTargetLowering::getParamHelpSymbol(SelectionDAG &DAG, int idx) {
2033 return getExtSymb(DAG, ".HLPPARAM", idx);
2036 // Check to see if the kernel argument is image*_t or sampler_t
2038 bool llvm::isImageOrSamplerVal(const Value *arg, const Module *context) {
2039 static const char *const specialTypes[] = { "struct._image2d_t",
2040 "struct._image3d_t",
2041 "struct._sampler_t" };
2043 const Type *Ty = arg->getType();
2044 const PointerType *PTy = dyn_cast<PointerType>(Ty);
2052 const StructType *STy = dyn_cast<StructType>(PTy->getElementType());
2053 const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : "";
2055 for (int i = 0, e = array_lengthof(specialTypes); i != e; ++i)
2056 if (TypeName == specialTypes[i])
2062 SDValue NVPTXTargetLowering::LowerFormalArguments(
2063 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2064 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2065 SmallVectorImpl<SDValue> &InVals) const {
2066 MachineFunction &MF = DAG.getMachineFunction();
2067 const DataLayout &DL = DAG.getDataLayout();
2068 auto PtrVT = getPointerTy(DAG.getDataLayout());
2070 const Function *F = MF.getFunction();
2071 const AttributeSet &PAL = F->getAttributes();
2072 const TargetLowering *TLI = STI.getTargetLowering();
2074 SDValue Root = DAG.getRoot();
2075 std::vector<SDValue> OutChains;
2077 bool isKernel = llvm::isKernelFunction(*F);
2078 bool isABI = (STI.getSmVersion() >= 20);
2079 assert(isABI && "Non-ABI compilation is not supported");
2083 std::vector<Type *> argTypes;
2084 std::vector<const Argument *> theArgs;
2085 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
2087 theArgs.push_back(I);
2088 argTypes.push_back(I->getType());
2090 // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
2091 // Ins.size() will be larger
2092 // * if there is an aggregate argument with multiple fields (each field
2093 // showing up separately in Ins)
2094 // * if there is a vector argument with more than typical vector-length
2095 // elements (generally if more than 4) where each vector element is
2096 // individually present in Ins.
2097 // So a different index should be used for indexing into Ins.
2098 // See similar issue in LowerCall.
2099 unsigned InsIdx = 0;
2102 for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
2103 Type *Ty = argTypes[i];
2105 // If the kernel argument is image*_t or sampler_t, convert it to
2106 // a i32 constant holding the parameter position. This can later
2107 // matched in the AsmPrinter to output the correct mangled name.
2108 if (isImageOrSamplerVal(
2110 (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
2112 assert(isKernel && "Only kernels can have image/sampler params");
2113 InVals.push_back(DAG.getConstant(i + 1, dl, MVT::i32));
2117 if (theArgs[i]->use_empty()) {
2119 if (Ty->isAggregateType()) {
2120 SmallVector<EVT, 16> vtparts;
2122 ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts);
2123 assert(vtparts.size() > 0 && "empty aggregate type not expected");
2124 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2126 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2129 if (vtparts.size() > 0)
2133 if (Ty->isVectorTy()) {
2134 EVT ObjectVT = getValueType(DL, Ty);
2135 unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
2136 for (unsigned parti = 0; parti < NumRegs; ++parti) {
2137 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2144 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2148 // In the following cases, assign a node order of "idx+1"
2149 // to newly created nodes. The SDNodes for params have to
2150 // appear in the same order as their order of appearance
2151 // in the original function. "idx+1" holds that order.
2152 if (!PAL.hasAttribute(i + 1, Attribute::ByVal)) {
2153 if (Ty->isAggregateType()) {
2154 SmallVector<EVT, 16> vtparts;
2155 SmallVector<uint64_t, 16> offsets;
2157 // NOTE: Here, we lose the ability to issue vector loads for vectors
2158 // that are a part of a struct. This should be investigated in the
2160 ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts, &offsets,
2162 assert(vtparts.size() > 0 && "empty aggregate type not expected");
2163 bool aggregateIsPacked = false;
2164 if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
2165 aggregateIsPacked = STy->isPacked();
2167 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2168 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2170 EVT partVT = vtparts[parti];
2171 Value *srcValue = Constant::getNullValue(
2172 PointerType::get(partVT.getTypeForEVT(F->getContext()),
2173 llvm::ADDRESS_SPACE_PARAM));
2175 DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
2176 DAG.getConstant(offsets[parti], dl, PtrVT));
2177 unsigned partAlign = aggregateIsPacked
2179 : DL.getABITypeAlignment(
2180 partVT.getTypeForEVT(F->getContext()));
2182 if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
2183 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
2184 ISD::SEXTLOAD : ISD::ZEXTLOAD;
2185 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
2186 MachinePointerInfo(srcValue), partVT, false,
2187 false, false, partAlign);
2189 p = DAG.getLoad(partVT, dl, Root, srcAddr,
2190 MachinePointerInfo(srcValue), false, false, false,
2194 p.getNode()->setIROrder(idx + 1);
2195 InVals.push_back(p);
2198 if (vtparts.size() > 0)
2202 if (Ty->isVectorTy()) {
2203 EVT ObjectVT = getValueType(DL, Ty);
2204 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2205 unsigned NumElts = ObjectVT.getVectorNumElements();
2206 assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
2207 "Vector was not scalarized");
2208 EVT EltVT = ObjectVT.getVectorElementType();
2213 // We only have one element, so just directly load it
2214 Value *SrcValue = Constant::getNullValue(PointerType::get(
2215 EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2216 SDValue P = DAG.getLoad(
2217 EltVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false, false,
2219 DL.getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
2221 P.getNode()->setIROrder(idx + 1);
2223 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
2224 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
2225 InVals.push_back(P);
2227 } else if (NumElts == 2) {
2229 // f32,f32 = load ...
2230 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
2231 Value *SrcValue = Constant::getNullValue(PointerType::get(
2232 VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2233 SDValue P = DAG.getLoad(
2234 VecVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false, false,
2236 DL.getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
2238 P.getNode()->setIROrder(idx + 1);
2240 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2241 DAG.getIntPtrConstant(0, dl));
2242 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2243 DAG.getIntPtrConstant(1, dl));
2245 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
2246 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
2247 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
2250 InVals.push_back(Elt0);
2251 InVals.push_back(Elt1);
2255 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
2257 // vector will be expanded to a power of 2 elements, so we know we can
2258 // always round up to the next multiple of 4 when creating the vector
2260 // e.g. 4 elem => 1 ld.v4
2261 // 6 elem => 2 ld.v4
2262 // 8 elem => 2 ld.v4
2263 // 11 elem => 3 ld.v4
2264 unsigned VecSize = 4;
2265 if (EltVT.getSizeInBits() == 64) {
2268 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
2270 for (unsigned i = 0; i < NumElts; i += VecSize) {
2271 Value *SrcValue = Constant::getNullValue(
2272 PointerType::get(VecVT.getTypeForEVT(F->getContext()),
2273 llvm::ADDRESS_SPACE_PARAM));
2274 SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
2275 DAG.getConstant(Ofst, dl, PtrVT));
2276 SDValue P = DAG.getLoad(
2277 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
2279 DL.getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
2281 P.getNode()->setIROrder(idx + 1);
2283 for (unsigned j = 0; j < VecSize; ++j) {
2284 if (i + j >= NumElts)
2286 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2287 DAG.getIntPtrConstant(j, dl));
2288 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
2289 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
2290 InVals.push_back(Elt);
2292 Ofst += DL.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2302 EVT ObjectVT = getValueType(DL, Ty);
2303 // If ABI, load from the param symbol
2304 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2305 Value *srcValue = Constant::getNullValue(PointerType::get(
2306 ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2308 if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
2309 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
2310 ISD::SEXTLOAD : ISD::ZEXTLOAD;
2312 ExtOp, dl, Ins[InsIdx].VT, Root, Arg, MachinePointerInfo(srcValue),
2313 ObjectVT, false, false, false,
2314 DL.getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
2317 Ins[InsIdx].VT, dl, Root, Arg, MachinePointerInfo(srcValue), false,
2319 DL.getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
2322 p.getNode()->setIROrder(idx + 1);
2323 InVals.push_back(p);
2327 // Param has ByVal attribute
2328 // Return MoveParam(param symbol).
2329 // Ideally, the param symbol can be returned directly,
2330 // but when SDNode builder decides to use it in a CopyToReg(),
2331 // machine instruction fails because TargetExternalSymbol
2332 // (not lowered) is target dependent, and CopyToReg assumes
2333 // the source is lowered.
2334 EVT ObjectVT = getValueType(DL, Ty);
2335 assert(ObjectVT == Ins[InsIdx].VT &&
2336 "Ins type did not match function type");
2337 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2338 SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
2340 p.getNode()->setIROrder(idx + 1);
2342 InVals.push_back(p);
2344 SDValue p2 = DAG.getNode(
2345 ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
2346 DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, dl, MVT::i32), p);
2347 InVals.push_back(p2);
2351 // Clang will check explicit VarArg and issue error if any. However, Clang
2352 // will let code with
2353 // implicit var arg like f() pass. See bug 617733.
2354 // We treat this case as if the arg list is empty.
2355 // if (F.isVarArg()) {
2356 // assert(0 && "VarArg not supported yet!");
2359 if (!OutChains.empty())
2360 DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
2367 NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2369 const SmallVectorImpl<ISD::OutputArg> &Outs,
2370 const SmallVectorImpl<SDValue> &OutVals,
2371 SDLoc dl, SelectionDAG &DAG) const {
2372 MachineFunction &MF = DAG.getMachineFunction();
2373 const Function *F = MF.getFunction();
2374 Type *RetTy = F->getReturnType();
2375 const DataLayout &TD = DAG.getDataLayout();
2377 bool isABI = (STI.getSmVersion() >= 20);
2378 assert(isABI && "Non-ABI compilation is not supported");
2382 if (VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
2383 // If we have a vector type, the OutVals array will be the scalarized
2384 // components and we have combine them into 1 or more vector stores.
2385 unsigned NumElts = VTy->getNumElements();
2386 assert(NumElts == Outs.size() && "Bad scalarization of return value");
2388 // const_cast can be removed in later LLVM versions
2389 EVT EltVT = getValueType(TD, RetTy).getVectorElementType();
2390 bool NeedExtend = false;
2391 if (EltVT.getSizeInBits() < 16)
2396 SDValue StoreVal = OutVals[0];
2397 // We only have one element, so just directly store it
2399 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
2400 SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal };
2401 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
2402 DAG.getVTList(MVT::Other), Ops,
2403 EltVT, MachinePointerInfo());
2405 } else if (NumElts == 2) {
2407 SDValue StoreVal0 = OutVals[0];
2408 SDValue StoreVal1 = OutVals[1];
2411 StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal0);
2412 StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
2415 SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal0,
2417 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
2418 DAG.getVTList(MVT::Other), Ops,
2419 EltVT, MachinePointerInfo());
2422 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
2423 // vector will be expanded to a power of 2 elements, so we know we can
2424 // always round up to the next multiple of 4 when creating the vector
2426 // e.g. 4 elem => 1 st.v4
2427 // 6 elem => 2 st.v4
2428 // 8 elem => 2 st.v4
2429 // 11 elem => 3 st.v4
2431 unsigned VecSize = 4;
2432 if (OutVals[0].getValueType().getSizeInBits() == 64)
2435 unsigned Offset = 0;
2438 EVT::getVectorVT(F->getContext(), EltVT, VecSize);
2439 unsigned PerStoreOffset =
2440 TD.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2442 for (unsigned i = 0; i < NumElts; i += VecSize) {
2445 SmallVector<SDValue, 8> Ops;
2446 Ops.push_back(Chain);
2447 Ops.push_back(DAG.getConstant(Offset, dl, MVT::i32));
2448 unsigned Opc = NVPTXISD::StoreRetvalV2;
2449 EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
2451 StoreVal = OutVals[i];
2453 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2454 Ops.push_back(StoreVal);
2456 if (i + 1 < NumElts) {
2457 StoreVal = OutVals[i + 1];
2459 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2461 StoreVal = DAG.getUNDEF(ExtendedVT);
2463 Ops.push_back(StoreVal);
2466 Opc = NVPTXISD::StoreRetvalV4;
2467 if (i + 2 < NumElts) {
2468 StoreVal = OutVals[i + 2];
2471 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2473 StoreVal = DAG.getUNDEF(ExtendedVT);
2475 Ops.push_back(StoreVal);
2477 if (i + 3 < NumElts) {
2478 StoreVal = OutVals[i + 3];
2481 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2483 StoreVal = DAG.getUNDEF(ExtendedVT);
2485 Ops.push_back(StoreVal);
2488 // Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
2490 DAG.getMemIntrinsicNode(Opc, dl, DAG.getVTList(MVT::Other), Ops,
2491 EltVT, MachinePointerInfo());
2492 Offset += PerStoreOffset;
2496 SmallVector<EVT, 16> ValVTs;
2497 SmallVector<uint64_t, 16> Offsets;
2498 ComputePTXValueVTs(*this, DAG.getDataLayout(), RetTy, ValVTs, &Offsets, 0);
2499 assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
2501 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
2502 SDValue theVal = OutVals[i];
2503 EVT TheValType = theVal.getValueType();
2504 unsigned numElems = 1;
2505 if (TheValType.isVector())
2506 numElems = TheValType.getVectorNumElements();
2507 for (unsigned j = 0, je = numElems; j != je; ++j) {
2508 SDValue TmpVal = theVal;
2509 if (TheValType.isVector())
2510 TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2511 TheValType.getVectorElementType(), TmpVal,
2512 DAG.getIntPtrConstant(j, dl));
2513 EVT TheStoreType = ValVTs[i];
2514 if (RetTy->isIntegerTy() && TD.getTypeAllocSizeInBits(RetTy) < 32) {
2515 // The following zero-extension is for integer types only, and
2516 // specifically not for aggregates.
2517 TmpVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, TmpVal);
2518 TheStoreType = MVT::i32;
2520 else if (TmpVal.getValueType().getSizeInBits() < 16)
2521 TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal);
2525 DAG.getConstant(Offsets[i], dl, MVT::i32),
2527 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
2528 DAG.getVTList(MVT::Other), Ops,
2530 MachinePointerInfo());
2535 return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
2539 void NVPTXTargetLowering::LowerAsmOperandForConstraint(
2540 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2541 SelectionDAG &DAG) const {
2542 if (Constraint.length() > 1)
2545 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2548 // NVPTX suuport vector of legal types of any length in Intrinsics because the
2549 // NVPTX specific type legalizer
2550 // will legalize them to the PTX supported length.
2551 bool NVPTXTargetLowering::isTypeSupportedInIntrinsic(MVT VT) const {
2552 if (isTypeLegal(VT))
2554 if (VT.isVector()) {
2555 MVT eVT = VT.getVectorElementType();
2556 if (isTypeLegal(eVT))
2562 static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2563 switch (Intrinsic) {
2567 case Intrinsic::nvvm_tex_1d_v4f32_s32:
2568 return NVPTXISD::Tex1DFloatS32;
2569 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2570 return NVPTXISD::Tex1DFloatFloat;
2571 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2572 return NVPTXISD::Tex1DFloatFloatLevel;
2573 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2574 return NVPTXISD::Tex1DFloatFloatGrad;
2575 case Intrinsic::nvvm_tex_1d_v4s32_s32:
2576 return NVPTXISD::Tex1DS32S32;
2577 case Intrinsic::nvvm_tex_1d_v4s32_f32:
2578 return NVPTXISD::Tex1DS32Float;
2579 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
2580 return NVPTXISD::Tex1DS32FloatLevel;
2581 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
2582 return NVPTXISD::Tex1DS32FloatGrad;
2583 case Intrinsic::nvvm_tex_1d_v4u32_s32:
2584 return NVPTXISD::Tex1DU32S32;
2585 case Intrinsic::nvvm_tex_1d_v4u32_f32:
2586 return NVPTXISD::Tex1DU32Float;
2587 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
2588 return NVPTXISD::Tex1DU32FloatLevel;
2589 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
2590 return NVPTXISD::Tex1DU32FloatGrad;
2592 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
2593 return NVPTXISD::Tex1DArrayFloatS32;
2594 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2595 return NVPTXISD::Tex1DArrayFloatFloat;
2596 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2597 return NVPTXISD::Tex1DArrayFloatFloatLevel;
2598 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2599 return NVPTXISD::Tex1DArrayFloatFloatGrad;
2600 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
2601 return NVPTXISD::Tex1DArrayS32S32;
2602 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
2603 return NVPTXISD::Tex1DArrayS32Float;
2604 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
2605 return NVPTXISD::Tex1DArrayS32FloatLevel;
2606 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
2607 return NVPTXISD::Tex1DArrayS32FloatGrad;
2608 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
2609 return NVPTXISD::Tex1DArrayU32S32;
2610 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
2611 return NVPTXISD::Tex1DArrayU32Float;
2612 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
2613 return NVPTXISD::Tex1DArrayU32FloatLevel;
2614 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
2615 return NVPTXISD::Tex1DArrayU32FloatGrad;
2617 case Intrinsic::nvvm_tex_2d_v4f32_s32:
2618 return NVPTXISD::Tex2DFloatS32;
2619 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2620 return NVPTXISD::Tex2DFloatFloat;
2621 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2622 return NVPTXISD::Tex2DFloatFloatLevel;
2623 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2624 return NVPTXISD::Tex2DFloatFloatGrad;
2625 case Intrinsic::nvvm_tex_2d_v4s32_s32:
2626 return NVPTXISD::Tex2DS32S32;
2627 case Intrinsic::nvvm_tex_2d_v4s32_f32:
2628 return NVPTXISD::Tex2DS32Float;
2629 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
2630 return NVPTXISD::Tex2DS32FloatLevel;
2631 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
2632 return NVPTXISD::Tex2DS32FloatGrad;
2633 case Intrinsic::nvvm_tex_2d_v4u32_s32:
2634 return NVPTXISD::Tex2DU32S32;
2635 case Intrinsic::nvvm_tex_2d_v4u32_f32:
2636 return NVPTXISD::Tex2DU32Float;
2637 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
2638 return NVPTXISD::Tex2DU32FloatLevel;
2639 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
2640 return NVPTXISD::Tex2DU32FloatGrad;
2642 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
2643 return NVPTXISD::Tex2DArrayFloatS32;
2644 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2645 return NVPTXISD::Tex2DArrayFloatFloat;
2646 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2647 return NVPTXISD::Tex2DArrayFloatFloatLevel;
2648 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2649 return NVPTXISD::Tex2DArrayFloatFloatGrad;
2650 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
2651 return NVPTXISD::Tex2DArrayS32S32;
2652 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
2653 return NVPTXISD::Tex2DArrayS32Float;
2654 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
2655 return NVPTXISD::Tex2DArrayS32FloatLevel;
2656 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
2657 return NVPTXISD::Tex2DArrayS32FloatGrad;
2658 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
2659 return NVPTXISD::Tex2DArrayU32S32;
2660 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
2661 return NVPTXISD::Tex2DArrayU32Float;
2662 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
2663 return NVPTXISD::Tex2DArrayU32FloatLevel;
2664 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
2665 return NVPTXISD::Tex2DArrayU32FloatGrad;
2667 case Intrinsic::nvvm_tex_3d_v4f32_s32:
2668 return NVPTXISD::Tex3DFloatS32;
2669 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2670 return NVPTXISD::Tex3DFloatFloat;
2671 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2672 return NVPTXISD::Tex3DFloatFloatLevel;
2673 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2674 return NVPTXISD::Tex3DFloatFloatGrad;
2675 case Intrinsic::nvvm_tex_3d_v4s32_s32:
2676 return NVPTXISD::Tex3DS32S32;
2677 case Intrinsic::nvvm_tex_3d_v4s32_f32:
2678 return NVPTXISD::Tex3DS32Float;
2679 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
2680 return NVPTXISD::Tex3DS32FloatLevel;
2681 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
2682 return NVPTXISD::Tex3DS32FloatGrad;
2683 case Intrinsic::nvvm_tex_3d_v4u32_s32:
2684 return NVPTXISD::Tex3DU32S32;
2685 case Intrinsic::nvvm_tex_3d_v4u32_f32:
2686 return NVPTXISD::Tex3DU32Float;
2687 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
2688 return NVPTXISD::Tex3DU32FloatLevel;
2689 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
2690 return NVPTXISD::Tex3DU32FloatGrad;
2692 case Intrinsic::nvvm_tex_cube_v4f32_f32:
2693 return NVPTXISD::TexCubeFloatFloat;
2694 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
2695 return NVPTXISD::TexCubeFloatFloatLevel;
2696 case Intrinsic::nvvm_tex_cube_v4s32_f32:
2697 return NVPTXISD::TexCubeS32Float;
2698 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
2699 return NVPTXISD::TexCubeS32FloatLevel;
2700 case Intrinsic::nvvm_tex_cube_v4u32_f32:
2701 return NVPTXISD::TexCubeU32Float;
2702 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
2703 return NVPTXISD::TexCubeU32FloatLevel;
2705 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
2706 return NVPTXISD::TexCubeArrayFloatFloat;
2707 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
2708 return NVPTXISD::TexCubeArrayFloatFloatLevel;
2709 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
2710 return NVPTXISD::TexCubeArrayS32Float;
2711 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
2712 return NVPTXISD::TexCubeArrayS32FloatLevel;
2713 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
2714 return NVPTXISD::TexCubeArrayU32Float;
2715 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
2716 return NVPTXISD::TexCubeArrayU32FloatLevel;
2718 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
2719 return NVPTXISD::Tld4R2DFloatFloat;
2720 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
2721 return NVPTXISD::Tld4G2DFloatFloat;
2722 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
2723 return NVPTXISD::Tld4B2DFloatFloat;
2724 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
2725 return NVPTXISD::Tld4A2DFloatFloat;
2726 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
2727 return NVPTXISD::Tld4R2DS64Float;
2728 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
2729 return NVPTXISD::Tld4G2DS64Float;
2730 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
2731 return NVPTXISD::Tld4B2DS64Float;
2732 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
2733 return NVPTXISD::Tld4A2DS64Float;
2734 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
2735 return NVPTXISD::Tld4R2DU64Float;
2736 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
2737 return NVPTXISD::Tld4G2DU64Float;
2738 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
2739 return NVPTXISD::Tld4B2DU64Float;
2740 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
2741 return NVPTXISD::Tld4A2DU64Float;
2743 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
2744 return NVPTXISD::TexUnified1DFloatS32;
2745 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
2746 return NVPTXISD::TexUnified1DFloatFloat;
2747 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
2748 return NVPTXISD::TexUnified1DFloatFloatLevel;
2749 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
2750 return NVPTXISD::TexUnified1DFloatFloatGrad;
2751 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
2752 return NVPTXISD::TexUnified1DS32S32;
2753 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
2754 return NVPTXISD::TexUnified1DS32Float;
2755 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
2756 return NVPTXISD::TexUnified1DS32FloatLevel;
2757 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
2758 return NVPTXISD::TexUnified1DS32FloatGrad;
2759 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
2760 return NVPTXISD::TexUnified1DU32S32;
2761 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
2762 return NVPTXISD::TexUnified1DU32Float;
2763 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
2764 return NVPTXISD::TexUnified1DU32FloatLevel;
2765 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
2766 return NVPTXISD::TexUnified1DU32FloatGrad;
2768 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
2769 return NVPTXISD::TexUnified1DArrayFloatS32;
2770 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
2771 return NVPTXISD::TexUnified1DArrayFloatFloat;
2772 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
2773 return NVPTXISD::TexUnified1DArrayFloatFloatLevel;
2774 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
2775 return NVPTXISD::TexUnified1DArrayFloatFloatGrad;
2776 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
2777 return NVPTXISD::TexUnified1DArrayS32S32;
2778 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
2779 return NVPTXISD::TexUnified1DArrayS32Float;
2780 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
2781 return NVPTXISD::TexUnified1DArrayS32FloatLevel;
2782 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
2783 return NVPTXISD::TexUnified1DArrayS32FloatGrad;
2784 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
2785 return NVPTXISD::TexUnified1DArrayU32S32;
2786 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
2787 return NVPTXISD::TexUnified1DArrayU32Float;
2788 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
2789 return NVPTXISD::TexUnified1DArrayU32FloatLevel;
2790 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
2791 return NVPTXISD::TexUnified1DArrayU32FloatGrad;
2793 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
2794 return NVPTXISD::TexUnified2DFloatS32;
2795 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
2796 return NVPTXISD::TexUnified2DFloatFloat;
2797 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
2798 return NVPTXISD::TexUnified2DFloatFloatLevel;
2799 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
2800 return NVPTXISD::TexUnified2DFloatFloatGrad;
2801 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
2802 return NVPTXISD::TexUnified2DS32S32;
2803 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
2804 return NVPTXISD::TexUnified2DS32Float;
2805 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
2806 return NVPTXISD::TexUnified2DS32FloatLevel;
2807 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
2808 return NVPTXISD::TexUnified2DS32FloatGrad;
2809 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
2810 return NVPTXISD::TexUnified2DU32S32;
2811 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
2812 return NVPTXISD::TexUnified2DU32Float;
2813 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
2814 return NVPTXISD::TexUnified2DU32FloatLevel;
2815 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
2816 return NVPTXISD::TexUnified2DU32FloatGrad;
2818 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
2819 return NVPTXISD::TexUnified2DArrayFloatS32;
2820 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
2821 return NVPTXISD::TexUnified2DArrayFloatFloat;
2822 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
2823 return NVPTXISD::TexUnified2DArrayFloatFloatLevel;
2824 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
2825 return NVPTXISD::TexUnified2DArrayFloatFloatGrad;
2826 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
2827 return NVPTXISD::TexUnified2DArrayS32S32;
2828 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
2829 return NVPTXISD::TexUnified2DArrayS32Float;
2830 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
2831 return NVPTXISD::TexUnified2DArrayS32FloatLevel;
2832 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
2833 return NVPTXISD::TexUnified2DArrayS32FloatGrad;
2834 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
2835 return NVPTXISD::TexUnified2DArrayU32S32;
2836 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
2837 return NVPTXISD::TexUnified2DArrayU32Float;
2838 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
2839 return NVPTXISD::TexUnified2DArrayU32FloatLevel;
2840 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
2841 return NVPTXISD::TexUnified2DArrayU32FloatGrad;
2843 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
2844 return NVPTXISD::TexUnified3DFloatS32;
2845 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
2846 return NVPTXISD::TexUnified3DFloatFloat;
2847 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
2848 return NVPTXISD::TexUnified3DFloatFloatLevel;
2849 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
2850 return NVPTXISD::TexUnified3DFloatFloatGrad;
2851 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
2852 return NVPTXISD::TexUnified3DS32S32;
2853 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
2854 return NVPTXISD::TexUnified3DS32Float;
2855 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
2856 return NVPTXISD::TexUnified3DS32FloatLevel;
2857 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
2858 return NVPTXISD::TexUnified3DS32FloatGrad;
2859 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
2860 return NVPTXISD::TexUnified3DU32S32;
2861 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
2862 return NVPTXISD::TexUnified3DU32Float;
2863 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
2864 return NVPTXISD::TexUnified3DU32FloatLevel;
2865 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
2866 return NVPTXISD::TexUnified3DU32FloatGrad;
2868 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
2869 return NVPTXISD::TexUnifiedCubeFloatFloat;
2870 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
2871 return NVPTXISD::TexUnifiedCubeFloatFloatLevel;
2872 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
2873 return NVPTXISD::TexUnifiedCubeS32Float;
2874 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
2875 return NVPTXISD::TexUnifiedCubeS32FloatLevel;
2876 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
2877 return NVPTXISD::TexUnifiedCubeU32Float;
2878 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
2879 return NVPTXISD::TexUnifiedCubeU32FloatLevel;
2881 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
2882 return NVPTXISD::TexUnifiedCubeArrayFloatFloat;
2883 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
2884 return NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel;
2885 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
2886 return NVPTXISD::TexUnifiedCubeArrayS32Float;
2887 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
2888 return NVPTXISD::TexUnifiedCubeArrayS32FloatLevel;
2889 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
2890 return NVPTXISD::TexUnifiedCubeArrayU32Float;
2891 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
2892 return NVPTXISD::TexUnifiedCubeArrayU32FloatLevel;
2894 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
2895 return NVPTXISD::Tld4UnifiedR2DFloatFloat;
2896 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
2897 return NVPTXISD::Tld4UnifiedG2DFloatFloat;
2898 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
2899 return NVPTXISD::Tld4UnifiedB2DFloatFloat;
2900 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
2901 return NVPTXISD::Tld4UnifiedA2DFloatFloat;
2902 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
2903 return NVPTXISD::Tld4UnifiedR2DS64Float;
2904 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
2905 return NVPTXISD::Tld4UnifiedG2DS64Float;
2906 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
2907 return NVPTXISD::Tld4UnifiedB2DS64Float;
2908 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
2909 return NVPTXISD::Tld4UnifiedA2DS64Float;
2910 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
2911 return NVPTXISD::Tld4UnifiedR2DU64Float;
2912 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
2913 return NVPTXISD::Tld4UnifiedG2DU64Float;
2914 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
2915 return NVPTXISD::Tld4UnifiedB2DU64Float;
2916 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
2917 return NVPTXISD::Tld4UnifiedA2DU64Float;
2921 static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
2922 switch (Intrinsic) {
2925 case Intrinsic::nvvm_suld_1d_i8_clamp:
2926 return NVPTXISD::Suld1DI8Clamp;
2927 case Intrinsic::nvvm_suld_1d_i16_clamp:
2928 return NVPTXISD::Suld1DI16Clamp;
2929 case Intrinsic::nvvm_suld_1d_i32_clamp:
2930 return NVPTXISD::Suld1DI32Clamp;
2931 case Intrinsic::nvvm_suld_1d_i64_clamp:
2932 return NVPTXISD::Suld1DI64Clamp;
2933 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
2934 return NVPTXISD::Suld1DV2I8Clamp;
2935 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
2936 return NVPTXISD::Suld1DV2I16Clamp;
2937 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
2938 return NVPTXISD::Suld1DV2I32Clamp;
2939 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
2940 return NVPTXISD::Suld1DV2I64Clamp;
2941 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
2942 return NVPTXISD::Suld1DV4I8Clamp;
2943 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
2944 return NVPTXISD::Suld1DV4I16Clamp;
2945 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
2946 return NVPTXISD::Suld1DV4I32Clamp;
2947 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
2948 return NVPTXISD::Suld1DArrayI8Clamp;
2949 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
2950 return NVPTXISD::Suld1DArrayI16Clamp;
2951 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
2952 return NVPTXISD::Suld1DArrayI32Clamp;
2953 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
2954 return NVPTXISD::Suld1DArrayI64Clamp;
2955 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
2956 return NVPTXISD::Suld1DArrayV2I8Clamp;
2957 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
2958 return NVPTXISD::Suld1DArrayV2I16Clamp;
2959 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
2960 return NVPTXISD::Suld1DArrayV2I32Clamp;
2961 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
2962 return NVPTXISD::Suld1DArrayV2I64Clamp;
2963 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
2964 return NVPTXISD::Suld1DArrayV4I8Clamp;
2965 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
2966 return NVPTXISD::Suld1DArrayV4I16Clamp;
2967 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
2968 return NVPTXISD::Suld1DArrayV4I32Clamp;
2969 case Intrinsic::nvvm_suld_2d_i8_clamp:
2970 return NVPTXISD::Suld2DI8Clamp;
2971 case Intrinsic::nvvm_suld_2d_i16_clamp:
2972 return NVPTXISD::Suld2DI16Clamp;
2973 case Intrinsic::nvvm_suld_2d_i32_clamp:
2974 return NVPTXISD::Suld2DI32Clamp;
2975 case Intrinsic::nvvm_suld_2d_i64_clamp:
2976 return NVPTXISD::Suld2DI64Clamp;
2977 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
2978 return NVPTXISD::Suld2DV2I8Clamp;
2979 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
2980 return NVPTXISD::Suld2DV2I16Clamp;
2981 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
2982 return NVPTXISD::Suld2DV2I32Clamp;
2983 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
2984 return NVPTXISD::Suld2DV2I64Clamp;
2985 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
2986 return NVPTXISD::Suld2DV4I8Clamp;
2987 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
2988 return NVPTXISD::Suld2DV4I16Clamp;
2989 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
2990 return NVPTXISD::Suld2DV4I32Clamp;
2991 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
2992 return NVPTXISD::Suld2DArrayI8Clamp;
2993 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
2994 return NVPTXISD::Suld2DArrayI16Clamp;
2995 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
2996 return NVPTXISD::Suld2DArrayI32Clamp;
2997 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
2998 return NVPTXISD::Suld2DArrayI64Clamp;
2999 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3000 return NVPTXISD::Suld2DArrayV2I8Clamp;
3001 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3002 return NVPTXISD::Suld2DArrayV2I16Clamp;
3003 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3004 return NVPTXISD::Suld2DArrayV2I32Clamp;
3005 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3006 return NVPTXISD::Suld2DArrayV2I64Clamp;
3007 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3008 return NVPTXISD::Suld2DArrayV4I8Clamp;
3009 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3010 return NVPTXISD::Suld2DArrayV4I16Clamp;
3011 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3012 return NVPTXISD::Suld2DArrayV4I32Clamp;
3013 case Intrinsic::nvvm_suld_3d_i8_clamp:
3014 return NVPTXISD::Suld3DI8Clamp;
3015 case Intrinsic::nvvm_suld_3d_i16_clamp:
3016 return NVPTXISD::Suld3DI16Clamp;
3017 case Intrinsic::nvvm_suld_3d_i32_clamp:
3018 return NVPTXISD::Suld3DI32Clamp;
3019 case Intrinsic::nvvm_suld_3d_i64_clamp:
3020 return NVPTXISD::Suld3DI64Clamp;
3021 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3022 return NVPTXISD::Suld3DV2I8Clamp;
3023 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3024 return NVPTXISD::Suld3DV2I16Clamp;
3025 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3026 return NVPTXISD::Suld3DV2I32Clamp;
3027 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3028 return NVPTXISD::Suld3DV2I64Clamp;
3029 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3030 return NVPTXISD::Suld3DV4I8Clamp;
3031 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3032 return NVPTXISD::Suld3DV4I16Clamp;
3033 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3034 return NVPTXISD::Suld3DV4I32Clamp;
3035 case Intrinsic::nvvm_suld_1d_i8_trap:
3036 return NVPTXISD::Suld1DI8Trap;
3037 case Intrinsic::nvvm_suld_1d_i16_trap:
3038 return NVPTXISD::Suld1DI16Trap;
3039 case Intrinsic::nvvm_suld_1d_i32_trap:
3040 return NVPTXISD::Suld1DI32Trap;
3041 case Intrinsic::nvvm_suld_1d_i64_trap:
3042 return NVPTXISD::Suld1DI64Trap;
3043 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3044 return NVPTXISD::Suld1DV2I8Trap;
3045 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3046 return NVPTXISD::Suld1DV2I16Trap;
3047 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3048 return NVPTXISD::Suld1DV2I32Trap;
3049 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3050 return NVPTXISD::Suld1DV2I64Trap;
3051 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3052 return NVPTXISD::Suld1DV4I8Trap;
3053 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3054 return NVPTXISD::Suld1DV4I16Trap;
3055 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3056 return NVPTXISD::Suld1DV4I32Trap;
3057 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3058 return NVPTXISD::Suld1DArrayI8Trap;
3059 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3060 return NVPTXISD::Suld1DArrayI16Trap;
3061 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3062 return NVPTXISD::Suld1DArrayI32Trap;
3063 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3064 return NVPTXISD::Suld1DArrayI64Trap;
3065 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3066 return NVPTXISD::Suld1DArrayV2I8Trap;
3067 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3068 return NVPTXISD::Suld1DArrayV2I16Trap;
3069 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3070 return NVPTXISD::Suld1DArrayV2I32Trap;
3071 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3072 return NVPTXISD::Suld1DArrayV2I64Trap;
3073 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3074 return NVPTXISD::Suld1DArrayV4I8Trap;
3075 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3076 return NVPTXISD::Suld1DArrayV4I16Trap;
3077 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3078 return NVPTXISD::Suld1DArrayV4I32Trap;
3079 case Intrinsic::nvvm_suld_2d_i8_trap:
3080 return NVPTXISD::Suld2DI8Trap;
3081 case Intrinsic::nvvm_suld_2d_i16_trap:
3082 return NVPTXISD::Suld2DI16Trap;
3083 case Intrinsic::nvvm_suld_2d_i32_trap:
3084 return NVPTXISD::Suld2DI32Trap;
3085 case Intrinsic::nvvm_suld_2d_i64_trap:
3086 return NVPTXISD::Suld2DI64Trap;
3087 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3088 return NVPTXISD::Suld2DV2I8Trap;
3089 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3090 return NVPTXISD::Suld2DV2I16Trap;
3091 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3092 return NVPTXISD::Suld2DV2I32Trap;
3093 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3094 return NVPTXISD::Suld2DV2I64Trap;
3095 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3096 return NVPTXISD::Suld2DV4I8Trap;
3097 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3098 return NVPTXISD::Suld2DV4I16Trap;
3099 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3100 return NVPTXISD::Suld2DV4I32Trap;
3101 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3102 return NVPTXISD::Suld2DArrayI8Trap;
3103 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3104 return NVPTXISD::Suld2DArrayI16Trap;
3105 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3106 return NVPTXISD::Suld2DArrayI32Trap;
3107 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3108 return NVPTXISD::Suld2DArrayI64Trap;
3109 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3110 return NVPTXISD::Suld2DArrayV2I8Trap;
3111 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3112 return NVPTXISD::Suld2DArrayV2I16Trap;
3113 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3114 return NVPTXISD::Suld2DArrayV2I32Trap;
3115 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3116 return NVPTXISD::Suld2DArrayV2I64Trap;
3117 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3118 return NVPTXISD::Suld2DArrayV4I8Trap;
3119 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3120 return NVPTXISD::Suld2DArrayV4I16Trap;
3121 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3122 return NVPTXISD::Suld2DArrayV4I32Trap;
3123 case Intrinsic::nvvm_suld_3d_i8_trap:
3124 return NVPTXISD::Suld3DI8Trap;
3125 case Intrinsic::nvvm_suld_3d_i16_trap:
3126 return NVPTXISD::Suld3DI16Trap;
3127 case Intrinsic::nvvm_suld_3d_i32_trap:
3128 return NVPTXISD::Suld3DI32Trap;
3129 case Intrinsic::nvvm_suld_3d_i64_trap:
3130 return NVPTXISD::Suld3DI64Trap;
3131 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3132 return NVPTXISD::Suld3DV2I8Trap;
3133 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3134 return NVPTXISD::Suld3DV2I16Trap;
3135 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3136 return NVPTXISD::Suld3DV2I32Trap;
3137 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3138 return NVPTXISD::Suld3DV2I64Trap;
3139 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3140 return NVPTXISD::Suld3DV4I8Trap;
3141 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3142 return NVPTXISD::Suld3DV4I16Trap;
3143 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3144 return NVPTXISD::Suld3DV4I32Trap;
3145 case Intrinsic::nvvm_suld_1d_i8_zero:
3146 return NVPTXISD::Suld1DI8Zero;
3147 case Intrinsic::nvvm_suld_1d_i16_zero:
3148 return NVPTXISD::Suld1DI16Zero;
3149 case Intrinsic::nvvm_suld_1d_i32_zero:
3150 return NVPTXISD::Suld1DI32Zero;
3151 case Intrinsic::nvvm_suld_1d_i64_zero:
3152 return NVPTXISD::Suld1DI64Zero;
3153 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3154 return NVPTXISD::Suld1DV2I8Zero;
3155 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3156 return NVPTXISD::Suld1DV2I16Zero;
3157 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3158 return NVPTXISD::Suld1DV2I32Zero;
3159 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3160 return NVPTXISD::Suld1DV2I64Zero;
3161 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3162 return NVPTXISD::Suld1DV4I8Zero;
3163 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3164 return NVPTXISD::Suld1DV4I16Zero;
3165 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3166 return NVPTXISD::Suld1DV4I32Zero;
3167 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3168 return NVPTXISD::Suld1DArrayI8Zero;
3169 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3170 return NVPTXISD::Suld1DArrayI16Zero;
3171 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3172 return NVPTXISD::Suld1DArrayI32Zero;
3173 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3174 return NVPTXISD::Suld1DArrayI64Zero;
3175 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3176 return NVPTXISD::Suld1DArrayV2I8Zero;
3177 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3178 return NVPTXISD::Suld1DArrayV2I16Zero;
3179 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3180 return NVPTXISD::Suld1DArrayV2I32Zero;
3181 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3182 return NVPTXISD::Suld1DArrayV2I64Zero;
3183 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3184 return NVPTXISD::Suld1DArrayV4I8Zero;
3185 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3186 return NVPTXISD::Suld1DArrayV4I16Zero;
3187 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3188 return NVPTXISD::Suld1DArrayV4I32Zero;
3189 case Intrinsic::nvvm_suld_2d_i8_zero:
3190 return NVPTXISD::Suld2DI8Zero;
3191 case Intrinsic::nvvm_suld_2d_i16_zero:
3192 return NVPTXISD::Suld2DI16Zero;
3193 case Intrinsic::nvvm_suld_2d_i32_zero:
3194 return NVPTXISD::Suld2DI32Zero;
3195 case Intrinsic::nvvm_suld_2d_i64_zero:
3196 return NVPTXISD::Suld2DI64Zero;
3197 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3198 return NVPTXISD::Suld2DV2I8Zero;
3199 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3200 return NVPTXISD::Suld2DV2I16Zero;
3201 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3202 return NVPTXISD::Suld2DV2I32Zero;
3203 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3204 return NVPTXISD::Suld2DV2I64Zero;
3205 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3206 return NVPTXISD::Suld2DV4I8Zero;
3207 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3208 return NVPTXISD::Suld2DV4I16Zero;
3209 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3210 return NVPTXISD::Suld2DV4I32Zero;
3211 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3212 return NVPTXISD::Suld2DArrayI8Zero;
3213 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3214 return NVPTXISD::Suld2DArrayI16Zero;
3215 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3216 return NVPTXISD::Suld2DArrayI32Zero;
3217 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3218 return NVPTXISD::Suld2DArrayI64Zero;
3219 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3220 return NVPTXISD::Suld2DArrayV2I8Zero;
3221 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3222 return NVPTXISD::Suld2DArrayV2I16Zero;
3223 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3224 return NVPTXISD::Suld2DArrayV2I32Zero;
3225 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3226 return NVPTXISD::Suld2DArrayV2I64Zero;
3227 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3228 return NVPTXISD::Suld2DArrayV4I8Zero;
3229 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3230 return NVPTXISD::Suld2DArrayV4I16Zero;
3231 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3232 return NVPTXISD::Suld2DArrayV4I32Zero;
3233 case Intrinsic::nvvm_suld_3d_i8_zero:
3234 return NVPTXISD::Suld3DI8Zero;
3235 case Intrinsic::nvvm_suld_3d_i16_zero:
3236 return NVPTXISD::Suld3DI16Zero;
3237 case Intrinsic::nvvm_suld_3d_i32_zero:
3238 return NVPTXISD::Suld3DI32Zero;
3239 case Intrinsic::nvvm_suld_3d_i64_zero:
3240 return NVPTXISD::Suld3DI64Zero;
3241 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3242 return NVPTXISD::Suld3DV2I8Zero;
3243 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3244 return NVPTXISD::Suld3DV2I16Zero;
3245 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3246 return NVPTXISD::Suld3DV2I32Zero;
3247 case Intrinsic::nvvm_suld_3d_v2i64_zero:
3248 return NVPTXISD::Suld3DV2I64Zero;
3249 case Intrinsic::nvvm_suld_3d_v4i8_zero:
3250 return NVPTXISD::Suld3DV4I8Zero;
3251 case Intrinsic::nvvm_suld_3d_v4i16_zero:
3252 return NVPTXISD::Suld3DV4I16Zero;
3253 case Intrinsic::nvvm_suld_3d_v4i32_zero:
3254 return NVPTXISD::Suld3DV4I32Zero;
3258 // llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
3260 // because we need the information that is only available in the "Value" type
3262 // pointer. In particular, the address space information.
3263 bool NVPTXTargetLowering::getTgtMemIntrinsic(
3264 IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
3265 switch (Intrinsic) {
3269 case Intrinsic::nvvm_atomic_load_add_f32:
3270 Info.opc = ISD::INTRINSIC_W_CHAIN;
3271 Info.memVT = MVT::f32;
3272 Info.ptrVal = I.getArgOperand(0);
3275 Info.readMem = true;
3276 Info.writeMem = true;
3280 case Intrinsic::nvvm_atomic_load_inc_32:
3281 case Intrinsic::nvvm_atomic_load_dec_32:
3282 Info.opc = ISD::INTRINSIC_W_CHAIN;
3283 Info.memVT = MVT::i32;
3284 Info.ptrVal = I.getArgOperand(0);
3287 Info.readMem = true;
3288 Info.writeMem = true;
3292 case Intrinsic::nvvm_ldu_global_i:
3293 case Intrinsic::nvvm_ldu_global_f:
3294 case Intrinsic::nvvm_ldu_global_p: {
3295 auto &DL = I.getModule()->getDataLayout();
3296 Info.opc = ISD::INTRINSIC_W_CHAIN;
3297 if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
3298 Info.memVT = getValueType(DL, I.getType());
3299 else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
3300 Info.memVT = getPointerTy(DL);
3302 Info.memVT = getValueType(DL, I.getType());
3303 Info.ptrVal = I.getArgOperand(0);
3306 Info.readMem = true;
3307 Info.writeMem = false;
3308 Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3312 case Intrinsic::nvvm_ldg_global_i:
3313 case Intrinsic::nvvm_ldg_global_f:
3314 case Intrinsic::nvvm_ldg_global_p: {
3315 auto &DL = I.getModule()->getDataLayout();
3317 Info.opc = ISD::INTRINSIC_W_CHAIN;
3318 if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
3319 Info.memVT = getValueType(DL, I.getType());
3320 else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
3321 Info.memVT = getPointerTy(DL);
3323 Info.memVT = getValueType(DL, I.getType());
3324 Info.ptrVal = I.getArgOperand(0);
3327 Info.readMem = true;
3328 Info.writeMem = false;
3329 Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3334 case Intrinsic::nvvm_tex_1d_v4f32_s32:
3335 case Intrinsic::nvvm_tex_1d_v4f32_f32:
3336 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
3337 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
3338 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
3339 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
3340 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
3341 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
3342 case Intrinsic::nvvm_tex_2d_v4f32_s32:
3343 case Intrinsic::nvvm_tex_2d_v4f32_f32:
3344 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
3345 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
3346 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
3347 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
3348 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
3349 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
3350 case Intrinsic::nvvm_tex_3d_v4f32_s32:
3351 case Intrinsic::nvvm_tex_3d_v4f32_f32:
3352 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
3353 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
3354 case Intrinsic::nvvm_tex_cube_v4f32_f32:
3355 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
3356 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
3357 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
3358 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
3359 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
3360 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
3361 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
3362 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
3363 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
3364 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
3365 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
3366 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
3367 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
3368 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
3369 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
3370 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
3371 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
3372 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
3373 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
3374 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3375 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3376 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3377 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3378 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3379 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3380 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3381 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3382 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3383 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3384 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3385 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3386 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3387 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3388 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3389 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32: {
3390 Info.opc = getOpcForTextureInstr(Intrinsic);
3391 Info.memVT = MVT::v4f32;
3392 Info.ptrVal = nullptr;
3395 Info.readMem = true;
3396 Info.writeMem = false;
3400 case Intrinsic::nvvm_tex_1d_v4s32_s32:
3401 case Intrinsic::nvvm_tex_1d_v4s32_f32:
3402 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
3403 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
3404 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
3405 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
3406 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
3407 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
3408 case Intrinsic::nvvm_tex_2d_v4s32_s32:
3409 case Intrinsic::nvvm_tex_2d_v4s32_f32:
3410 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
3411 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
3412 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
3413 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
3414 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
3415 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
3416 case Intrinsic::nvvm_tex_3d_v4s32_s32:
3417 case Intrinsic::nvvm_tex_3d_v4s32_f32:
3418 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
3419 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
3420 case Intrinsic::nvvm_tex_cube_v4s32_f32:
3421 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
3422 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
3423 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
3424 case Intrinsic::nvvm_tex_cube_v4u32_f32:
3425 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
3426 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
3427 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
3428 case Intrinsic::nvvm_tex_1d_v4u32_s32:
3429 case Intrinsic::nvvm_tex_1d_v4u32_f32:
3430 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
3431 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
3432 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
3433 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
3434 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
3435 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
3436 case Intrinsic::nvvm_tex_2d_v4u32_s32:
3437 case Intrinsic::nvvm_tex_2d_v4u32_f32:
3438 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
3439 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
3440 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
3441 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
3442 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
3443 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
3444 case Intrinsic::nvvm_tex_3d_v4u32_s32:
3445 case Intrinsic::nvvm_tex_3d_v4u32_f32:
3446 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
3447 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
3448 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
3449 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
3450 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
3451 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
3452 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
3453 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
3454 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
3455 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
3456 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
3457 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
3458 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
3459 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
3460 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
3461 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
3462 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
3463 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
3464 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
3465 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
3466 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
3467 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3468 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3469 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3470 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3471 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3472 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3473 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3474 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3475 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3476 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
3477 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
3478 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
3479 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
3480 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
3481 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
3482 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
3483 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
3484 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3485 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3486 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3487 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3488 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3489 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3490 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3491 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3492 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3493 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3494 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3495 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3496 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3497 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3498 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3499 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3500 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3501 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3502 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3503 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3504 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3505 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3506 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3507 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
3508 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3509 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3510 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3511 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32: {
3512 Info.opc = getOpcForTextureInstr(Intrinsic);
3513 Info.memVT = MVT::v4i32;
3514 Info.ptrVal = nullptr;
3517 Info.readMem = true;
3518 Info.writeMem = false;
3522 case Intrinsic::nvvm_suld_1d_i8_clamp:
3523 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3524 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3525 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3526 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3527 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3528 case Intrinsic::nvvm_suld_2d_i8_clamp:
3529 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3530 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3531 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3532 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3533 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3534 case Intrinsic::nvvm_suld_3d_i8_clamp:
3535 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3536 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3537 case Intrinsic::nvvm_suld_1d_i8_trap:
3538 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3539 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3540 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3541 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3542 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3543 case Intrinsic::nvvm_suld_2d_i8_trap:
3544 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3545 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3546 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3547 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3548 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3549 case Intrinsic::nvvm_suld_3d_i8_trap:
3550 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3551 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3552 case Intrinsic::nvvm_suld_1d_i8_zero:
3553 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3554 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3555 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3556 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3557 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3558 case Intrinsic::nvvm_suld_2d_i8_zero:
3559 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3560 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3561 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3562 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3563 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3564 case Intrinsic::nvvm_suld_3d_i8_zero:
3565 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3566 case Intrinsic::nvvm_suld_3d_v4i8_zero: {
3567 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3568 Info.memVT = MVT::i8;
3569 Info.ptrVal = nullptr;
3572 Info.readMem = true;
3573 Info.writeMem = false;
3577 case Intrinsic::nvvm_suld_1d_i16_clamp:
3578 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3579 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3580 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3581 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3582 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3583 case Intrinsic::nvvm_suld_2d_i16_clamp:
3584 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3585 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3586 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3587 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3588 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3589 case Intrinsic::nvvm_suld_3d_i16_clamp:
3590 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3591 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3592 case Intrinsic::nvvm_suld_1d_i16_trap:
3593 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3594 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3595 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3596 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3597 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3598 case Intrinsic::nvvm_suld_2d_i16_trap:
3599 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3600 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3601 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3602 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3603 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3604 case Intrinsic::nvvm_suld_3d_i16_trap:
3605 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3606 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3607 case Intrinsic::nvvm_suld_1d_i16_zero:
3608 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3609 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3610 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3611 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3612 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3613 case Intrinsic::nvvm_suld_2d_i16_zero:
3614 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3615 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3616 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3617 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3618 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3619 case Intrinsic::nvvm_suld_3d_i16_zero:
3620 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3621 case Intrinsic::nvvm_suld_3d_v4i16_zero: {
3622 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3623 Info.memVT = MVT::i16;
3624 Info.ptrVal = nullptr;
3627 Info.readMem = true;
3628 Info.writeMem = false;
3632 case Intrinsic::nvvm_suld_1d_i32_clamp:
3633 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3634 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3635 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3636 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3637 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3638 case Intrinsic::nvvm_suld_2d_i32_clamp:
3639 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3640 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3641 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3642 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3643 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3644 case Intrinsic::nvvm_suld_3d_i32_clamp:
3645 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3646 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3647 case Intrinsic::nvvm_suld_1d_i32_trap:
3648 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3649 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3650 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3651 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3652 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3653 case Intrinsic::nvvm_suld_2d_i32_trap:
3654 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3655 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3656 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3657 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3658 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3659 case Intrinsic::nvvm_suld_3d_i32_trap:
3660 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3661 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3662 case Intrinsic::nvvm_suld_1d_i32_zero:
3663 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3664 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3665 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3666 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3667 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3668 case Intrinsic::nvvm_suld_2d_i32_zero:
3669 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3670 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3671 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3672 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3673 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3674 case Intrinsic::nvvm_suld_3d_i32_zero:
3675 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3676 case Intrinsic::nvvm_suld_3d_v4i32_zero: {
3677 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3678 Info.memVT = MVT::i32;
3679 Info.ptrVal = nullptr;
3682 Info.readMem = true;
3683 Info.writeMem = false;
3687 case Intrinsic::nvvm_suld_1d_i64_clamp:
3688 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3689 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3690 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3691 case Intrinsic::nvvm_suld_2d_i64_clamp:
3692 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3693 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3694 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3695 case Intrinsic::nvvm_suld_3d_i64_clamp:
3696 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3697 case Intrinsic::nvvm_suld_1d_i64_trap:
3698 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3699 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3700 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3701 case Intrinsic::nvvm_suld_2d_i64_trap:
3702 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3703 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3704 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3705 case Intrinsic::nvvm_suld_3d_i64_trap:
3706 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3707 case Intrinsic::nvvm_suld_1d_i64_zero:
3708 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3709 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3710 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3711 case Intrinsic::nvvm_suld_2d_i64_zero:
3712 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3713 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3714 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3715 case Intrinsic::nvvm_suld_3d_i64_zero:
3716 case Intrinsic::nvvm_suld_3d_v2i64_zero: {
3717 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3718 Info.memVT = MVT::i64;
3719 Info.ptrVal = nullptr;
3722 Info.readMem = true;
3723 Info.writeMem = false;
3731 /// isLegalAddressingMode - Return true if the addressing mode represented
3732 /// by AM is legal for this target, for a load/store of the specified type.
3733 /// Used to guide target specific optimizations, like loop strength reduction
3734 /// (LoopStrengthReduce.cpp) and memory optimization for address mode
3735 /// (CodeGenPrepare.cpp)
3736 bool NVPTXTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3737 const AddrMode &AM, Type *Ty,
3738 unsigned AS) const {
3740 // AddrMode - This represents an addressing mode of:
3741 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
3743 // The legal address modes are
3750 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale)
3756 case 0: // "r", "r+i" or "i" is allowed
3759 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
3761 // Otherwise we have r+i.
3764 // No scale > 1 is allowed
3770 //===----------------------------------------------------------------------===//
3771 // NVPTX Inline Assembly Support
3772 //===----------------------------------------------------------------------===//
3774 /// getConstraintType - Given a constraint letter, return the type of
3775 /// constraint it is for this target.
3776 NVPTXTargetLowering::ConstraintType
3777 NVPTXTargetLowering::getConstraintType(StringRef Constraint) const {
3778 if (Constraint.size() == 1) {
3779 switch (Constraint[0]) {
3791 return C_RegisterClass;
3794 return TargetLowering::getConstraintType(Constraint);
3797 std::pair<unsigned, const TargetRegisterClass *>
3798 NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3799 StringRef Constraint,
3801 if (Constraint.size() == 1) {
3802 switch (Constraint[0]) {
3804 return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
3806 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3808 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3810 return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
3813 return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
3815 return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
3817 return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
3820 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3823 /// getFunctionAlignment - Return the Log2 alignment of this function.
3824 unsigned NVPTXTargetLowering::getFunctionAlignment(const Function *) const {
3828 //===----------------------------------------------------------------------===//
3829 // NVPTX DAG Combining
3830 //===----------------------------------------------------------------------===//
3832 bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
3833 CodeGenOpt::Level OptLevel) const {
3834 const Function *F = MF.getFunction();
3835 const TargetOptions &TO = MF.getTarget().Options;
3837 // Always honor command-line argument
3838 if (FMAContractLevelOpt.getNumOccurrences() > 0) {
3839 return FMAContractLevelOpt > 0;
3840 } else if (OptLevel == 0) {
3841 // Do not contract if we're not optimizing the code
3843 } else if (TO.AllowFPOpFusion == FPOpFusion::Fast || TO.UnsafeFPMath) {
3844 // Honor TargetOptions flags that explicitly say fusion is okay
3846 } else if (F->hasFnAttribute("unsafe-fp-math")) {
3847 // Check for unsafe-fp-math=true coming from Clang
3848 Attribute Attr = F->getFnAttribute("unsafe-fp-math");
3849 StringRef Val = Attr.getValueAsString();
3854 // We did not have a clear indication that fusion is allowed, so assume not
3858 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
3859 /// operands N0 and N1. This is a helper for PerformADDCombine that is
3860 /// called with the default operands, and if that fails, with commuted
3862 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
3863 TargetLowering::DAGCombinerInfo &DCI,
3864 const NVPTXSubtarget &Subtarget,
3865 CodeGenOpt::Level OptLevel) {
3866 SelectionDAG &DAG = DCI.DAG;
3867 // Skip non-integer, non-scalar case
3868 EVT VT=N0.getValueType();
3872 // fold (add (mul a, b), c) -> (mad a, b, c)
3874 if (N0.getOpcode() == ISD::MUL) {
3875 assert (VT.isInteger());
3877 // Since integer multiply-add costs the same as integer multiply
3878 // but is more costly than integer add, do the fusion only when
3879 // the mul is only used in the add.
3880 if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
3881 !N0.getNode()->hasOneUse())
3885 return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
3886 N0.getOperand(0), N0.getOperand(1), N1);
3888 else if (N0.getOpcode() == ISD::FMUL) {
3889 if (VT == MVT::f32 || VT == MVT::f64) {
3890 const auto *TLI = static_cast<const NVPTXTargetLowering *>(
3891 &DAG.getTargetLoweringInfo());
3892 if (!TLI->allowFMA(DAG.getMachineFunction(), OptLevel))
3895 // For floating point:
3896 // Do the fusion only when the mul has less than 5 uses and all
3898 // The heuristic is that if a use is not an add, then that use
3899 // cannot be fused into fma, therefore mul is still needed anyway.
3900 // If there are more than 4 uses, even if they are all add, fusing
3901 // them will increase register pressue.
3904 int nonAddCount = 0;
3905 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3906 UE = N0.getNode()->use_end();
3910 if (User->getOpcode() != ISD::FADD)
3916 int orderNo = N->getIROrder();
3917 int orderNo2 = N0.getNode()->getIROrder();
3918 // simple heuristics here for considering potential register
3919 // pressure, the logics here is that the differnce are used
3920 // to measure the distance between def and use, the longer distance
3921 // more likely cause register pressure.
3922 if (orderNo - orderNo2 < 500)
3925 // Now, check if at least one of the FMUL's operands is live beyond the node N,
3926 // which guarantees that the FMA will not increase register pressure at node N.
3927 bool opIsLive = false;
3928 const SDNode *left = N0.getOperand(0).getNode();
3929 const SDNode *right = N0.getOperand(1).getNode();
3931 if (isa<ConstantSDNode>(left) || isa<ConstantSDNode>(right))
3935 for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
3937 int orderNo3 = User->getIROrder();
3938 if (orderNo3 > orderNo) {
3945 for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
3947 int orderNo3 = User->getIROrder();
3948 if (orderNo3 > orderNo) {
3958 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
3959 N0.getOperand(0), N0.getOperand(1), N1);
3966 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3968 static SDValue PerformADDCombine(SDNode *N,
3969 TargetLowering::DAGCombinerInfo &DCI,
3970 const NVPTXSubtarget &Subtarget,
3971 CodeGenOpt::Level OptLevel) {
3972 SDValue N0 = N->getOperand(0);
3973 SDValue N1 = N->getOperand(1);
3975 // First try with the default operand order.
3976 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget,
3978 if (Result.getNode())
3981 // If that didn't work, try again with the operands commuted.
3982 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
3985 static SDValue PerformANDCombine(SDNode *N,
3986 TargetLowering::DAGCombinerInfo &DCI) {
3987 // The type legalizer turns a vector load of i8 values into a zextload to i16
3988 // registers, optionally ANY_EXTENDs it (if target type is integer),
3989 // and ANDs off the high 8 bits. Since we turn this load into a
3990 // target-specific DAG node, the DAG combiner fails to eliminate these AND
3991 // nodes. Do that here.
3992 SDValue Val = N->getOperand(0);
3993 SDValue Mask = N->getOperand(1);
3995 if (isa<ConstantSDNode>(Val)) {
3996 std::swap(Val, Mask);
4000 // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
4001 if (Val.getOpcode() == ISD::ANY_EXTEND) {
4003 Val = Val->getOperand(0);
4006 if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
4007 Val = Val->getOperand(0);
4010 if (Val->getOpcode() == NVPTXISD::LoadV2 ||
4011 Val->getOpcode() == NVPTXISD::LoadV4) {
4012 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
4014 // Not an AND with a constant
4018 uint64_t MaskVal = MaskCnst->getZExtValue();
4019 if (MaskVal != 0xff) {
4020 // Not an AND that chops off top 8 bits
4024 MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
4026 // Not a MemSDNode?!?
4030 EVT MemVT = Mem->getMemoryVT();
4031 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
4032 // We only handle the i8 case
4037 cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
4039 if (ExtType == ISD::SEXTLOAD) {
4040 // If for some reason the load is a sextload, the and is needed to zero
4041 // out the high 8 bits
4046 if (AExt.getNode() != 0) {
4047 // Re-insert the ext as a zext.
4048 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
4049 AExt.getValueType(), Val);
4053 // If we get here, the AND is unnecessary. Just replace it with the load
4054 DCI.CombineTo(N, Val, AddTo);
4060 enum OperandSignedness {
4066 /// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
4067 /// that can be demoted to \p OptSize bits without loss of information. The
4068 /// signedness of the operand, if determinable, is placed in \p S.
4069 static bool IsMulWideOperandDemotable(SDValue Op,
4071 OperandSignedness &S) {
4074 if (Op.getOpcode() == ISD::SIGN_EXTEND ||
4075 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
4076 EVT OrigVT = Op.getOperand(0).getValueType();
4077 if (OrigVT.getSizeInBits() <= OptSize) {
4081 } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
4082 EVT OrigVT = Op.getOperand(0).getValueType();
4083 if (OrigVT.getSizeInBits() <= OptSize) {
4092 /// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
4093 /// be demoted to \p OptSize bits without loss of information. If the operands
4094 /// contain a constant, it should appear as the RHS operand. The signedness of
4095 /// the operands is placed in \p IsSigned.
4096 static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
4100 OperandSignedness LHSSign;
4102 // The LHS operand must be a demotable op
4103 if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
4106 // We should have been able to determine the signedness from the LHS
4107 if (LHSSign == Unknown)
4110 IsSigned = (LHSSign == Signed);
4112 // The RHS can be a demotable op or a constant
4113 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
4114 APInt Val = CI->getAPIntValue();
4115 if (LHSSign == Unsigned) {
4116 if (Val.isIntN(OptSize)) {
4121 if (Val.isSignedIntN(OptSize)) {
4127 OperandSignedness RHSSign;
4128 if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
4131 if (LHSSign != RHSSign)
4138 /// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
4139 /// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
4140 /// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
4142 static SDValue TryMULWIDECombine(SDNode *N,
4143 TargetLowering::DAGCombinerInfo &DCI) {
4144 EVT MulType = N->getValueType(0);
4145 if (MulType != MVT::i32 && MulType != MVT::i64) {
4150 unsigned OptSize = MulType.getSizeInBits() >> 1;
4151 SDValue LHS = N->getOperand(0);
4152 SDValue RHS = N->getOperand(1);
4154 // Canonicalize the multiply so the constant (if any) is on the right
4155 if (N->getOpcode() == ISD::MUL) {
4156 if (isa<ConstantSDNode>(LHS)) {
4157 std::swap(LHS, RHS);
4161 // If we have a SHL, determine the actual multiply amount
4162 if (N->getOpcode() == ISD::SHL) {
4163 ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
4168 APInt ShiftAmt = ShlRHS->getAPIntValue();
4169 unsigned BitWidth = MulType.getSizeInBits();
4170 if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
4171 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
4172 RHS = DCI.DAG.getConstant(MulVal, DL, MulType);
4179 // Verify that our operands are demotable
4180 if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
4185 if (MulType == MVT::i32) {
4186 DemotedVT = MVT::i16;
4188 DemotedVT = MVT::i32;
4191 // Truncate the operands to the correct size. Note that these are just for
4192 // type consistency and will (likely) be eliminated in later phases.
4194 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS);
4196 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS);
4200 Opc = NVPTXISD::MUL_WIDE_SIGNED;
4202 Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
4205 return DCI.DAG.getNode(Opc, DL, MulType, TruncLHS, TruncRHS);
4208 /// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
4209 static SDValue PerformMULCombine(SDNode *N,
4210 TargetLowering::DAGCombinerInfo &DCI,
4211 CodeGenOpt::Level OptLevel) {
4213 // Try mul.wide combining at OptLevel > 0
4214 SDValue Ret = TryMULWIDECombine(N, DCI);
4222 /// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
4223 static SDValue PerformSHLCombine(SDNode *N,
4224 TargetLowering::DAGCombinerInfo &DCI,
4225 CodeGenOpt::Level OptLevel) {
4227 // Try mul.wide combining at OptLevel > 0
4228 SDValue Ret = TryMULWIDECombine(N, DCI);
4236 SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
4237 DAGCombinerInfo &DCI) const {
4238 CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
4239 switch (N->getOpcode()) {
4243 return PerformADDCombine(N, DCI, STI, OptLevel);
4245 return PerformMULCombine(N, DCI, OptLevel);
4247 return PerformSHLCombine(N, DCI, OptLevel);
4249 return PerformANDCombine(N, DCI);
4254 /// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
4255 static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
4256 SmallVectorImpl<SDValue> &Results) {
4257 EVT ResVT = N->getValueType(0);
4260 assert(ResVT.isVector() && "Vector load must have vector type");
4262 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
4263 // legal. We can (and should) split that into 2 loads of <2 x double> here
4264 // but I'm leaving that as a TODO for now.
4265 assert(ResVT.isSimple() && "Can only handle simple types");
4266 switch (ResVT.getSimpleVT().SimpleTy) {
4279 // This is a "native" vector type
4283 LoadSDNode *LD = cast<LoadSDNode>(N);
4285 unsigned Align = LD->getAlignment();
4286 auto &TD = DAG.getDataLayout();
4287 unsigned PrefAlign =
4288 TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext()));
4289 if (Align < PrefAlign) {
4290 // This load is not sufficiently aligned, so bail out and let this vector
4291 // load be scalarized. Note that we may still be able to emit smaller
4292 // vector loads. For example, if we are loading a <4 x float> with an
4293 // alignment of 8, this check will fail but the legalizer will try again
4294 // with 2 x <2 x float>, which will succeed with an alignment of 8.
4298 EVT EltVT = ResVT.getVectorElementType();
4299 unsigned NumElts = ResVT.getVectorNumElements();
4301 // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
4302 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4303 // loaded type to i16 and propagate the "real" type as the memory type.
4304 bool NeedTrunc = false;
4305 if (EltVT.getSizeInBits() < 16) {
4310 unsigned Opcode = 0;
4317 Opcode = NVPTXISD::LoadV2;
4318 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4321 Opcode = NVPTXISD::LoadV4;
4322 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4323 LdResVTs = DAG.getVTList(ListVTs);
4328 // Copy regular operands
4329 SmallVector<SDValue, 8> OtherOps(N->op_begin(), N->op_end());
4331 // The select routine does not have access to the LoadSDNode instance, so
4332 // pass along the extension information
4333 OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType(), DL));
4335 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4337 LD->getMemOperand());
4339 SmallVector<SDValue, 4> ScalarRes;
4341 for (unsigned i = 0; i < NumElts; ++i) {
4342 SDValue Res = NewLD.getValue(i);
4344 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4345 ScalarRes.push_back(Res);
4348 SDValue LoadChain = NewLD.getValue(NumElts);
4350 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
4352 Results.push_back(BuildVec);
4353 Results.push_back(LoadChain);
4356 static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
4357 SmallVectorImpl<SDValue> &Results) {
4358 SDValue Chain = N->getOperand(0);
4359 SDValue Intrin = N->getOperand(1);
4362 // Get the intrinsic ID
4363 unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
4367 case Intrinsic::nvvm_ldg_global_i:
4368 case Intrinsic::nvvm_ldg_global_f:
4369 case Intrinsic::nvvm_ldg_global_p:
4370 case Intrinsic::nvvm_ldu_global_i:
4371 case Intrinsic::nvvm_ldu_global_f:
4372 case Intrinsic::nvvm_ldu_global_p: {
4373 EVT ResVT = N->getValueType(0);
4375 if (ResVT.isVector()) {
4378 unsigned NumElts = ResVT.getVectorNumElements();
4379 EVT EltVT = ResVT.getVectorElementType();
4381 // Since LDU/LDG are target nodes, we cannot rely on DAG type
4383 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4384 // loaded type to i16 and propagate the "real" type as the memory type.
4385 bool NeedTrunc = false;
4386 if (EltVT.getSizeInBits() < 16) {
4391 unsigned Opcode = 0;
4401 case Intrinsic::nvvm_ldg_global_i:
4402 case Intrinsic::nvvm_ldg_global_f:
4403 case Intrinsic::nvvm_ldg_global_p:
4404 Opcode = NVPTXISD::LDGV2;
4406 case Intrinsic::nvvm_ldu_global_i:
4407 case Intrinsic::nvvm_ldu_global_f:
4408 case Intrinsic::nvvm_ldu_global_p:
4409 Opcode = NVPTXISD::LDUV2;
4412 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4418 case Intrinsic::nvvm_ldg_global_i:
4419 case Intrinsic::nvvm_ldg_global_f:
4420 case Intrinsic::nvvm_ldg_global_p:
4421 Opcode = NVPTXISD::LDGV4;
4423 case Intrinsic::nvvm_ldu_global_i:
4424 case Intrinsic::nvvm_ldu_global_f:
4425 case Intrinsic::nvvm_ldu_global_p:
4426 Opcode = NVPTXISD::LDUV4;
4429 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4430 LdResVTs = DAG.getVTList(ListVTs);
4435 SmallVector<SDValue, 8> OtherOps;
4437 // Copy regular operands
4439 OtherOps.push_back(Chain); // Chain
4440 // Skip operand 1 (intrinsic ID)
4442 OtherOps.append(N->op_begin() + 2, N->op_end());
4444 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4446 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4447 MemSD->getMemoryVT(),
4448 MemSD->getMemOperand());
4450 SmallVector<SDValue, 4> ScalarRes;
4452 for (unsigned i = 0; i < NumElts; ++i) {
4453 SDValue Res = NewLD.getValue(i);
4456 DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4457 ScalarRes.push_back(Res);
4460 SDValue LoadChain = NewLD.getValue(NumElts);
4463 DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
4465 Results.push_back(BuildVec);
4466 Results.push_back(LoadChain);
4469 assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
4470 "Custom handling of non-i8 ldu/ldg?");
4472 // Just copy all operands as-is
4473 SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
4475 // Force output to i16
4476 SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
4478 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4480 // We make sure the memory type is i8, which will be used during isel
4481 // to select the proper instruction.
4483 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
4484 MVT::i8, MemSD->getMemOperand());
4486 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
4487 NewLD.getValue(0)));
4488 Results.push_back(NewLD.getValue(1));
4494 void NVPTXTargetLowering::ReplaceNodeResults(
4495 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
4496 switch (N->getOpcode()) {
4498 report_fatal_error("Unhandled custom legalization");
4500 ReplaceLoadVector(N, DAG, Results);
4502 case ISD::INTRINSIC_W_CHAIN:
4503 ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
4508 // Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
4509 void NVPTXSection::anchor() {}
4511 NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
4515 delete ReadOnlySection;
4517 delete StaticCtorSection;
4518 delete StaticDtorSection;
4520 delete EHFrameSection;
4521 delete DwarfAbbrevSection;
4522 delete DwarfInfoSection;
4523 delete DwarfLineSection;
4524 delete DwarfFrameSection;
4525 delete DwarfPubTypesSection;
4526 delete DwarfDebugInlineSection;
4527 delete DwarfStrSection;
4528 delete DwarfLocSection;
4529 delete DwarfARangesSection;
4530 delete DwarfRangesSection;
4534 NVPTXTargetObjectFile::SelectSectionForGlobal(const GlobalValue *GV,
4535 SectionKind Kind, Mangler &Mang,
4536 const TargetMachine &TM) const {
4537 return getDataSection();