2 // The LLVM Compiler Infrastructure
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXISelLowering.h"
16 #include "NVPTXTargetMachine.h"
17 #include "NVPTXTargetObjectFile.h"
18 #include "NVPTXUtilities.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
25 #include "llvm/IR/CallSite.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/IntrinsicInst.h"
30 #include "llvm/IR/Intrinsics.h"
31 #include "llvm/IR/Module.h"
32 #include "llvm/MC/MCSectionELF.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
41 #define DEBUG_TYPE "nvptx-lower"
45 static unsigned int uniqueCallSite = 0;
47 static cl::opt<bool> sched4reg(
49 cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
51 static cl::opt<unsigned>
52 FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
53 cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
54 " 1: do it 2: do it aggressively"),
57 static bool IsPTXVectorType(MVT VT) {
58 switch (VT.SimpleTy) {
77 /// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
78 /// EVTs that compose it. Unlike ComputeValueVTs, this will break apart vectors
79 /// into their primitive components.
80 /// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
81 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
82 /// LowerCall, and LowerReturn.
83 static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL,
84 Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
85 SmallVectorImpl<uint64_t> *Offsets = nullptr,
86 uint64_t StartingOffset = 0) {
87 SmallVector<EVT, 16> TempVTs;
88 SmallVector<uint64_t, 16> TempOffsets;
90 ComputeValueVTs(TLI, DL, Ty, TempVTs, &TempOffsets, StartingOffset);
91 for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
93 uint64_t Off = TempOffsets[i];
95 for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
96 ValueVTs.push_back(VT.getVectorElementType());
98 Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
101 ValueVTs.push_back(VT);
103 Offsets->push_back(Off);
108 // NVPTXTargetLowering Constructor.
109 NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
110 const NVPTXSubtarget &STI)
111 : TargetLowering(TM), nvTM(&TM), STI(STI) {
113 // always lower memset, memcpy, and memmove intrinsics to load/store
114 // instructions, rather
115 // then generating calls to memset, mempcy or memmove.
116 MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
117 MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
118 MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
120 setBooleanContents(ZeroOrNegativeOneBooleanContent);
121 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
123 // Jump is Expensive. Don't create extra control flow for 'and', 'or'
124 // condition branches.
125 setJumpIsExpensive(true);
127 // Wide divides are _very_ slow. Try to reduce the width of the divide if
129 addBypassSlowDiv(64, 32);
131 // By default, use the Source scheduling
133 setSchedulingPreference(Sched::RegPressure);
135 setSchedulingPreference(Sched::Source);
137 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
138 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
139 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
140 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
141 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
142 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
144 // Operations not directly supported by NVPTX.
145 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
146 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
147 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
148 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
149 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
150 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
151 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
152 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
153 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
154 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
155 setOperationAction(ISD::BR_CC, MVT::i8, Expand);
156 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
157 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
158 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
159 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
160 // For others we will expand to a SHL/SRA pair.
161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
162 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
163 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
164 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
167 setOperationAction(ISD::SHL_PARTS, MVT::i32 , Custom);
168 setOperationAction(ISD::SRA_PARTS, MVT::i32 , Custom);
169 setOperationAction(ISD::SRL_PARTS, MVT::i32 , Custom);
170 setOperationAction(ISD::SHL_PARTS, MVT::i64 , Custom);
171 setOperationAction(ISD::SRA_PARTS, MVT::i64 , Custom);
172 setOperationAction(ISD::SRL_PARTS, MVT::i64 , Custom);
174 if (STI.hasROT64()) {
175 setOperationAction(ISD::ROTL, MVT::i64, Legal);
176 setOperationAction(ISD::ROTR, MVT::i64, Legal);
178 setOperationAction(ISD::ROTL, MVT::i64, Expand);
179 setOperationAction(ISD::ROTR, MVT::i64, Expand);
181 if (STI.hasROT32()) {
182 setOperationAction(ISD::ROTL, MVT::i32, Legal);
183 setOperationAction(ISD::ROTR, MVT::i32, Legal);
185 setOperationAction(ISD::ROTL, MVT::i32, Expand);
186 setOperationAction(ISD::ROTR, MVT::i32, Expand);
189 setOperationAction(ISD::ROTL, MVT::i16, Expand);
190 setOperationAction(ISD::ROTR, MVT::i16, Expand);
191 setOperationAction(ISD::ROTL, MVT::i8, Expand);
192 setOperationAction(ISD::ROTR, MVT::i8, Expand);
193 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
194 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
195 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
197 // Indirect branch is not supported.
198 // This also disables Jump Table creation.
199 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
200 setOperationAction(ISD::BRIND, MVT::Other, Expand);
202 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
203 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
205 // We want to legalize constant related memmove and memcopy
207 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
209 // Turn FP extload into load/fextend
210 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
211 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
212 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
213 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
214 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
215 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
216 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
217 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
218 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
219 // Turn FP truncstore into trunc + store.
220 // FIXME: vector types should also be expanded
221 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
222 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
223 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
225 // PTX does not support load / store predicate registers
226 setOperationAction(ISD::LOAD, MVT::i1, Custom);
227 setOperationAction(ISD::STORE, MVT::i1, Custom);
229 for (MVT VT : MVT::integer_valuetypes()) {
230 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
231 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
232 setTruncStoreAction(VT, MVT::i1, Expand);
235 // This is legal in NVPTX
236 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
237 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
239 // TRAP can be lowered to PTX trap
240 setOperationAction(ISD::TRAP, MVT::Other, Legal);
242 setOperationAction(ISD::ADDC, MVT::i64, Expand);
243 setOperationAction(ISD::ADDE, MVT::i64, Expand);
245 // Register custom handling for vector loads/stores
246 for (MVT VT : MVT::vector_valuetypes()) {
247 if (IsPTXVectorType(VT)) {
248 setOperationAction(ISD::LOAD, VT, Custom);
249 setOperationAction(ISD::STORE, VT, Custom);
250 setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
254 // Custom handling for i8 intrinsics
255 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
257 setOperationAction(ISD::CTLZ, MVT::i16, Legal);
258 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
259 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
260 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal);
261 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
262 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
263 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
264 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
265 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
266 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
267 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
268 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
269 setOperationAction(ISD::CTPOP, MVT::i16, Legal);
270 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
271 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
273 // PTX does not directly support SELP of i1, so promote to i32 first
274 setOperationAction(ISD::SELECT, MVT::i1, Custom);
276 // We have some custom DAG combine patterns for these nodes
277 setTargetDAGCombine(ISD::ADD);
278 setTargetDAGCombine(ISD::AND);
279 setTargetDAGCombine(ISD::FADD);
280 setTargetDAGCombine(ISD::MUL);
281 setTargetDAGCombine(ISD::SHL);
283 // Now deduce the information based on the above mentioned
285 computeRegisterProperties(STI.getRegisterInfo());
288 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
289 switch ((NVPTXISD::NodeType)Opcode) {
290 case NVPTXISD::FIRST_NUMBER:
293 return "NVPTXISD::CALL";
294 case NVPTXISD::RET_FLAG:
295 return "NVPTXISD::RET_FLAG";
296 case NVPTXISD::LOAD_PARAM:
297 return "NVPTXISD::LOAD_PARAM";
298 case NVPTXISD::Wrapper:
299 return "NVPTXISD::Wrapper";
300 case NVPTXISD::DeclareParam:
301 return "NVPTXISD::DeclareParam";
302 case NVPTXISD::DeclareScalarParam:
303 return "NVPTXISD::DeclareScalarParam";
304 case NVPTXISD::DeclareRet:
305 return "NVPTXISD::DeclareRet";
306 case NVPTXISD::DeclareScalarRet:
307 return "NVPTXISD::DeclareScalarRet";
308 case NVPTXISD::DeclareRetParam:
309 return "NVPTXISD::DeclareRetParam";
310 case NVPTXISD::PrintCall:
311 return "NVPTXISD::PrintCall";
312 case NVPTXISD::PrintCallUni:
313 return "NVPTXISD::PrintCallUni";
314 case NVPTXISD::LoadParam:
315 return "NVPTXISD::LoadParam";
316 case NVPTXISD::LoadParamV2:
317 return "NVPTXISD::LoadParamV2";
318 case NVPTXISD::LoadParamV4:
319 return "NVPTXISD::LoadParamV4";
320 case NVPTXISD::StoreParam:
321 return "NVPTXISD::StoreParam";
322 case NVPTXISD::StoreParamV2:
323 return "NVPTXISD::StoreParamV2";
324 case NVPTXISD::StoreParamV4:
325 return "NVPTXISD::StoreParamV4";
326 case NVPTXISD::StoreParamS32:
327 return "NVPTXISD::StoreParamS32";
328 case NVPTXISD::StoreParamU32:
329 return "NVPTXISD::StoreParamU32";
330 case NVPTXISD::CallArgBegin:
331 return "NVPTXISD::CallArgBegin";
332 case NVPTXISD::CallArg:
333 return "NVPTXISD::CallArg";
334 case NVPTXISD::LastCallArg:
335 return "NVPTXISD::LastCallArg";
336 case NVPTXISD::CallArgEnd:
337 return "NVPTXISD::CallArgEnd";
338 case NVPTXISD::CallVoid:
339 return "NVPTXISD::CallVoid";
340 case NVPTXISD::CallVal:
341 return "NVPTXISD::CallVal";
342 case NVPTXISD::CallSymbol:
343 return "NVPTXISD::CallSymbol";
344 case NVPTXISD::Prototype:
345 return "NVPTXISD::Prototype";
346 case NVPTXISD::MoveParam:
347 return "NVPTXISD::MoveParam";
348 case NVPTXISD::StoreRetval:
349 return "NVPTXISD::StoreRetval";
350 case NVPTXISD::StoreRetvalV2:
351 return "NVPTXISD::StoreRetvalV2";
352 case NVPTXISD::StoreRetvalV4:
353 return "NVPTXISD::StoreRetvalV4";
354 case NVPTXISD::PseudoUseParam:
355 return "NVPTXISD::PseudoUseParam";
356 case NVPTXISD::RETURN:
357 return "NVPTXISD::RETURN";
358 case NVPTXISD::CallSeqBegin:
359 return "NVPTXISD::CallSeqBegin";
360 case NVPTXISD::CallSeqEnd:
361 return "NVPTXISD::CallSeqEnd";
362 case NVPTXISD::CallPrototype:
363 return "NVPTXISD::CallPrototype";
364 case NVPTXISD::LoadV2:
365 return "NVPTXISD::LoadV2";
366 case NVPTXISD::LoadV4:
367 return "NVPTXISD::LoadV4";
368 case NVPTXISD::LDGV2:
369 return "NVPTXISD::LDGV2";
370 case NVPTXISD::LDGV4:
371 return "NVPTXISD::LDGV4";
372 case NVPTXISD::LDUV2:
373 return "NVPTXISD::LDUV2";
374 case NVPTXISD::LDUV4:
375 return "NVPTXISD::LDUV4";
376 case NVPTXISD::StoreV2:
377 return "NVPTXISD::StoreV2";
378 case NVPTXISD::StoreV4:
379 return "NVPTXISD::StoreV4";
380 case NVPTXISD::FUN_SHFL_CLAMP:
381 return "NVPTXISD::FUN_SHFL_CLAMP";
382 case NVPTXISD::FUN_SHFR_CLAMP:
383 return "NVPTXISD::FUN_SHFR_CLAMP";
385 return "NVPTXISD::IMAD";
386 case NVPTXISD::Dummy:
387 return "NVPTXISD::Dummy";
388 case NVPTXISD::MUL_WIDE_SIGNED:
389 return "NVPTXISD::MUL_WIDE_SIGNED";
390 case NVPTXISD::MUL_WIDE_UNSIGNED:
391 return "NVPTXISD::MUL_WIDE_UNSIGNED";
392 case NVPTXISD::Tex1DFloatS32: return "NVPTXISD::Tex1DFloatS32";
393 case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
394 case NVPTXISD::Tex1DFloatFloatLevel:
395 return "NVPTXISD::Tex1DFloatFloatLevel";
396 case NVPTXISD::Tex1DFloatFloatGrad:
397 return "NVPTXISD::Tex1DFloatFloatGrad";
398 case NVPTXISD::Tex1DS32S32: return "NVPTXISD::Tex1DS32S32";
399 case NVPTXISD::Tex1DS32Float: return "NVPTXISD::Tex1DS32Float";
400 case NVPTXISD::Tex1DS32FloatLevel:
401 return "NVPTXISD::Tex1DS32FloatLevel";
402 case NVPTXISD::Tex1DS32FloatGrad:
403 return "NVPTXISD::Tex1DS32FloatGrad";
404 case NVPTXISD::Tex1DU32S32: return "NVPTXISD::Tex1DU32S32";
405 case NVPTXISD::Tex1DU32Float: return "NVPTXISD::Tex1DU32Float";
406 case NVPTXISD::Tex1DU32FloatLevel:
407 return "NVPTXISD::Tex1DU32FloatLevel";
408 case NVPTXISD::Tex1DU32FloatGrad:
409 return "NVPTXISD::Tex1DU32FloatGrad";
410 case NVPTXISD::Tex1DArrayFloatS32: return "NVPTXISD::Tex1DArrayFloatS32";
411 case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
412 case NVPTXISD::Tex1DArrayFloatFloatLevel:
413 return "NVPTXISD::Tex1DArrayFloatFloatLevel";
414 case NVPTXISD::Tex1DArrayFloatFloatGrad:
415 return "NVPTXISD::Tex1DArrayFloatFloatGrad";
416 case NVPTXISD::Tex1DArrayS32S32: return "NVPTXISD::Tex1DArrayS32S32";
417 case NVPTXISD::Tex1DArrayS32Float: return "NVPTXISD::Tex1DArrayS32Float";
418 case NVPTXISD::Tex1DArrayS32FloatLevel:
419 return "NVPTXISD::Tex1DArrayS32FloatLevel";
420 case NVPTXISD::Tex1DArrayS32FloatGrad:
421 return "NVPTXISD::Tex1DArrayS32FloatGrad";
422 case NVPTXISD::Tex1DArrayU32S32: return "NVPTXISD::Tex1DArrayU32S32";
423 case NVPTXISD::Tex1DArrayU32Float: return "NVPTXISD::Tex1DArrayU32Float";
424 case NVPTXISD::Tex1DArrayU32FloatLevel:
425 return "NVPTXISD::Tex1DArrayU32FloatLevel";
426 case NVPTXISD::Tex1DArrayU32FloatGrad:
427 return "NVPTXISD::Tex1DArrayU32FloatGrad";
428 case NVPTXISD::Tex2DFloatS32: return "NVPTXISD::Tex2DFloatS32";
429 case NVPTXISD::Tex2DFloatFloat: return "NVPTXISD::Tex2DFloatFloat";
430 case NVPTXISD::Tex2DFloatFloatLevel:
431 return "NVPTXISD::Tex2DFloatFloatLevel";
432 case NVPTXISD::Tex2DFloatFloatGrad:
433 return "NVPTXISD::Tex2DFloatFloatGrad";
434 case NVPTXISD::Tex2DS32S32: return "NVPTXISD::Tex2DS32S32";
435 case NVPTXISD::Tex2DS32Float: return "NVPTXISD::Tex2DS32Float";
436 case NVPTXISD::Tex2DS32FloatLevel:
437 return "NVPTXISD::Tex2DS32FloatLevel";
438 case NVPTXISD::Tex2DS32FloatGrad:
439 return "NVPTXISD::Tex2DS32FloatGrad";
440 case NVPTXISD::Tex2DU32S32: return "NVPTXISD::Tex2DU32S32";
441 case NVPTXISD::Tex2DU32Float: return "NVPTXISD::Tex2DU32Float";
442 case NVPTXISD::Tex2DU32FloatLevel:
443 return "NVPTXISD::Tex2DU32FloatLevel";
444 case NVPTXISD::Tex2DU32FloatGrad:
445 return "NVPTXISD::Tex2DU32FloatGrad";
446 case NVPTXISD::Tex2DArrayFloatS32: return "NVPTXISD::Tex2DArrayFloatS32";
447 case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
448 case NVPTXISD::Tex2DArrayFloatFloatLevel:
449 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
450 case NVPTXISD::Tex2DArrayFloatFloatGrad:
451 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
452 case NVPTXISD::Tex2DArrayS32S32: return "NVPTXISD::Tex2DArrayS32S32";
453 case NVPTXISD::Tex2DArrayS32Float: return "NVPTXISD::Tex2DArrayS32Float";
454 case NVPTXISD::Tex2DArrayS32FloatLevel:
455 return "NVPTXISD::Tex2DArrayS32FloatLevel";
456 case NVPTXISD::Tex2DArrayS32FloatGrad:
457 return "NVPTXISD::Tex2DArrayS32FloatGrad";
458 case NVPTXISD::Tex2DArrayU32S32: return "NVPTXISD::Tex2DArrayU32S32";
459 case NVPTXISD::Tex2DArrayU32Float: return "NVPTXISD::Tex2DArrayU32Float";
460 case NVPTXISD::Tex2DArrayU32FloatLevel:
461 return "NVPTXISD::Tex2DArrayU32FloatLevel";
462 case NVPTXISD::Tex2DArrayU32FloatGrad:
463 return "NVPTXISD::Tex2DArrayU32FloatGrad";
464 case NVPTXISD::Tex3DFloatS32: return "NVPTXISD::Tex3DFloatS32";
465 case NVPTXISD::Tex3DFloatFloat: return "NVPTXISD::Tex3DFloatFloat";
466 case NVPTXISD::Tex3DFloatFloatLevel:
467 return "NVPTXISD::Tex3DFloatFloatLevel";
468 case NVPTXISD::Tex3DFloatFloatGrad:
469 return "NVPTXISD::Tex3DFloatFloatGrad";
470 case NVPTXISD::Tex3DS32S32: return "NVPTXISD::Tex3DS32S32";
471 case NVPTXISD::Tex3DS32Float: return "NVPTXISD::Tex3DS32Float";
472 case NVPTXISD::Tex3DS32FloatLevel:
473 return "NVPTXISD::Tex3DS32FloatLevel";
474 case NVPTXISD::Tex3DS32FloatGrad:
475 return "NVPTXISD::Tex3DS32FloatGrad";
476 case NVPTXISD::Tex3DU32S32: return "NVPTXISD::Tex3DU32S32";
477 case NVPTXISD::Tex3DU32Float: return "NVPTXISD::Tex3DU32Float";
478 case NVPTXISD::Tex3DU32FloatLevel:
479 return "NVPTXISD::Tex3DU32FloatLevel";
480 case NVPTXISD::Tex3DU32FloatGrad:
481 return "NVPTXISD::Tex3DU32FloatGrad";
482 case NVPTXISD::TexCubeFloatFloat: return "NVPTXISD::TexCubeFloatFloat";
483 case NVPTXISD::TexCubeFloatFloatLevel:
484 return "NVPTXISD::TexCubeFloatFloatLevel";
485 case NVPTXISD::TexCubeS32Float: return "NVPTXISD::TexCubeS32Float";
486 case NVPTXISD::TexCubeS32FloatLevel:
487 return "NVPTXISD::TexCubeS32FloatLevel";
488 case NVPTXISD::TexCubeU32Float: return "NVPTXISD::TexCubeU32Float";
489 case NVPTXISD::TexCubeU32FloatLevel:
490 return "NVPTXISD::TexCubeU32FloatLevel";
491 case NVPTXISD::TexCubeArrayFloatFloat:
492 return "NVPTXISD::TexCubeArrayFloatFloat";
493 case NVPTXISD::TexCubeArrayFloatFloatLevel:
494 return "NVPTXISD::TexCubeArrayFloatFloatLevel";
495 case NVPTXISD::TexCubeArrayS32Float:
496 return "NVPTXISD::TexCubeArrayS32Float";
497 case NVPTXISD::TexCubeArrayS32FloatLevel:
498 return "NVPTXISD::TexCubeArrayS32FloatLevel";
499 case NVPTXISD::TexCubeArrayU32Float:
500 return "NVPTXISD::TexCubeArrayU32Float";
501 case NVPTXISD::TexCubeArrayU32FloatLevel:
502 return "NVPTXISD::TexCubeArrayU32FloatLevel";
503 case NVPTXISD::Tld4R2DFloatFloat:
504 return "NVPTXISD::Tld4R2DFloatFloat";
505 case NVPTXISD::Tld4G2DFloatFloat:
506 return "NVPTXISD::Tld4G2DFloatFloat";
507 case NVPTXISD::Tld4B2DFloatFloat:
508 return "NVPTXISD::Tld4B2DFloatFloat";
509 case NVPTXISD::Tld4A2DFloatFloat:
510 return "NVPTXISD::Tld4A2DFloatFloat";
511 case NVPTXISD::Tld4R2DS64Float:
512 return "NVPTXISD::Tld4R2DS64Float";
513 case NVPTXISD::Tld4G2DS64Float:
514 return "NVPTXISD::Tld4G2DS64Float";
515 case NVPTXISD::Tld4B2DS64Float:
516 return "NVPTXISD::Tld4B2DS64Float";
517 case NVPTXISD::Tld4A2DS64Float:
518 return "NVPTXISD::Tld4A2DS64Float";
519 case NVPTXISD::Tld4R2DU64Float:
520 return "NVPTXISD::Tld4R2DU64Float";
521 case NVPTXISD::Tld4G2DU64Float:
522 return "NVPTXISD::Tld4G2DU64Float";
523 case NVPTXISD::Tld4B2DU64Float:
524 return "NVPTXISD::Tld4B2DU64Float";
525 case NVPTXISD::Tld4A2DU64Float:
526 return "NVPTXISD::Tld4A2DU64Float";
528 case NVPTXISD::TexUnified1DFloatS32:
529 return "NVPTXISD::TexUnified1DFloatS32";
530 case NVPTXISD::TexUnified1DFloatFloat:
531 return "NVPTXISD::TexUnified1DFloatFloat";
532 case NVPTXISD::TexUnified1DFloatFloatLevel:
533 return "NVPTXISD::TexUnified1DFloatFloatLevel";
534 case NVPTXISD::TexUnified1DFloatFloatGrad:
535 return "NVPTXISD::TexUnified1DFloatFloatGrad";
536 case NVPTXISD::TexUnified1DS32S32:
537 return "NVPTXISD::TexUnified1DS32S32";
538 case NVPTXISD::TexUnified1DS32Float:
539 return "NVPTXISD::TexUnified1DS32Float";
540 case NVPTXISD::TexUnified1DS32FloatLevel:
541 return "NVPTXISD::TexUnified1DS32FloatLevel";
542 case NVPTXISD::TexUnified1DS32FloatGrad:
543 return "NVPTXISD::TexUnified1DS32FloatGrad";
544 case NVPTXISD::TexUnified1DU32S32:
545 return "NVPTXISD::TexUnified1DU32S32";
546 case NVPTXISD::TexUnified1DU32Float:
547 return "NVPTXISD::TexUnified1DU32Float";
548 case NVPTXISD::TexUnified1DU32FloatLevel:
549 return "NVPTXISD::TexUnified1DU32FloatLevel";
550 case NVPTXISD::TexUnified1DU32FloatGrad:
551 return "NVPTXISD::TexUnified1DU32FloatGrad";
552 case NVPTXISD::TexUnified1DArrayFloatS32:
553 return "NVPTXISD::TexUnified1DArrayFloatS32";
554 case NVPTXISD::TexUnified1DArrayFloatFloat:
555 return "NVPTXISD::TexUnified1DArrayFloatFloat";
556 case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
557 return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
558 case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
559 return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
560 case NVPTXISD::TexUnified1DArrayS32S32:
561 return "NVPTXISD::TexUnified1DArrayS32S32";
562 case NVPTXISD::TexUnified1DArrayS32Float:
563 return "NVPTXISD::TexUnified1DArrayS32Float";
564 case NVPTXISD::TexUnified1DArrayS32FloatLevel:
565 return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
566 case NVPTXISD::TexUnified1DArrayS32FloatGrad:
567 return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
568 case NVPTXISD::TexUnified1DArrayU32S32:
569 return "NVPTXISD::TexUnified1DArrayU32S32";
570 case NVPTXISD::TexUnified1DArrayU32Float:
571 return "NVPTXISD::TexUnified1DArrayU32Float";
572 case NVPTXISD::TexUnified1DArrayU32FloatLevel:
573 return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
574 case NVPTXISD::TexUnified1DArrayU32FloatGrad:
575 return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
576 case NVPTXISD::TexUnified2DFloatS32:
577 return "NVPTXISD::TexUnified2DFloatS32";
578 case NVPTXISD::TexUnified2DFloatFloat:
579 return "NVPTXISD::TexUnified2DFloatFloat";
580 case NVPTXISD::TexUnified2DFloatFloatLevel:
581 return "NVPTXISD::TexUnified2DFloatFloatLevel";
582 case NVPTXISD::TexUnified2DFloatFloatGrad:
583 return "NVPTXISD::TexUnified2DFloatFloatGrad";
584 case NVPTXISD::TexUnified2DS32S32:
585 return "NVPTXISD::TexUnified2DS32S32";
586 case NVPTXISD::TexUnified2DS32Float:
587 return "NVPTXISD::TexUnified2DS32Float";
588 case NVPTXISD::TexUnified2DS32FloatLevel:
589 return "NVPTXISD::TexUnified2DS32FloatLevel";
590 case NVPTXISD::TexUnified2DS32FloatGrad:
591 return "NVPTXISD::TexUnified2DS32FloatGrad";
592 case NVPTXISD::TexUnified2DU32S32:
593 return "NVPTXISD::TexUnified2DU32S32";
594 case NVPTXISD::TexUnified2DU32Float:
595 return "NVPTXISD::TexUnified2DU32Float";
596 case NVPTXISD::TexUnified2DU32FloatLevel:
597 return "NVPTXISD::TexUnified2DU32FloatLevel";
598 case NVPTXISD::TexUnified2DU32FloatGrad:
599 return "NVPTXISD::TexUnified2DU32FloatGrad";
600 case NVPTXISD::TexUnified2DArrayFloatS32:
601 return "NVPTXISD::TexUnified2DArrayFloatS32";
602 case NVPTXISD::TexUnified2DArrayFloatFloat:
603 return "NVPTXISD::TexUnified2DArrayFloatFloat";
604 case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
605 return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
606 case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
607 return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
608 case NVPTXISD::TexUnified2DArrayS32S32:
609 return "NVPTXISD::TexUnified2DArrayS32S32";
610 case NVPTXISD::TexUnified2DArrayS32Float:
611 return "NVPTXISD::TexUnified2DArrayS32Float";
612 case NVPTXISD::TexUnified2DArrayS32FloatLevel:
613 return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
614 case NVPTXISD::TexUnified2DArrayS32FloatGrad:
615 return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
616 case NVPTXISD::TexUnified2DArrayU32S32:
617 return "NVPTXISD::TexUnified2DArrayU32S32";
618 case NVPTXISD::TexUnified2DArrayU32Float:
619 return "NVPTXISD::TexUnified2DArrayU32Float";
620 case NVPTXISD::TexUnified2DArrayU32FloatLevel:
621 return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
622 case NVPTXISD::TexUnified2DArrayU32FloatGrad:
623 return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
624 case NVPTXISD::TexUnified3DFloatS32:
625 return "NVPTXISD::TexUnified3DFloatS32";
626 case NVPTXISD::TexUnified3DFloatFloat:
627 return "NVPTXISD::TexUnified3DFloatFloat";
628 case NVPTXISD::TexUnified3DFloatFloatLevel:
629 return "NVPTXISD::TexUnified3DFloatFloatLevel";
630 case NVPTXISD::TexUnified3DFloatFloatGrad:
631 return "NVPTXISD::TexUnified3DFloatFloatGrad";
632 case NVPTXISD::TexUnified3DS32S32:
633 return "NVPTXISD::TexUnified3DS32S32";
634 case NVPTXISD::TexUnified3DS32Float:
635 return "NVPTXISD::TexUnified3DS32Float";
636 case NVPTXISD::TexUnified3DS32FloatLevel:
637 return "NVPTXISD::TexUnified3DS32FloatLevel";
638 case NVPTXISD::TexUnified3DS32FloatGrad:
639 return "NVPTXISD::TexUnified3DS32FloatGrad";
640 case NVPTXISD::TexUnified3DU32S32:
641 return "NVPTXISD::TexUnified3DU32S32";
642 case NVPTXISD::TexUnified3DU32Float:
643 return "NVPTXISD::TexUnified3DU32Float";
644 case NVPTXISD::TexUnified3DU32FloatLevel:
645 return "NVPTXISD::TexUnified3DU32FloatLevel";
646 case NVPTXISD::TexUnified3DU32FloatGrad:
647 return "NVPTXISD::TexUnified3DU32FloatGrad";
648 case NVPTXISD::TexUnifiedCubeFloatFloat:
649 return "NVPTXISD::TexUnifiedCubeFloatFloat";
650 case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
651 return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
652 case NVPTXISD::TexUnifiedCubeS32Float:
653 return "NVPTXISD::TexUnifiedCubeS32Float";
654 case NVPTXISD::TexUnifiedCubeS32FloatLevel:
655 return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
656 case NVPTXISD::TexUnifiedCubeU32Float:
657 return "NVPTXISD::TexUnifiedCubeU32Float";
658 case NVPTXISD::TexUnifiedCubeU32FloatLevel:
659 return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
660 case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
661 return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
662 case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
663 return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
664 case NVPTXISD::TexUnifiedCubeArrayS32Float:
665 return "NVPTXISD::TexUnifiedCubeArrayS32Float";
666 case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
667 return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
668 case NVPTXISD::TexUnifiedCubeArrayU32Float:
669 return "NVPTXISD::TexUnifiedCubeArrayU32Float";
670 case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
671 return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
672 case NVPTXISD::Tld4UnifiedR2DFloatFloat:
673 return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
674 case NVPTXISD::Tld4UnifiedG2DFloatFloat:
675 return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
676 case NVPTXISD::Tld4UnifiedB2DFloatFloat:
677 return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
678 case NVPTXISD::Tld4UnifiedA2DFloatFloat:
679 return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
680 case NVPTXISD::Tld4UnifiedR2DS64Float:
681 return "NVPTXISD::Tld4UnifiedR2DS64Float";
682 case NVPTXISD::Tld4UnifiedG2DS64Float:
683 return "NVPTXISD::Tld4UnifiedG2DS64Float";
684 case NVPTXISD::Tld4UnifiedB2DS64Float:
685 return "NVPTXISD::Tld4UnifiedB2DS64Float";
686 case NVPTXISD::Tld4UnifiedA2DS64Float:
687 return "NVPTXISD::Tld4UnifiedA2DS64Float";
688 case NVPTXISD::Tld4UnifiedR2DU64Float:
689 return "NVPTXISD::Tld4UnifiedR2DU64Float";
690 case NVPTXISD::Tld4UnifiedG2DU64Float:
691 return "NVPTXISD::Tld4UnifiedG2DU64Float";
692 case NVPTXISD::Tld4UnifiedB2DU64Float:
693 return "NVPTXISD::Tld4UnifiedB2DU64Float";
694 case NVPTXISD::Tld4UnifiedA2DU64Float:
695 return "NVPTXISD::Tld4UnifiedA2DU64Float";
697 case NVPTXISD::Suld1DI8Clamp: return "NVPTXISD::Suld1DI8Clamp";
698 case NVPTXISD::Suld1DI16Clamp: return "NVPTXISD::Suld1DI16Clamp";
699 case NVPTXISD::Suld1DI32Clamp: return "NVPTXISD::Suld1DI32Clamp";
700 case NVPTXISD::Suld1DI64Clamp: return "NVPTXISD::Suld1DI64Clamp";
701 case NVPTXISD::Suld1DV2I8Clamp: return "NVPTXISD::Suld1DV2I8Clamp";
702 case NVPTXISD::Suld1DV2I16Clamp: return "NVPTXISD::Suld1DV2I16Clamp";
703 case NVPTXISD::Suld1DV2I32Clamp: return "NVPTXISD::Suld1DV2I32Clamp";
704 case NVPTXISD::Suld1DV2I64Clamp: return "NVPTXISD::Suld1DV2I64Clamp";
705 case NVPTXISD::Suld1DV4I8Clamp: return "NVPTXISD::Suld1DV4I8Clamp";
706 case NVPTXISD::Suld1DV4I16Clamp: return "NVPTXISD::Suld1DV4I16Clamp";
707 case NVPTXISD::Suld1DV4I32Clamp: return "NVPTXISD::Suld1DV4I32Clamp";
709 case NVPTXISD::Suld1DArrayI8Clamp: return "NVPTXISD::Suld1DArrayI8Clamp";
710 case NVPTXISD::Suld1DArrayI16Clamp: return "NVPTXISD::Suld1DArrayI16Clamp";
711 case NVPTXISD::Suld1DArrayI32Clamp: return "NVPTXISD::Suld1DArrayI32Clamp";
712 case NVPTXISD::Suld1DArrayI64Clamp: return "NVPTXISD::Suld1DArrayI64Clamp";
713 case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
714 case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
715 case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
716 case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
717 case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
718 case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
719 case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
721 case NVPTXISD::Suld2DI8Clamp: return "NVPTXISD::Suld2DI8Clamp";
722 case NVPTXISD::Suld2DI16Clamp: return "NVPTXISD::Suld2DI16Clamp";
723 case NVPTXISD::Suld2DI32Clamp: return "NVPTXISD::Suld2DI32Clamp";
724 case NVPTXISD::Suld2DI64Clamp: return "NVPTXISD::Suld2DI64Clamp";
725 case NVPTXISD::Suld2DV2I8Clamp: return "NVPTXISD::Suld2DV2I8Clamp";
726 case NVPTXISD::Suld2DV2I16Clamp: return "NVPTXISD::Suld2DV2I16Clamp";
727 case NVPTXISD::Suld2DV2I32Clamp: return "NVPTXISD::Suld2DV2I32Clamp";
728 case NVPTXISD::Suld2DV2I64Clamp: return "NVPTXISD::Suld2DV2I64Clamp";
729 case NVPTXISD::Suld2DV4I8Clamp: return "NVPTXISD::Suld2DV4I8Clamp";
730 case NVPTXISD::Suld2DV4I16Clamp: return "NVPTXISD::Suld2DV4I16Clamp";
731 case NVPTXISD::Suld2DV4I32Clamp: return "NVPTXISD::Suld2DV4I32Clamp";
733 case NVPTXISD::Suld2DArrayI8Clamp: return "NVPTXISD::Suld2DArrayI8Clamp";
734 case NVPTXISD::Suld2DArrayI16Clamp: return "NVPTXISD::Suld2DArrayI16Clamp";
735 case NVPTXISD::Suld2DArrayI32Clamp: return "NVPTXISD::Suld2DArrayI32Clamp";
736 case NVPTXISD::Suld2DArrayI64Clamp: return "NVPTXISD::Suld2DArrayI64Clamp";
737 case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
738 case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
739 case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
740 case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
741 case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
742 case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
743 case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
745 case NVPTXISD::Suld3DI8Clamp: return "NVPTXISD::Suld3DI8Clamp";
746 case NVPTXISD::Suld3DI16Clamp: return "NVPTXISD::Suld3DI16Clamp";
747 case NVPTXISD::Suld3DI32Clamp: return "NVPTXISD::Suld3DI32Clamp";
748 case NVPTXISD::Suld3DI64Clamp: return "NVPTXISD::Suld3DI64Clamp";
749 case NVPTXISD::Suld3DV2I8Clamp: return "NVPTXISD::Suld3DV2I8Clamp";
750 case NVPTXISD::Suld3DV2I16Clamp: return "NVPTXISD::Suld3DV2I16Clamp";
751 case NVPTXISD::Suld3DV2I32Clamp: return "NVPTXISD::Suld3DV2I32Clamp";
752 case NVPTXISD::Suld3DV2I64Clamp: return "NVPTXISD::Suld3DV2I64Clamp";
753 case NVPTXISD::Suld3DV4I8Clamp: return "NVPTXISD::Suld3DV4I8Clamp";
754 case NVPTXISD::Suld3DV4I16Clamp: return "NVPTXISD::Suld3DV4I16Clamp";
755 case NVPTXISD::Suld3DV4I32Clamp: return "NVPTXISD::Suld3DV4I32Clamp";
757 case NVPTXISD::Suld1DI8Trap: return "NVPTXISD::Suld1DI8Trap";
758 case NVPTXISD::Suld1DI16Trap: return "NVPTXISD::Suld1DI16Trap";
759 case NVPTXISD::Suld1DI32Trap: return "NVPTXISD::Suld1DI32Trap";
760 case NVPTXISD::Suld1DI64Trap: return "NVPTXISD::Suld1DI64Trap";
761 case NVPTXISD::Suld1DV2I8Trap: return "NVPTXISD::Suld1DV2I8Trap";
762 case NVPTXISD::Suld1DV2I16Trap: return "NVPTXISD::Suld1DV2I16Trap";
763 case NVPTXISD::Suld1DV2I32Trap: return "NVPTXISD::Suld1DV2I32Trap";
764 case NVPTXISD::Suld1DV2I64Trap: return "NVPTXISD::Suld1DV2I64Trap";
765 case NVPTXISD::Suld1DV4I8Trap: return "NVPTXISD::Suld1DV4I8Trap";
766 case NVPTXISD::Suld1DV4I16Trap: return "NVPTXISD::Suld1DV4I16Trap";
767 case NVPTXISD::Suld1DV4I32Trap: return "NVPTXISD::Suld1DV4I32Trap";
769 case NVPTXISD::Suld1DArrayI8Trap: return "NVPTXISD::Suld1DArrayI8Trap";
770 case NVPTXISD::Suld1DArrayI16Trap: return "NVPTXISD::Suld1DArrayI16Trap";
771 case NVPTXISD::Suld1DArrayI32Trap: return "NVPTXISD::Suld1DArrayI32Trap";
772 case NVPTXISD::Suld1DArrayI64Trap: return "NVPTXISD::Suld1DArrayI64Trap";
773 case NVPTXISD::Suld1DArrayV2I8Trap: return "NVPTXISD::Suld1DArrayV2I8Trap";
774 case NVPTXISD::Suld1DArrayV2I16Trap: return "NVPTXISD::Suld1DArrayV2I16Trap";
775 case NVPTXISD::Suld1DArrayV2I32Trap: return "NVPTXISD::Suld1DArrayV2I32Trap";
776 case NVPTXISD::Suld1DArrayV2I64Trap: return "NVPTXISD::Suld1DArrayV2I64Trap";
777 case NVPTXISD::Suld1DArrayV4I8Trap: return "NVPTXISD::Suld1DArrayV4I8Trap";
778 case NVPTXISD::Suld1DArrayV4I16Trap: return "NVPTXISD::Suld1DArrayV4I16Trap";
779 case NVPTXISD::Suld1DArrayV4I32Trap: return "NVPTXISD::Suld1DArrayV4I32Trap";
781 case NVPTXISD::Suld2DI8Trap: return "NVPTXISD::Suld2DI8Trap";
782 case NVPTXISD::Suld2DI16Trap: return "NVPTXISD::Suld2DI16Trap";
783 case NVPTXISD::Suld2DI32Trap: return "NVPTXISD::Suld2DI32Trap";
784 case NVPTXISD::Suld2DI64Trap: return "NVPTXISD::Suld2DI64Trap";
785 case NVPTXISD::Suld2DV2I8Trap: return "NVPTXISD::Suld2DV2I8Trap";
786 case NVPTXISD::Suld2DV2I16Trap: return "NVPTXISD::Suld2DV2I16Trap";
787 case NVPTXISD::Suld2DV2I32Trap: return "NVPTXISD::Suld2DV2I32Trap";
788 case NVPTXISD::Suld2DV2I64Trap: return "NVPTXISD::Suld2DV2I64Trap";
789 case NVPTXISD::Suld2DV4I8Trap: return "NVPTXISD::Suld2DV4I8Trap";
790 case NVPTXISD::Suld2DV4I16Trap: return "NVPTXISD::Suld2DV4I16Trap";
791 case NVPTXISD::Suld2DV4I32Trap: return "NVPTXISD::Suld2DV4I32Trap";
793 case NVPTXISD::Suld2DArrayI8Trap: return "NVPTXISD::Suld2DArrayI8Trap";
794 case NVPTXISD::Suld2DArrayI16Trap: return "NVPTXISD::Suld2DArrayI16Trap";
795 case NVPTXISD::Suld2DArrayI32Trap: return "NVPTXISD::Suld2DArrayI32Trap";
796 case NVPTXISD::Suld2DArrayI64Trap: return "NVPTXISD::Suld2DArrayI64Trap";
797 case NVPTXISD::Suld2DArrayV2I8Trap: return "NVPTXISD::Suld2DArrayV2I8Trap";
798 case NVPTXISD::Suld2DArrayV2I16Trap: return "NVPTXISD::Suld2DArrayV2I16Trap";
799 case NVPTXISD::Suld2DArrayV2I32Trap: return "NVPTXISD::Suld2DArrayV2I32Trap";
800 case NVPTXISD::Suld2DArrayV2I64Trap: return "NVPTXISD::Suld2DArrayV2I64Trap";
801 case NVPTXISD::Suld2DArrayV4I8Trap: return "NVPTXISD::Suld2DArrayV4I8Trap";
802 case NVPTXISD::Suld2DArrayV4I16Trap: return "NVPTXISD::Suld2DArrayV4I16Trap";
803 case NVPTXISD::Suld2DArrayV4I32Trap: return "NVPTXISD::Suld2DArrayV4I32Trap";
805 case NVPTXISD::Suld3DI8Trap: return "NVPTXISD::Suld3DI8Trap";
806 case NVPTXISD::Suld3DI16Trap: return "NVPTXISD::Suld3DI16Trap";
807 case NVPTXISD::Suld3DI32Trap: return "NVPTXISD::Suld3DI32Trap";
808 case NVPTXISD::Suld3DI64Trap: return "NVPTXISD::Suld3DI64Trap";
809 case NVPTXISD::Suld3DV2I8Trap: return "NVPTXISD::Suld3DV2I8Trap";
810 case NVPTXISD::Suld3DV2I16Trap: return "NVPTXISD::Suld3DV2I16Trap";
811 case NVPTXISD::Suld3DV2I32Trap: return "NVPTXISD::Suld3DV2I32Trap";
812 case NVPTXISD::Suld3DV2I64Trap: return "NVPTXISD::Suld3DV2I64Trap";
813 case NVPTXISD::Suld3DV4I8Trap: return "NVPTXISD::Suld3DV4I8Trap";
814 case NVPTXISD::Suld3DV4I16Trap: return "NVPTXISD::Suld3DV4I16Trap";
815 case NVPTXISD::Suld3DV4I32Trap: return "NVPTXISD::Suld3DV4I32Trap";
817 case NVPTXISD::Suld1DI8Zero: return "NVPTXISD::Suld1DI8Zero";
818 case NVPTXISD::Suld1DI16Zero: return "NVPTXISD::Suld1DI16Zero";
819 case NVPTXISD::Suld1DI32Zero: return "NVPTXISD::Suld1DI32Zero";
820 case NVPTXISD::Suld1DI64Zero: return "NVPTXISD::Suld1DI64Zero";
821 case NVPTXISD::Suld1DV2I8Zero: return "NVPTXISD::Suld1DV2I8Zero";
822 case NVPTXISD::Suld1DV2I16Zero: return "NVPTXISD::Suld1DV2I16Zero";
823 case NVPTXISD::Suld1DV2I32Zero: return "NVPTXISD::Suld1DV2I32Zero";
824 case NVPTXISD::Suld1DV2I64Zero: return "NVPTXISD::Suld1DV2I64Zero";
825 case NVPTXISD::Suld1DV4I8Zero: return "NVPTXISD::Suld1DV4I8Zero";
826 case NVPTXISD::Suld1DV4I16Zero: return "NVPTXISD::Suld1DV4I16Zero";
827 case NVPTXISD::Suld1DV4I32Zero: return "NVPTXISD::Suld1DV4I32Zero";
829 case NVPTXISD::Suld1DArrayI8Zero: return "NVPTXISD::Suld1DArrayI8Zero";
830 case NVPTXISD::Suld1DArrayI16Zero: return "NVPTXISD::Suld1DArrayI16Zero";
831 case NVPTXISD::Suld1DArrayI32Zero: return "NVPTXISD::Suld1DArrayI32Zero";
832 case NVPTXISD::Suld1DArrayI64Zero: return "NVPTXISD::Suld1DArrayI64Zero";
833 case NVPTXISD::Suld1DArrayV2I8Zero: return "NVPTXISD::Suld1DArrayV2I8Zero";
834 case NVPTXISD::Suld1DArrayV2I16Zero: return "NVPTXISD::Suld1DArrayV2I16Zero";
835 case NVPTXISD::Suld1DArrayV2I32Zero: return "NVPTXISD::Suld1DArrayV2I32Zero";
836 case NVPTXISD::Suld1DArrayV2I64Zero: return "NVPTXISD::Suld1DArrayV2I64Zero";
837 case NVPTXISD::Suld1DArrayV4I8Zero: return "NVPTXISD::Suld1DArrayV4I8Zero";
838 case NVPTXISD::Suld1DArrayV4I16Zero: return "NVPTXISD::Suld1DArrayV4I16Zero";
839 case NVPTXISD::Suld1DArrayV4I32Zero: return "NVPTXISD::Suld1DArrayV4I32Zero";
841 case NVPTXISD::Suld2DI8Zero: return "NVPTXISD::Suld2DI8Zero";
842 case NVPTXISD::Suld2DI16Zero: return "NVPTXISD::Suld2DI16Zero";
843 case NVPTXISD::Suld2DI32Zero: return "NVPTXISD::Suld2DI32Zero";
844 case NVPTXISD::Suld2DI64Zero: return "NVPTXISD::Suld2DI64Zero";
845 case NVPTXISD::Suld2DV2I8Zero: return "NVPTXISD::Suld2DV2I8Zero";
846 case NVPTXISD::Suld2DV2I16Zero: return "NVPTXISD::Suld2DV2I16Zero";
847 case NVPTXISD::Suld2DV2I32Zero: return "NVPTXISD::Suld2DV2I32Zero";
848 case NVPTXISD::Suld2DV2I64Zero: return "NVPTXISD::Suld2DV2I64Zero";
849 case NVPTXISD::Suld2DV4I8Zero: return "NVPTXISD::Suld2DV4I8Zero";
850 case NVPTXISD::Suld2DV4I16Zero: return "NVPTXISD::Suld2DV4I16Zero";
851 case NVPTXISD::Suld2DV4I32Zero: return "NVPTXISD::Suld2DV4I32Zero";
853 case NVPTXISD::Suld2DArrayI8Zero: return "NVPTXISD::Suld2DArrayI8Zero";
854 case NVPTXISD::Suld2DArrayI16Zero: return "NVPTXISD::Suld2DArrayI16Zero";
855 case NVPTXISD::Suld2DArrayI32Zero: return "NVPTXISD::Suld2DArrayI32Zero";
856 case NVPTXISD::Suld2DArrayI64Zero: return "NVPTXISD::Suld2DArrayI64Zero";
857 case NVPTXISD::Suld2DArrayV2I8Zero: return "NVPTXISD::Suld2DArrayV2I8Zero";
858 case NVPTXISD::Suld2DArrayV2I16Zero: return "NVPTXISD::Suld2DArrayV2I16Zero";
859 case NVPTXISD::Suld2DArrayV2I32Zero: return "NVPTXISD::Suld2DArrayV2I32Zero";
860 case NVPTXISD::Suld2DArrayV2I64Zero: return "NVPTXISD::Suld2DArrayV2I64Zero";
861 case NVPTXISD::Suld2DArrayV4I8Zero: return "NVPTXISD::Suld2DArrayV4I8Zero";
862 case NVPTXISD::Suld2DArrayV4I16Zero: return "NVPTXISD::Suld2DArrayV4I16Zero";
863 case NVPTXISD::Suld2DArrayV4I32Zero: return "NVPTXISD::Suld2DArrayV4I32Zero";
865 case NVPTXISD::Suld3DI8Zero: return "NVPTXISD::Suld3DI8Zero";
866 case NVPTXISD::Suld3DI16Zero: return "NVPTXISD::Suld3DI16Zero";
867 case NVPTXISD::Suld3DI32Zero: return "NVPTXISD::Suld3DI32Zero";
868 case NVPTXISD::Suld3DI64Zero: return "NVPTXISD::Suld3DI64Zero";
869 case NVPTXISD::Suld3DV2I8Zero: return "NVPTXISD::Suld3DV2I8Zero";
870 case NVPTXISD::Suld3DV2I16Zero: return "NVPTXISD::Suld3DV2I16Zero";
871 case NVPTXISD::Suld3DV2I32Zero: return "NVPTXISD::Suld3DV2I32Zero";
872 case NVPTXISD::Suld3DV2I64Zero: return "NVPTXISD::Suld3DV2I64Zero";
873 case NVPTXISD::Suld3DV4I8Zero: return "NVPTXISD::Suld3DV4I8Zero";
874 case NVPTXISD::Suld3DV4I16Zero: return "NVPTXISD::Suld3DV4I16Zero";
875 case NVPTXISD::Suld3DV4I32Zero: return "NVPTXISD::Suld3DV4I32Zero";
880 TargetLoweringBase::LegalizeTypeAction
881 NVPTXTargetLowering::getPreferredVectorAction(EVT VT) const {
882 if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
883 return TypeSplitVector;
885 return TargetLoweringBase::getPreferredVectorAction(VT);
889 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
891 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
892 auto PtrVT = getPointerTy(DAG.getDataLayout());
893 Op = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
894 return DAG.getNode(NVPTXISD::Wrapper, dl, PtrVT, Op);
897 std::string NVPTXTargetLowering::getPrototype(
898 const DataLayout &DL, Type *retTy, const ArgListTy &Args,
899 const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment,
900 const ImmutableCallSite *CS) const {
901 auto PtrVT = getPointerTy(DL);
903 bool isABI = (STI.getSmVersion() >= 20);
904 assert(isABI && "Non-ABI compilation is not supported");
909 O << "prototype_" << uniqueCallSite << " : .callprototype ";
911 if (retTy->getTypeID() == Type::VoidTyID) {
915 if (retTy->isFloatingPointTy() || retTy->isIntegerTy()) {
917 if (auto *ITy = dyn_cast<IntegerType>(retTy)) {
918 size = ITy->getBitWidth();
922 assert(retTy->isFloatingPointTy() &&
923 "Floating point type expected here");
924 size = retTy->getPrimitiveSizeInBits();
927 O << ".param .b" << size << " _";
928 } else if (isa<PointerType>(retTy)) {
929 O << ".param .b" << PtrVT.getSizeInBits() << " _";
930 } else if ((retTy->getTypeID() == Type::StructTyID) ||
931 isa<VectorType>(retTy)) {
932 auto &DL = CS->getCalledFunction()->getParent()->getDataLayout();
933 O << ".param .align " << retAlignment << " .b8 _["
934 << DL.getTypeAllocSize(retTy) << "]";
936 llvm_unreachable("Unknown return type");
945 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
946 Type *Ty = Args[i].Ty;
952 if (!Outs[OIdx].Flags.isByVal()) {
953 if (Ty->isAggregateType() || Ty->isVectorTy()) {
955 const CallInst *CallI = cast<CallInst>(CS->getInstruction());
956 // +1 because index 0 is reserved for return type alignment
957 if (!llvm::getAlign(*CallI, i + 1, align))
958 align = DL.getABITypeAlignment(Ty);
959 unsigned sz = DL.getTypeAllocSize(Ty);
960 O << ".param .align " << align << " .b8 ";
962 O << "[" << sz << "]";
963 // update the index for Outs
964 SmallVector<EVT, 16> vtparts;
965 ComputeValueVTs(*this, DL, Ty, vtparts);
966 if (unsigned len = vtparts.size())
970 // i8 types in IR will be i16 types in SDAG
971 assert((getValueType(DL, Ty) == Outs[OIdx].VT ||
972 (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
973 "type mismatch between callee prototype and arguments");
976 if (isa<IntegerType>(Ty)) {
977 sz = cast<IntegerType>(Ty)->getBitWidth();
980 } else if (isa<PointerType>(Ty))
981 sz = PtrVT.getSizeInBits();
983 sz = Ty->getPrimitiveSizeInBits();
984 O << ".param .b" << sz << " ";
988 auto *PTy = dyn_cast<PointerType>(Ty);
989 assert(PTy && "Param with byval attribute should be a pointer type");
990 Type *ETy = PTy->getElementType();
992 unsigned align = Outs[OIdx].Flags.getByValAlign();
993 unsigned sz = DL.getTypeAllocSize(ETy);
994 O << ".param .align " << align << " .b8 ";
996 O << "[" << sz << "]";
1003 NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
1004 const ImmutableCallSite *CS,
1006 unsigned Idx) const {
1008 const Value *DirectCallee = CS->getCalledFunction();
1010 if (!DirectCallee) {
1011 // We don't have a direct function symbol, but that may be because of
1012 // constant cast instructions in the call.
1013 const Instruction *CalleeI = CS->getInstruction();
1014 assert(CalleeI && "Call target is not a function or derived value?");
1016 // With bitcast'd call targets, the instruction will be the call
1017 if (isa<CallInst>(CalleeI)) {
1018 // Check if we have call alignment metadata
1019 if (llvm::getAlign(*cast<CallInst>(CalleeI), Idx, Align))
1022 const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
1023 // Ignore any bitcast instructions
1024 while(isa<ConstantExpr>(CalleeV)) {
1025 const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
1028 // Look through the bitcast
1029 CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
1032 // We have now looked past all of the bitcasts. Do we finally have a
1034 if (isa<Function>(CalleeV))
1035 DirectCallee = CalleeV;
1039 // Check for function alignment information if we found that the
1040 // ultimate target is a Function
1042 if (llvm::getAlign(*cast<Function>(DirectCallee), Idx, Align))
1045 // Call is indirect or alignment information is not available, fall back to
1046 // the ABI type alignment
1047 auto &DL = CS->getCaller()->getParent()->getDataLayout();
1048 return DL.getABITypeAlignment(Ty);
1051 SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1052 SmallVectorImpl<SDValue> &InVals) const {
1053 SelectionDAG &DAG = CLI.DAG;
1055 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1056 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1057 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1058 SDValue Chain = CLI.Chain;
1059 SDValue Callee = CLI.Callee;
1060 bool &isTailCall = CLI.IsTailCall;
1061 ArgListTy &Args = CLI.getArgs();
1062 Type *retTy = CLI.RetTy;
1063 ImmutableCallSite *CS = CLI.CS;
1065 bool isABI = (STI.getSmVersion() >= 20);
1066 assert(isABI && "Non-ABI compilation is not supported");
1069 MachineFunction &MF = DAG.getMachineFunction();
1070 const Function *F = MF.getFunction();
1071 auto &DL = MF.getDataLayout();
1073 SDValue tempChain = Chain;
1074 Chain = DAG.getCALLSEQ_START(Chain,
1075 DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1077 SDValue InFlag = Chain.getValue(1);
1079 unsigned paramCount = 0;
1080 // Args.size() and Outs.size() need not match.
1081 // Outs.size() will be larger
1082 // * if there is an aggregate argument with multiple fields (each field
1083 // showing up separately in Outs)
1084 // * if there is a vector argument with more than typical vector-length
1085 // elements (generally if more than 4) where each vector element is
1086 // individually present in Outs.
1087 // So a different index should be used for indexing into Outs/OutVals.
1088 // See similar issue in LowerFormalArguments.
1090 // Declare the .params or .reg need to pass values
1092 for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
1093 EVT VT = Outs[OIdx].VT;
1094 Type *Ty = Args[i].Ty;
1096 if (!Outs[OIdx].Flags.isByVal()) {
1097 if (Ty->isAggregateType()) {
1099 SmallVector<EVT, 16> vtparts;
1100 SmallVector<uint64_t, 16> Offsets;
1101 ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts, &Offsets,
1104 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
1105 // declare .param .align <align> .b8 .param<n>[<size>];
1106 unsigned sz = DL.getTypeAllocSize(Ty);
1107 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1108 SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, dl,
1110 DAG.getConstant(paramCount, dl, MVT::i32),
1111 DAG.getConstant(sz, dl, MVT::i32),
1113 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1115 InFlag = Chain.getValue(1);
1116 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1117 EVT elemtype = vtparts[j];
1118 unsigned ArgAlign = GreatestCommonDivisor64(align, Offsets[j]);
1119 if (elemtype.isInteger() && (sz < 8))
1121 SDValue StVal = OutVals[OIdx];
1122 if (elemtype.getSizeInBits() < 16) {
1123 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
1125 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1126 SDValue CopyParamOps[] = { Chain,
1127 DAG.getConstant(paramCount, dl, MVT::i32),
1128 DAG.getConstant(Offsets[j], dl, MVT::i32),
1130 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
1131 CopyParamVTs, CopyParamOps,
1132 elemtype, MachinePointerInfo(),
1134 InFlag = Chain.getValue(1);
1137 if (vtparts.size() > 0)
1142 if (Ty->isVectorTy()) {
1143 EVT ObjectVT = getValueType(DL, Ty);
1144 unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
1145 // declare .param .align <align> .b8 .param<n>[<size>];
1146 unsigned sz = DL.getTypeAllocSize(Ty);
1147 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1148 SDValue DeclareParamOps[] = { Chain,
1149 DAG.getConstant(align, dl, MVT::i32),
1150 DAG.getConstant(paramCount, dl, MVT::i32),
1151 DAG.getConstant(sz, dl, MVT::i32),
1153 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1155 InFlag = Chain.getValue(1);
1156 unsigned NumElts = ObjectVT.getVectorNumElements();
1157 EVT EltVT = ObjectVT.getVectorElementType();
1159 bool NeedExtend = false;
1160 if (EltVT.getSizeInBits() < 16) {
1167 SDValue Elt = OutVals[OIdx++];
1169 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt);
1171 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1172 SDValue CopyParamOps[] = { Chain,
1173 DAG.getConstant(paramCount, dl, MVT::i32),
1174 DAG.getConstant(0, dl, MVT::i32), Elt,
1176 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
1177 CopyParamVTs, CopyParamOps,
1178 MemVT, MachinePointerInfo());
1179 InFlag = Chain.getValue(1);
1180 } else if (NumElts == 2) {
1181 SDValue Elt0 = OutVals[OIdx++];
1182 SDValue Elt1 = OutVals[OIdx++];
1184 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0);
1185 Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1);
1188 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1189 SDValue CopyParamOps[] = { Chain,
1190 DAG.getConstant(paramCount, dl, MVT::i32),
1191 DAG.getConstant(0, dl, MVT::i32), Elt0,
1193 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
1194 CopyParamVTs, CopyParamOps,
1195 MemVT, MachinePointerInfo());
1196 InFlag = Chain.getValue(1);
1198 unsigned curOffset = 0;
1200 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
1202 // vector will be expanded to a power of 2 elements, so we know we can
1203 // always round up to the next multiple of 4 when creating the vector
1205 // e.g. 4 elem => 1 st.v4
1206 // 6 elem => 2 st.v4
1207 // 8 elem => 2 st.v4
1208 // 11 elem => 3 st.v4
1209 unsigned VecSize = 4;
1210 if (EltVT.getSizeInBits() == 64)
1213 // This is potentially only part of a vector, so assume all elements
1214 // are packed together.
1215 unsigned PerStoreOffset = MemVT.getStoreSizeInBits() / 8 * VecSize;
1217 for (unsigned i = 0; i < NumElts; i += VecSize) {
1220 SmallVector<SDValue, 8> Ops;
1221 Ops.push_back(Chain);
1222 Ops.push_back(DAG.getConstant(paramCount, dl, MVT::i32));
1223 Ops.push_back(DAG.getConstant(curOffset, dl, MVT::i32));
1225 unsigned Opc = NVPTXISD::StoreParamV2;
1227 StoreVal = OutVals[OIdx++];
1229 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1230 Ops.push_back(StoreVal);
1232 if (i + 1 < NumElts) {
1233 StoreVal = OutVals[OIdx++];
1236 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1238 StoreVal = DAG.getUNDEF(EltVT);
1240 Ops.push_back(StoreVal);
1243 Opc = NVPTXISD::StoreParamV4;
1244 if (i + 2 < NumElts) {
1245 StoreVal = OutVals[OIdx++];
1248 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1250 StoreVal = DAG.getUNDEF(EltVT);
1252 Ops.push_back(StoreVal);
1254 if (i + 3 < NumElts) {
1255 StoreVal = OutVals[OIdx++];
1258 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1260 StoreVal = DAG.getUNDEF(EltVT);
1262 Ops.push_back(StoreVal);
1265 Ops.push_back(InFlag);
1267 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1268 Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, Ops,
1269 MemVT, MachinePointerInfo());
1270 InFlag = Chain.getValue(1);
1271 curOffset += PerStoreOffset;
1279 // for ABI, declare .param .b<size> .param<n>;
1280 unsigned sz = VT.getSizeInBits();
1281 bool needExtend = false;
1282 if (VT.isInteger()) {
1288 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1289 SDValue DeclareParamOps[] = { Chain,
1290 DAG.getConstant(paramCount, dl, MVT::i32),
1291 DAG.getConstant(sz, dl, MVT::i32),
1292 DAG.getConstant(0, dl, MVT::i32), InFlag };
1293 Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
1295 InFlag = Chain.getValue(1);
1296 SDValue OutV = OutVals[OIdx];
1298 // zext/sext i1 to i16
1299 unsigned opc = ISD::ZERO_EXTEND;
1300 if (Outs[OIdx].Flags.isSExt())
1301 opc = ISD::SIGN_EXTEND;
1302 OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
1304 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1305 SDValue CopyParamOps[] = { Chain,
1306 DAG.getConstant(paramCount, dl, MVT::i32),
1307 DAG.getConstant(0, dl, MVT::i32), OutV,
1310 unsigned opcode = NVPTXISD::StoreParam;
1311 if (Outs[OIdx].Flags.isZExt())
1312 opcode = NVPTXISD::StoreParamU32;
1313 else if (Outs[OIdx].Flags.isSExt())
1314 opcode = NVPTXISD::StoreParamS32;
1315 Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps,
1316 VT, MachinePointerInfo());
1318 InFlag = Chain.getValue(1);
1323 SmallVector<EVT, 16> vtparts;
1324 SmallVector<uint64_t, 16> Offsets;
1325 auto *PTy = dyn_cast<PointerType>(Args[i].Ty);
1326 assert(PTy && "Type of a byval parameter should be pointer");
1327 ComputePTXValueVTs(*this, DAG.getDataLayout(), PTy->getElementType(),
1328 vtparts, &Offsets, 0);
1330 // declare .param .align <align> .b8 .param<n>[<size>];
1331 unsigned sz = Outs[OIdx].Flags.getByValSize();
1332 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1333 unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
1334 // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
1335 // so we don't need to worry about natural alignment or not.
1336 // See TargetLowering::LowerCallTo().
1337 SDValue DeclareParamOps[] = {
1338 Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), dl, MVT::i32),
1339 DAG.getConstant(paramCount, dl, MVT::i32),
1340 DAG.getConstant(sz, dl, MVT::i32), InFlag
1342 Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1344 InFlag = Chain.getValue(1);
1345 for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1346 EVT elemtype = vtparts[j];
1347 int curOffset = Offsets[j];
1348 unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset);
1349 auto PtrVT = getPointerTy(DAG.getDataLayout());
1350 SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, OutVals[OIdx],
1351 DAG.getConstant(curOffset, dl, PtrVT));
1352 SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
1353 MachinePointerInfo(), false, false, false,
1355 if (elemtype.getSizeInBits() < 16) {
1356 theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
1358 SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1359 SDValue CopyParamOps[] = { Chain,
1360 DAG.getConstant(paramCount, dl, MVT::i32),
1361 DAG.getConstant(curOffset, dl, MVT::i32),
1363 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
1364 CopyParamOps, elemtype,
1365 MachinePointerInfo());
1367 InFlag = Chain.getValue(1);
1372 GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
1373 unsigned retAlignment = 0;
1376 if (Ins.size() > 0) {
1377 SmallVector<EVT, 16> resvtparts;
1378 ComputeValueVTs(*this, DL, retTy, resvtparts);
1381 // .param .align 16 .b8 retval0[<size-in-bytes>], or
1382 // .param .b<size-in-bits> retval0
1383 unsigned resultsz = DL.getTypeAllocSizeInBits(retTy);
1384 // Emit ".param .b<size-in-bits> retval0" instead of byte arrays only for
1385 // these three types to match the logic in
1386 // NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
1387 // Plus, this behavior is consistent with nvcc's.
1388 if (retTy->isFloatingPointTy() || retTy->isIntegerTy() ||
1389 retTy->isPointerTy()) {
1390 // Scalar needs to be at least 32bit wide
1393 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1394 SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1395 DAG.getConstant(resultsz, dl, MVT::i32),
1396 DAG.getConstant(0, dl, MVT::i32), InFlag };
1397 Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
1399 InFlag = Chain.getValue(1);
1401 retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
1402 SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1403 SDValue DeclareRetOps[] = { Chain,
1404 DAG.getConstant(retAlignment, dl, MVT::i32),
1405 DAG.getConstant(resultsz / 8, dl, MVT::i32),
1406 DAG.getConstant(0, dl, MVT::i32), InFlag };
1407 Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
1409 InFlag = Chain.getValue(1);
1414 // This is indirect function call case : PTX requires a prototype of the
1416 // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
1417 // to be emitted, and the label has to used as the last arg of call
1419 // The prototype is embedded in a string and put as the operand for a
1420 // CallPrototype SDNode which will print out to the value of the string.
1421 SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1423 getPrototype(DAG.getDataLayout(), retTy, Args, Outs, retAlignment, CS);
1424 const char *ProtoStr =
1425 nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
1426 SDValue ProtoOps[] = {
1427 Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
1429 Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
1430 InFlag = Chain.getValue(1);
1432 // Op to just print "call"
1433 SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1434 SDValue PrintCallOps[] = {
1435 Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, dl, MVT::i32), InFlag
1437 Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
1438 dl, PrintCallVTs, PrintCallOps);
1439 InFlag = Chain.getValue(1);
1441 // Ops to print out the function name
1442 SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1443 SDValue CallVoidOps[] = { Chain, Callee, InFlag };
1444 Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
1445 InFlag = Chain.getValue(1);
1447 // Ops to print out the param list
1448 SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1449 SDValue CallArgBeginOps[] = { Chain, InFlag };
1450 Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
1452 InFlag = Chain.getValue(1);
1454 for (unsigned i = 0, e = paramCount; i != e; ++i) {
1457 opcode = NVPTXISD::LastCallArg;
1459 opcode = NVPTXISD::CallArg;
1460 SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1461 SDValue CallArgOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1462 DAG.getConstant(i, dl, MVT::i32), InFlag };
1463 Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
1464 InFlag = Chain.getValue(1);
1466 SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1467 SDValue CallArgEndOps[] = { Chain,
1468 DAG.getConstant(Func ? 1 : 0, dl, MVT::i32),
1470 Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
1471 InFlag = Chain.getValue(1);
1474 SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1475 SDValue PrototypeOps[] = { Chain,
1476 DAG.getConstant(uniqueCallSite, dl, MVT::i32),
1478 Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
1479 InFlag = Chain.getValue(1);
1482 // Generate loads from param memory/moves from registers for result
1483 if (Ins.size() > 0) {
1484 if (retTy && retTy->isVectorTy()) {
1485 EVT ObjectVT = getValueType(DL, retTy);
1486 unsigned NumElts = ObjectVT.getVectorNumElements();
1487 EVT EltVT = ObjectVT.getVectorElementType();
1488 assert(STI.getTargetLowering()->getNumRegisters(F->getContext(),
1489 ObjectVT) == NumElts &&
1490 "Vector was not scalarized");
1491 unsigned sz = EltVT.getSizeInBits();
1492 bool needTruncate = sz < 8;
1495 // Just a simple load
1496 SmallVector<EVT, 4> LoadRetVTs;
1497 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1498 // If loading i1/i8 result, generate
1502 LoadRetVTs.push_back(MVT::i16);
1504 LoadRetVTs.push_back(EltVT);
1505 LoadRetVTs.push_back(MVT::Other);
1506 LoadRetVTs.push_back(MVT::Glue);
1507 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1508 DAG.getConstant(0, dl, MVT::i32), InFlag};
1509 SDValue retval = DAG.getMemIntrinsicNode(
1510 NVPTXISD::LoadParam, dl,
1511 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
1512 Chain = retval.getValue(1);
1513 InFlag = retval.getValue(2);
1514 SDValue Ret0 = retval;
1516 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0);
1517 InVals.push_back(Ret0);
1518 } else if (NumElts == 2) {
1520 SmallVector<EVT, 4> LoadRetVTs;
1521 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1522 // If loading i1/i8 result, generate
1526 LoadRetVTs.push_back(MVT::i16);
1527 LoadRetVTs.push_back(MVT::i16);
1529 LoadRetVTs.push_back(EltVT);
1530 LoadRetVTs.push_back(EltVT);
1532 LoadRetVTs.push_back(MVT::Other);
1533 LoadRetVTs.push_back(MVT::Glue);
1534 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1535 DAG.getConstant(0, dl, MVT::i32), InFlag};
1536 SDValue retval = DAG.getMemIntrinsicNode(
1537 NVPTXISD::LoadParamV2, dl,
1538 DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
1539 Chain = retval.getValue(2);
1540 InFlag = retval.getValue(3);
1541 SDValue Ret0 = retval.getValue(0);
1542 SDValue Ret1 = retval.getValue(1);
1544 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0);
1545 InVals.push_back(Ret0);
1546 Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1);
1547 InVals.push_back(Ret1);
1549 InVals.push_back(Ret0);
1550 InVals.push_back(Ret1);
1553 // Split into N LoadV4
1555 unsigned VecSize = 4;
1556 unsigned Opc = NVPTXISD::LoadParamV4;
1557 if (EltVT.getSizeInBits() == 64) {
1559 Opc = NVPTXISD::LoadParamV2;
1561 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1562 for (unsigned i = 0; i < NumElts; i += VecSize) {
1563 SmallVector<EVT, 8> LoadRetVTs;
1564 if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1565 // If loading i1/i8 result, generate
1569 for (unsigned j = 0; j < VecSize; ++j)
1570 LoadRetVTs.push_back(MVT::i16);
1572 for (unsigned j = 0; j < VecSize; ++j)
1573 LoadRetVTs.push_back(EltVT);
1575 LoadRetVTs.push_back(MVT::Other);
1576 LoadRetVTs.push_back(MVT::Glue);
1577 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1578 DAG.getConstant(Ofst, dl, MVT::i32), InFlag};
1579 SDValue retval = DAG.getMemIntrinsicNode(
1580 Opc, dl, DAG.getVTList(LoadRetVTs),
1581 LoadRetOps, EltVT, MachinePointerInfo());
1583 Chain = retval.getValue(2);
1584 InFlag = retval.getValue(3);
1586 Chain = retval.getValue(4);
1587 InFlag = retval.getValue(5);
1590 for (unsigned j = 0; j < VecSize; ++j) {
1591 if (i + j >= NumElts)
1593 SDValue Elt = retval.getValue(j);
1595 Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
1596 InVals.push_back(Elt);
1598 Ofst += DL.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1602 SmallVector<EVT, 16> VTs;
1603 SmallVector<uint64_t, 16> Offsets;
1604 ComputePTXValueVTs(*this, DAG.getDataLayout(), retTy, VTs, &Offsets, 0);
1605 assert(VTs.size() == Ins.size() && "Bad value decomposition");
1606 unsigned RetAlign = getArgumentAlignment(Callee, CS, retTy, 0);
1607 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
1608 unsigned sz = VTs[i].getSizeInBits();
1609 unsigned AlignI = GreatestCommonDivisor64(RetAlign, Offsets[i]);
1610 bool needTruncate = sz < 8;
1611 if (VTs[i].isInteger() && (sz < 8))
1614 SmallVector<EVT, 4> LoadRetVTs;
1615 EVT TheLoadType = VTs[i];
1616 if (retTy->isIntegerTy() && DL.getTypeAllocSizeInBits(retTy) < 32) {
1617 // This is for integer types only, and specifically not for
1619 LoadRetVTs.push_back(MVT::i32);
1620 TheLoadType = MVT::i32;
1621 } else if (sz < 16) {
1622 // If loading i1/i8 result, generate
1624 // trunc i16 to i1/i8
1625 LoadRetVTs.push_back(MVT::i16);
1627 LoadRetVTs.push_back(Ins[i].VT);
1628 LoadRetVTs.push_back(MVT::Other);
1629 LoadRetVTs.push_back(MVT::Glue);
1631 SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1632 DAG.getConstant(Offsets[i], dl, MVT::i32),
1634 SDValue retval = DAG.getMemIntrinsicNode(
1635 NVPTXISD::LoadParam, dl,
1636 DAG.getVTList(LoadRetVTs), LoadRetOps,
1637 TheLoadType, MachinePointerInfo(), AlignI);
1638 Chain = retval.getValue(1);
1639 InFlag = retval.getValue(2);
1640 SDValue Ret0 = retval.getValue(0);
1642 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
1643 InVals.push_back(Ret0);
1648 Chain = DAG.getCALLSEQ_END(Chain,
1649 DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1650 DAG.getIntPtrConstant(uniqueCallSite + 1, dl,
1655 // set isTailCall to false for now, until we figure out how to express
1656 // tail call optimization in PTX
1661 // By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
1662 // (see LegalizeDAG.cpp). This is slow and uses local memory.
1663 // We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
1665 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
1666 SDNode *Node = Op.getNode();
1668 SmallVector<SDValue, 8> Ops;
1669 unsigned NumOperands = Node->getNumOperands();
1670 for (unsigned i = 0; i < NumOperands; ++i) {
1671 SDValue SubOp = Node->getOperand(i);
1672 EVT VVT = SubOp.getNode()->getValueType(0);
1673 EVT EltVT = VVT.getVectorElementType();
1674 unsigned NumSubElem = VVT.getVectorNumElements();
1675 for (unsigned j = 0; j < NumSubElem; ++j) {
1676 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1677 DAG.getIntPtrConstant(j, dl)));
1680 return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
1683 /// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
1684 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1686 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1688 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
1689 SelectionDAG &DAG) const {
1690 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1691 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
1693 EVT VT = Op.getValueType();
1694 unsigned VTBits = VT.getSizeInBits();
1696 SDValue ShOpLo = Op.getOperand(0);
1697 SDValue ShOpHi = Op.getOperand(1);
1698 SDValue ShAmt = Op.getOperand(2);
1699 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
1701 if (VTBits == 32 && STI.getSmVersion() >= 35) {
1703 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1704 // {dHi, dLo} = {aHi, aLo} >> Amt
1706 // dLo = shf.r.clamp aLo, aHi, Amt
1708 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1709 SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
1712 SDValue Ops[2] = { Lo, Hi };
1713 return DAG.getMergeValues(Ops, dl);
1717 // {dHi, dLo} = {aHi, aLo} >> Amt
1718 // - if (Amt>=size) then
1719 // dLo = aHi >> (Amt-size)
1720 // dHi = aHi >> Amt (this is either all 0 or all 1)
1722 // dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
1725 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1726 DAG.getConstant(VTBits, dl, MVT::i32),
1728 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
1729 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1730 DAG.getConstant(VTBits, dl, MVT::i32));
1731 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
1732 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1733 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
1735 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1736 DAG.getConstant(VTBits, dl, MVT::i32),
1738 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1739 SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1741 SDValue Ops[2] = { Lo, Hi };
1742 return DAG.getMergeValues(Ops, dl);
1746 /// LowerShiftLeftParts - Lower SHL_PARTS, which
1747 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1749 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1751 SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
1752 SelectionDAG &DAG) const {
1753 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1754 assert(Op.getOpcode() == ISD::SHL_PARTS);
1756 EVT VT = Op.getValueType();
1757 unsigned VTBits = VT.getSizeInBits();
1759 SDValue ShOpLo = Op.getOperand(0);
1760 SDValue ShOpHi = Op.getOperand(1);
1761 SDValue ShAmt = Op.getOperand(2);
1763 if (VTBits == 32 && STI.getSmVersion() >= 35) {
1765 // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1766 // {dHi, dLo} = {aHi, aLo} << Amt
1767 // dHi = shf.l.clamp aLo, aHi, Amt
1770 SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
1772 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1774 SDValue Ops[2] = { Lo, Hi };
1775 return DAG.getMergeValues(Ops, dl);
1779 // {dHi, dLo} = {aHi, aLo} << Amt
1780 // - if (Amt>=size) then
1781 // dLo = aLo << Amt (all 0)
1782 // dLo = aLo << (Amt-size)
1785 // dHi = (aHi << Amt) | (aLo >> (size-Amt))
1787 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1788 DAG.getConstant(VTBits, dl, MVT::i32),
1790 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1791 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1792 DAG.getConstant(VTBits, dl, MVT::i32));
1793 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1794 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1795 SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1797 SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1798 DAG.getConstant(VTBits, dl, MVT::i32),
1800 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1801 SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1803 SDValue Ops[2] = { Lo, Hi };
1804 return DAG.getMergeValues(Ops, dl);
1809 NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1810 switch (Op.getOpcode()) {
1811 case ISD::RETURNADDR:
1813 case ISD::FRAMEADDR:
1815 case ISD::GlobalAddress:
1816 return LowerGlobalAddress(Op, DAG);
1817 case ISD::INTRINSIC_W_CHAIN:
1819 case ISD::BUILD_VECTOR:
1820 case ISD::EXTRACT_SUBVECTOR:
1822 case ISD::CONCAT_VECTORS:
1823 return LowerCONCAT_VECTORS(Op, DAG);
1825 return LowerSTORE(Op, DAG);
1827 return LowerLOAD(Op, DAG);
1828 case ISD::SHL_PARTS:
1829 return LowerShiftLeftParts(Op, DAG);
1830 case ISD::SRA_PARTS:
1831 case ISD::SRL_PARTS:
1832 return LowerShiftRightParts(Op, DAG);
1834 return LowerSelect(Op, DAG);
1836 llvm_unreachable("Custom lowering not defined for operation");
1840 SDValue NVPTXTargetLowering::LowerSelect(SDValue Op, SelectionDAG &DAG) const {
1841 SDValue Op0 = Op->getOperand(0);
1842 SDValue Op1 = Op->getOperand(1);
1843 SDValue Op2 = Op->getOperand(2);
1844 SDLoc DL(Op.getNode());
1846 assert(Op.getValueType() == MVT::i1 && "Custom lowering enabled only for i1");
1848 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
1849 Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2);
1850 SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2);
1851 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select);
1856 SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1857 if (Op.getValueType() == MVT::i1)
1858 return LowerLOADi1(Op, DAG);
1865 // v1 = ld i8* addr (-> i16)
1866 // v = trunc i16 to i1
1867 SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
1868 SDNode *Node = Op.getNode();
1869 LoadSDNode *LD = cast<LoadSDNode>(Node);
1871 assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
1872 assert(Node->getValueType(0) == MVT::i1 &&
1873 "Custom lowering for i1 load only");
1875 DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
1876 LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(),
1877 LD->isInvariant(), LD->getAlignment());
1878 SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
1879 // The legalizer (the caller) is expecting two values from the legalized
1880 // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
1881 // in LegalizeDAG.cpp which also uses MergeValues.
1882 SDValue Ops[] = { result, LD->getChain() };
1883 return DAG.getMergeValues(Ops, dl);
1886 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1887 EVT ValVT = Op.getOperand(1).getValueType();
1888 if (ValVT == MVT::i1)
1889 return LowerSTOREi1(Op, DAG);
1890 else if (ValVT.isVector())
1891 return LowerSTOREVector(Op, DAG);
1897 NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
1898 SDNode *N = Op.getNode();
1899 SDValue Val = N->getOperand(1);
1901 EVT ValVT = Val.getValueType();
1903 if (ValVT.isVector()) {
1904 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
1905 // legal. We can (and should) split that into 2 stores of <2 x double> here
1906 // but I'm leaving that as a TODO for now.
1907 if (!ValVT.isSimple())
1909 switch (ValVT.getSimpleVT().SimpleTy) {
1922 // This is a "native" vector type
1926 MemSDNode *MemSD = cast<MemSDNode>(N);
1927 const DataLayout &TD = DAG.getDataLayout();
1929 unsigned Align = MemSD->getAlignment();
1930 unsigned PrefAlign =
1931 TD.getPrefTypeAlignment(ValVT.getTypeForEVT(*DAG.getContext()));
1932 if (Align < PrefAlign) {
1933 // This store is not sufficiently aligned, so bail out and let this vector
1934 // store be scalarized. Note that we may still be able to emit smaller
1935 // vector stores. For example, if we are storing a <4 x float> with an
1936 // alignment of 8, this check will fail but the legalizer will try again
1937 // with 2 x <2 x float>, which will succeed with an alignment of 8.
1941 unsigned Opcode = 0;
1942 EVT EltVT = ValVT.getVectorElementType();
1943 unsigned NumElts = ValVT.getVectorNumElements();
1945 // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
1946 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
1947 // stored type to i16 and propagate the "real" type as the memory type.
1948 bool NeedExt = false;
1949 if (EltVT.getSizeInBits() < 16)
1956 Opcode = NVPTXISD::StoreV2;
1959 Opcode = NVPTXISD::StoreV4;
1964 SmallVector<SDValue, 8> Ops;
1966 // First is the chain
1967 Ops.push_back(N->getOperand(0));
1969 // Then the split values
1970 for (unsigned i = 0; i < NumElts; ++i) {
1971 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
1972 DAG.getIntPtrConstant(i, DL));
1974 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
1975 Ops.push_back(ExtVal);
1978 // Then any remaining arguments
1979 Ops.append(N->op_begin() + 2, N->op_end());
1981 SDValue NewSt = DAG.getMemIntrinsicNode(
1982 Opcode, DL, DAG.getVTList(MVT::Other), Ops,
1983 MemSD->getMemoryVT(), MemSD->getMemOperand());
1985 //return DCI.CombineTo(N, NewSt, true);
1994 // v1 = zxt v to i16
1996 SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
1997 SDNode *Node = Op.getNode();
1999 StoreSDNode *ST = cast<StoreSDNode>(Node);
2000 SDValue Tmp1 = ST->getChain();
2001 SDValue Tmp2 = ST->getBasePtr();
2002 SDValue Tmp3 = ST->getValue();
2003 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
2004 unsigned Alignment = ST->getAlignment();
2005 bool isVolatile = ST->isVolatile();
2006 bool isNonTemporal = ST->isNonTemporal();
2007 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
2008 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
2009 ST->getPointerInfo(), MVT::i8, isNonTemporal,
2010 isVolatile, Alignment);
2014 SDValue NVPTXTargetLowering::getExtSymb(SelectionDAG &DAG, const char *inname,
2015 int idx, EVT v) const {
2016 std::string *name = nvTM->getManagedStrPool()->getManagedString(inname);
2017 std::stringstream suffix;
2019 *name += suffix.str();
2020 return DAG.getTargetExternalSymbol(name->c_str(), v);
2024 NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
2025 std::string ParamSym;
2026 raw_string_ostream ParamStr(ParamSym);
2028 ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
2031 std::string *SavedStr =
2032 nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
2033 return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
2036 SDValue NVPTXTargetLowering::getParamHelpSymbol(SelectionDAG &DAG, int idx) {
2037 return getExtSymb(DAG, ".HLPPARAM", idx);
2040 // Check to see if the kernel argument is image*_t or sampler_t
2042 bool llvm::isImageOrSamplerVal(const Value *arg, const Module *context) {
2043 static const char *const specialTypes[] = { "struct._image2d_t",
2044 "struct._image3d_t",
2045 "struct._sampler_t" };
2047 Type *Ty = arg->getType();
2048 auto *PTy = dyn_cast<PointerType>(Ty);
2056 auto *STy = dyn_cast<StructType>(PTy->getElementType());
2057 const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : "";
2059 for (int i = 0, e = array_lengthof(specialTypes); i != e; ++i)
2060 if (TypeName == specialTypes[i])
2066 SDValue NVPTXTargetLowering::LowerFormalArguments(
2067 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2068 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2069 SmallVectorImpl<SDValue> &InVals) const {
2070 MachineFunction &MF = DAG.getMachineFunction();
2071 const DataLayout &DL = DAG.getDataLayout();
2072 auto PtrVT = getPointerTy(DAG.getDataLayout());
2074 const Function *F = MF.getFunction();
2075 const AttributeSet &PAL = F->getAttributes();
2076 const TargetLowering *TLI = STI.getTargetLowering();
2078 SDValue Root = DAG.getRoot();
2079 std::vector<SDValue> OutChains;
2081 bool isKernel = llvm::isKernelFunction(*F);
2082 bool isABI = (STI.getSmVersion() >= 20);
2083 assert(isABI && "Non-ABI compilation is not supported");
2087 std::vector<Type *> argTypes;
2088 std::vector<const Argument *> theArgs;
2089 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
2091 theArgs.push_back(I);
2092 argTypes.push_back(I->getType());
2094 // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
2095 // Ins.size() will be larger
2096 // * if there is an aggregate argument with multiple fields (each field
2097 // showing up separately in Ins)
2098 // * if there is a vector argument with more than typical vector-length
2099 // elements (generally if more than 4) where each vector element is
2100 // individually present in Ins.
2101 // So a different index should be used for indexing into Ins.
2102 // See similar issue in LowerCall.
2103 unsigned InsIdx = 0;
2106 for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
2107 Type *Ty = argTypes[i];
2109 // If the kernel argument is image*_t or sampler_t, convert it to
2110 // a i32 constant holding the parameter position. This can later
2111 // matched in the AsmPrinter to output the correct mangled name.
2112 if (isImageOrSamplerVal(
2114 (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
2116 assert(isKernel && "Only kernels can have image/sampler params");
2117 InVals.push_back(DAG.getConstant(i + 1, dl, MVT::i32));
2121 if (theArgs[i]->use_empty()) {
2123 if (Ty->isAggregateType()) {
2124 SmallVector<EVT, 16> vtparts;
2126 ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts);
2127 assert(vtparts.size() > 0 && "empty aggregate type not expected");
2128 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2130 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2133 if (vtparts.size() > 0)
2137 if (Ty->isVectorTy()) {
2138 EVT ObjectVT = getValueType(DL, Ty);
2139 unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
2140 for (unsigned parti = 0; parti < NumRegs; ++parti) {
2141 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2148 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2152 // In the following cases, assign a node order of "idx+1"
2153 // to newly created nodes. The SDNodes for params have to
2154 // appear in the same order as their order of appearance
2155 // in the original function. "idx+1" holds that order.
2156 if (!PAL.hasAttribute(i + 1, Attribute::ByVal)) {
2157 if (Ty->isAggregateType()) {
2158 SmallVector<EVT, 16> vtparts;
2159 SmallVector<uint64_t, 16> offsets;
2161 // NOTE: Here, we lose the ability to issue vector loads for vectors
2162 // that are a part of a struct. This should be investigated in the
2164 ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts, &offsets,
2166 assert(vtparts.size() > 0 && "empty aggregate type not expected");
2167 bool aggregateIsPacked = false;
2168 if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
2169 aggregateIsPacked = STy->isPacked();
2171 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2172 for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2174 EVT partVT = vtparts[parti];
2175 Value *srcValue = Constant::getNullValue(
2176 PointerType::get(partVT.getTypeForEVT(F->getContext()),
2177 llvm::ADDRESS_SPACE_PARAM));
2179 DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
2180 DAG.getConstant(offsets[parti], dl, PtrVT));
2181 unsigned partAlign = aggregateIsPacked
2183 : DL.getABITypeAlignment(
2184 partVT.getTypeForEVT(F->getContext()));
2186 if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
2187 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
2188 ISD::SEXTLOAD : ISD::ZEXTLOAD;
2189 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
2190 MachinePointerInfo(srcValue), partVT, false,
2191 false, false, partAlign);
2193 p = DAG.getLoad(partVT, dl, Root, srcAddr,
2194 MachinePointerInfo(srcValue), false, false, false,
2198 p.getNode()->setIROrder(idx + 1);
2199 InVals.push_back(p);
2202 if (vtparts.size() > 0)
2206 if (Ty->isVectorTy()) {
2207 EVT ObjectVT = getValueType(DL, Ty);
2208 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2209 unsigned NumElts = ObjectVT.getVectorNumElements();
2210 assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
2211 "Vector was not scalarized");
2212 EVT EltVT = ObjectVT.getVectorElementType();
2217 // We only have one element, so just directly load it
2218 Value *SrcValue = Constant::getNullValue(PointerType::get(
2219 EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2220 SDValue P = DAG.getLoad(
2221 EltVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false, false,
2223 DL.getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
2225 P.getNode()->setIROrder(idx + 1);
2227 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
2228 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
2229 InVals.push_back(P);
2231 } else if (NumElts == 2) {
2233 // f32,f32 = load ...
2234 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
2235 Value *SrcValue = Constant::getNullValue(PointerType::get(
2236 VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2237 SDValue P = DAG.getLoad(
2238 VecVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false, false,
2240 DL.getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
2242 P.getNode()->setIROrder(idx + 1);
2244 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2245 DAG.getIntPtrConstant(0, dl));
2246 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2247 DAG.getIntPtrConstant(1, dl));
2249 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
2250 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
2251 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
2254 InVals.push_back(Elt0);
2255 InVals.push_back(Elt1);
2259 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
2261 // vector will be expanded to a power of 2 elements, so we know we can
2262 // always round up to the next multiple of 4 when creating the vector
2264 // e.g. 4 elem => 1 ld.v4
2265 // 6 elem => 2 ld.v4
2266 // 8 elem => 2 ld.v4
2267 // 11 elem => 3 ld.v4
2268 unsigned VecSize = 4;
2269 if (EltVT.getSizeInBits() == 64) {
2272 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
2274 for (unsigned i = 0; i < NumElts; i += VecSize) {
2275 Value *SrcValue = Constant::getNullValue(
2276 PointerType::get(VecVT.getTypeForEVT(F->getContext()),
2277 llvm::ADDRESS_SPACE_PARAM));
2278 SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
2279 DAG.getConstant(Ofst, dl, PtrVT));
2280 SDValue P = DAG.getLoad(
2281 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
2283 DL.getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
2285 P.getNode()->setIROrder(idx + 1);
2287 for (unsigned j = 0; j < VecSize; ++j) {
2288 if (i + j >= NumElts)
2290 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2291 DAG.getIntPtrConstant(j, dl));
2292 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
2293 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
2294 InVals.push_back(Elt);
2296 Ofst += DL.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2306 EVT ObjectVT = getValueType(DL, Ty);
2307 // If ABI, load from the param symbol
2308 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2309 Value *srcValue = Constant::getNullValue(PointerType::get(
2310 ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2312 if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
2313 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
2314 ISD::SEXTLOAD : ISD::ZEXTLOAD;
2316 ExtOp, dl, Ins[InsIdx].VT, Root, Arg, MachinePointerInfo(srcValue),
2317 ObjectVT, false, false, false,
2318 DL.getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
2321 Ins[InsIdx].VT, dl, Root, Arg, MachinePointerInfo(srcValue), false,
2323 DL.getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
2326 p.getNode()->setIROrder(idx + 1);
2327 InVals.push_back(p);
2331 // Param has ByVal attribute
2332 // Return MoveParam(param symbol).
2333 // Ideally, the param symbol can be returned directly,
2334 // but when SDNode builder decides to use it in a CopyToReg(),
2335 // machine instruction fails because TargetExternalSymbol
2336 // (not lowered) is target dependent, and CopyToReg assumes
2337 // the source is lowered.
2338 EVT ObjectVT = getValueType(DL, Ty);
2339 assert(ObjectVT == Ins[InsIdx].VT &&
2340 "Ins type did not match function type");
2341 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2342 SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
2344 p.getNode()->setIROrder(idx + 1);
2346 InVals.push_back(p);
2348 SDValue p2 = DAG.getNode(
2349 ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
2350 DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, dl, MVT::i32), p);
2351 InVals.push_back(p2);
2355 // Clang will check explicit VarArg and issue error if any. However, Clang
2356 // will let code with
2357 // implicit var arg like f() pass. See bug 617733.
2358 // We treat this case as if the arg list is empty.
2359 // if (F.isVarArg()) {
2360 // assert(0 && "VarArg not supported yet!");
2363 if (!OutChains.empty())
2364 DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
2371 NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2373 const SmallVectorImpl<ISD::OutputArg> &Outs,
2374 const SmallVectorImpl<SDValue> &OutVals,
2375 SDLoc dl, SelectionDAG &DAG) const {
2376 MachineFunction &MF = DAG.getMachineFunction();
2377 const Function *F = MF.getFunction();
2378 Type *RetTy = F->getReturnType();
2379 const DataLayout &TD = DAG.getDataLayout();
2381 bool isABI = (STI.getSmVersion() >= 20);
2382 assert(isABI && "Non-ABI compilation is not supported");
2386 if (VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
2387 // If we have a vector type, the OutVals array will be the scalarized
2388 // components and we have combine them into 1 or more vector stores.
2389 unsigned NumElts = VTy->getNumElements();
2390 assert(NumElts == Outs.size() && "Bad scalarization of return value");
2392 // const_cast can be removed in later LLVM versions
2393 EVT EltVT = getValueType(TD, RetTy).getVectorElementType();
2394 bool NeedExtend = false;
2395 if (EltVT.getSizeInBits() < 16)
2400 SDValue StoreVal = OutVals[0];
2401 // We only have one element, so just directly store it
2403 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
2404 SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal };
2405 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
2406 DAG.getVTList(MVT::Other), Ops,
2407 EltVT, MachinePointerInfo());
2409 } else if (NumElts == 2) {
2411 SDValue StoreVal0 = OutVals[0];
2412 SDValue StoreVal1 = OutVals[1];
2415 StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal0);
2416 StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
2419 SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal0,
2421 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
2422 DAG.getVTList(MVT::Other), Ops,
2423 EltVT, MachinePointerInfo());
2426 // We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
2427 // vector will be expanded to a power of 2 elements, so we know we can
2428 // always round up to the next multiple of 4 when creating the vector
2430 // e.g. 4 elem => 1 st.v4
2431 // 6 elem => 2 st.v4
2432 // 8 elem => 2 st.v4
2433 // 11 elem => 3 st.v4
2435 unsigned VecSize = 4;
2436 if (OutVals[0].getValueType().getSizeInBits() == 64)
2439 unsigned Offset = 0;
2442 EVT::getVectorVT(F->getContext(), EltVT, VecSize);
2443 unsigned PerStoreOffset =
2444 TD.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2446 for (unsigned i = 0; i < NumElts; i += VecSize) {
2449 SmallVector<SDValue, 8> Ops;
2450 Ops.push_back(Chain);
2451 Ops.push_back(DAG.getConstant(Offset, dl, MVT::i32));
2452 unsigned Opc = NVPTXISD::StoreRetvalV2;
2453 EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
2455 StoreVal = OutVals[i];
2457 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2458 Ops.push_back(StoreVal);
2460 if (i + 1 < NumElts) {
2461 StoreVal = OutVals[i + 1];
2463 StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2465 StoreVal = DAG.getUNDEF(ExtendedVT);
2467 Ops.push_back(StoreVal);
2470 Opc = NVPTXISD::StoreRetvalV4;
2471 if (i + 2 < NumElts) {
2472 StoreVal = OutVals[i + 2];
2475 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2477 StoreVal = DAG.getUNDEF(ExtendedVT);
2479 Ops.push_back(StoreVal);
2481 if (i + 3 < NumElts) {
2482 StoreVal = OutVals[i + 3];
2485 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2487 StoreVal = DAG.getUNDEF(ExtendedVT);
2489 Ops.push_back(StoreVal);
2492 // Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
2494 DAG.getMemIntrinsicNode(Opc, dl, DAG.getVTList(MVT::Other), Ops,
2495 EltVT, MachinePointerInfo());
2496 Offset += PerStoreOffset;
2500 SmallVector<EVT, 16> ValVTs;
2501 SmallVector<uint64_t, 16> Offsets;
2502 ComputePTXValueVTs(*this, DAG.getDataLayout(), RetTy, ValVTs, &Offsets, 0);
2503 assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
2505 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
2506 SDValue theVal = OutVals[i];
2507 EVT TheValType = theVal.getValueType();
2508 unsigned numElems = 1;
2509 if (TheValType.isVector())
2510 numElems = TheValType.getVectorNumElements();
2511 for (unsigned j = 0, je = numElems; j != je; ++j) {
2512 SDValue TmpVal = theVal;
2513 if (TheValType.isVector())
2514 TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2515 TheValType.getVectorElementType(), TmpVal,
2516 DAG.getIntPtrConstant(j, dl));
2517 EVT TheStoreType = ValVTs[i];
2518 if (RetTy->isIntegerTy() && TD.getTypeAllocSizeInBits(RetTy) < 32) {
2519 // The following zero-extension is for integer types only, and
2520 // specifically not for aggregates.
2521 TmpVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, TmpVal);
2522 TheStoreType = MVT::i32;
2524 else if (TmpVal.getValueType().getSizeInBits() < 16)
2525 TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal);
2529 DAG.getConstant(Offsets[i], dl, MVT::i32),
2531 Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
2532 DAG.getVTList(MVT::Other), Ops,
2534 MachinePointerInfo());
2539 return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
2543 void NVPTXTargetLowering::LowerAsmOperandForConstraint(
2544 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2545 SelectionDAG &DAG) const {
2546 if (Constraint.length() > 1)
2549 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2552 // NVPTX suuport vector of legal types of any length in Intrinsics because the
2553 // NVPTX specific type legalizer
2554 // will legalize them to the PTX supported length.
2555 bool NVPTXTargetLowering::isTypeSupportedInIntrinsic(MVT VT) const {
2556 if (isTypeLegal(VT))
2558 if (VT.isVector()) {
2559 MVT eVT = VT.getVectorElementType();
2560 if (isTypeLegal(eVT))
2566 static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2567 switch (Intrinsic) {
2571 case Intrinsic::nvvm_tex_1d_v4f32_s32:
2572 return NVPTXISD::Tex1DFloatS32;
2573 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2574 return NVPTXISD::Tex1DFloatFloat;
2575 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2576 return NVPTXISD::Tex1DFloatFloatLevel;
2577 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2578 return NVPTXISD::Tex1DFloatFloatGrad;
2579 case Intrinsic::nvvm_tex_1d_v4s32_s32:
2580 return NVPTXISD::Tex1DS32S32;
2581 case Intrinsic::nvvm_tex_1d_v4s32_f32:
2582 return NVPTXISD::Tex1DS32Float;
2583 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
2584 return NVPTXISD::Tex1DS32FloatLevel;
2585 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
2586 return NVPTXISD::Tex1DS32FloatGrad;
2587 case Intrinsic::nvvm_tex_1d_v4u32_s32:
2588 return NVPTXISD::Tex1DU32S32;
2589 case Intrinsic::nvvm_tex_1d_v4u32_f32:
2590 return NVPTXISD::Tex1DU32Float;
2591 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
2592 return NVPTXISD::Tex1DU32FloatLevel;
2593 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
2594 return NVPTXISD::Tex1DU32FloatGrad;
2596 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
2597 return NVPTXISD::Tex1DArrayFloatS32;
2598 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2599 return NVPTXISD::Tex1DArrayFloatFloat;
2600 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2601 return NVPTXISD::Tex1DArrayFloatFloatLevel;
2602 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2603 return NVPTXISD::Tex1DArrayFloatFloatGrad;
2604 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
2605 return NVPTXISD::Tex1DArrayS32S32;
2606 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
2607 return NVPTXISD::Tex1DArrayS32Float;
2608 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
2609 return NVPTXISD::Tex1DArrayS32FloatLevel;
2610 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
2611 return NVPTXISD::Tex1DArrayS32FloatGrad;
2612 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
2613 return NVPTXISD::Tex1DArrayU32S32;
2614 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
2615 return NVPTXISD::Tex1DArrayU32Float;
2616 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
2617 return NVPTXISD::Tex1DArrayU32FloatLevel;
2618 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
2619 return NVPTXISD::Tex1DArrayU32FloatGrad;
2621 case Intrinsic::nvvm_tex_2d_v4f32_s32:
2622 return NVPTXISD::Tex2DFloatS32;
2623 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2624 return NVPTXISD::Tex2DFloatFloat;
2625 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2626 return NVPTXISD::Tex2DFloatFloatLevel;
2627 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2628 return NVPTXISD::Tex2DFloatFloatGrad;
2629 case Intrinsic::nvvm_tex_2d_v4s32_s32:
2630 return NVPTXISD::Tex2DS32S32;
2631 case Intrinsic::nvvm_tex_2d_v4s32_f32:
2632 return NVPTXISD::Tex2DS32Float;
2633 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
2634 return NVPTXISD::Tex2DS32FloatLevel;
2635 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
2636 return NVPTXISD::Tex2DS32FloatGrad;
2637 case Intrinsic::nvvm_tex_2d_v4u32_s32:
2638 return NVPTXISD::Tex2DU32S32;
2639 case Intrinsic::nvvm_tex_2d_v4u32_f32:
2640 return NVPTXISD::Tex2DU32Float;
2641 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
2642 return NVPTXISD::Tex2DU32FloatLevel;
2643 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
2644 return NVPTXISD::Tex2DU32FloatGrad;
2646 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
2647 return NVPTXISD::Tex2DArrayFloatS32;
2648 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2649 return NVPTXISD::Tex2DArrayFloatFloat;
2650 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2651 return NVPTXISD::Tex2DArrayFloatFloatLevel;
2652 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2653 return NVPTXISD::Tex2DArrayFloatFloatGrad;
2654 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
2655 return NVPTXISD::Tex2DArrayS32S32;
2656 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
2657 return NVPTXISD::Tex2DArrayS32Float;
2658 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
2659 return NVPTXISD::Tex2DArrayS32FloatLevel;
2660 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
2661 return NVPTXISD::Tex2DArrayS32FloatGrad;
2662 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
2663 return NVPTXISD::Tex2DArrayU32S32;
2664 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
2665 return NVPTXISD::Tex2DArrayU32Float;
2666 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
2667 return NVPTXISD::Tex2DArrayU32FloatLevel;
2668 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
2669 return NVPTXISD::Tex2DArrayU32FloatGrad;
2671 case Intrinsic::nvvm_tex_3d_v4f32_s32:
2672 return NVPTXISD::Tex3DFloatS32;
2673 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2674 return NVPTXISD::Tex3DFloatFloat;
2675 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2676 return NVPTXISD::Tex3DFloatFloatLevel;
2677 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2678 return NVPTXISD::Tex3DFloatFloatGrad;
2679 case Intrinsic::nvvm_tex_3d_v4s32_s32:
2680 return NVPTXISD::Tex3DS32S32;
2681 case Intrinsic::nvvm_tex_3d_v4s32_f32:
2682 return NVPTXISD::Tex3DS32Float;
2683 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
2684 return NVPTXISD::Tex3DS32FloatLevel;
2685 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
2686 return NVPTXISD::Tex3DS32FloatGrad;
2687 case Intrinsic::nvvm_tex_3d_v4u32_s32:
2688 return NVPTXISD::Tex3DU32S32;
2689 case Intrinsic::nvvm_tex_3d_v4u32_f32:
2690 return NVPTXISD::Tex3DU32Float;
2691 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
2692 return NVPTXISD::Tex3DU32FloatLevel;
2693 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
2694 return NVPTXISD::Tex3DU32FloatGrad;
2696 case Intrinsic::nvvm_tex_cube_v4f32_f32:
2697 return NVPTXISD::TexCubeFloatFloat;
2698 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
2699 return NVPTXISD::TexCubeFloatFloatLevel;
2700 case Intrinsic::nvvm_tex_cube_v4s32_f32:
2701 return NVPTXISD::TexCubeS32Float;
2702 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
2703 return NVPTXISD::TexCubeS32FloatLevel;
2704 case Intrinsic::nvvm_tex_cube_v4u32_f32:
2705 return NVPTXISD::TexCubeU32Float;
2706 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
2707 return NVPTXISD::TexCubeU32FloatLevel;
2709 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
2710 return NVPTXISD::TexCubeArrayFloatFloat;
2711 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
2712 return NVPTXISD::TexCubeArrayFloatFloatLevel;
2713 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
2714 return NVPTXISD::TexCubeArrayS32Float;
2715 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
2716 return NVPTXISD::TexCubeArrayS32FloatLevel;
2717 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
2718 return NVPTXISD::TexCubeArrayU32Float;
2719 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
2720 return NVPTXISD::TexCubeArrayU32FloatLevel;
2722 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
2723 return NVPTXISD::Tld4R2DFloatFloat;
2724 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
2725 return NVPTXISD::Tld4G2DFloatFloat;
2726 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
2727 return NVPTXISD::Tld4B2DFloatFloat;
2728 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
2729 return NVPTXISD::Tld4A2DFloatFloat;
2730 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
2731 return NVPTXISD::Tld4R2DS64Float;
2732 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
2733 return NVPTXISD::Tld4G2DS64Float;
2734 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
2735 return NVPTXISD::Tld4B2DS64Float;
2736 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
2737 return NVPTXISD::Tld4A2DS64Float;
2738 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
2739 return NVPTXISD::Tld4R2DU64Float;
2740 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
2741 return NVPTXISD::Tld4G2DU64Float;
2742 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
2743 return NVPTXISD::Tld4B2DU64Float;
2744 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
2745 return NVPTXISD::Tld4A2DU64Float;
2747 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
2748 return NVPTXISD::TexUnified1DFloatS32;
2749 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
2750 return NVPTXISD::TexUnified1DFloatFloat;
2751 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
2752 return NVPTXISD::TexUnified1DFloatFloatLevel;
2753 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
2754 return NVPTXISD::TexUnified1DFloatFloatGrad;
2755 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
2756 return NVPTXISD::TexUnified1DS32S32;
2757 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
2758 return NVPTXISD::TexUnified1DS32Float;
2759 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
2760 return NVPTXISD::TexUnified1DS32FloatLevel;
2761 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
2762 return NVPTXISD::TexUnified1DS32FloatGrad;
2763 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
2764 return NVPTXISD::TexUnified1DU32S32;
2765 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
2766 return NVPTXISD::TexUnified1DU32Float;
2767 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
2768 return NVPTXISD::TexUnified1DU32FloatLevel;
2769 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
2770 return NVPTXISD::TexUnified1DU32FloatGrad;
2772 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
2773 return NVPTXISD::TexUnified1DArrayFloatS32;
2774 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
2775 return NVPTXISD::TexUnified1DArrayFloatFloat;
2776 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
2777 return NVPTXISD::TexUnified1DArrayFloatFloatLevel;
2778 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
2779 return NVPTXISD::TexUnified1DArrayFloatFloatGrad;
2780 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
2781 return NVPTXISD::TexUnified1DArrayS32S32;
2782 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
2783 return NVPTXISD::TexUnified1DArrayS32Float;
2784 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
2785 return NVPTXISD::TexUnified1DArrayS32FloatLevel;
2786 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
2787 return NVPTXISD::TexUnified1DArrayS32FloatGrad;
2788 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
2789 return NVPTXISD::TexUnified1DArrayU32S32;
2790 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
2791 return NVPTXISD::TexUnified1DArrayU32Float;
2792 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
2793 return NVPTXISD::TexUnified1DArrayU32FloatLevel;
2794 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
2795 return NVPTXISD::TexUnified1DArrayU32FloatGrad;
2797 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
2798 return NVPTXISD::TexUnified2DFloatS32;
2799 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
2800 return NVPTXISD::TexUnified2DFloatFloat;
2801 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
2802 return NVPTXISD::TexUnified2DFloatFloatLevel;
2803 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
2804 return NVPTXISD::TexUnified2DFloatFloatGrad;
2805 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
2806 return NVPTXISD::TexUnified2DS32S32;
2807 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
2808 return NVPTXISD::TexUnified2DS32Float;
2809 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
2810 return NVPTXISD::TexUnified2DS32FloatLevel;
2811 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
2812 return NVPTXISD::TexUnified2DS32FloatGrad;
2813 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
2814 return NVPTXISD::TexUnified2DU32S32;
2815 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
2816 return NVPTXISD::TexUnified2DU32Float;
2817 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
2818 return NVPTXISD::TexUnified2DU32FloatLevel;
2819 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
2820 return NVPTXISD::TexUnified2DU32FloatGrad;
2822 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
2823 return NVPTXISD::TexUnified2DArrayFloatS32;
2824 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
2825 return NVPTXISD::TexUnified2DArrayFloatFloat;
2826 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
2827 return NVPTXISD::TexUnified2DArrayFloatFloatLevel;
2828 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
2829 return NVPTXISD::TexUnified2DArrayFloatFloatGrad;
2830 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
2831 return NVPTXISD::TexUnified2DArrayS32S32;
2832 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
2833 return NVPTXISD::TexUnified2DArrayS32Float;
2834 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
2835 return NVPTXISD::TexUnified2DArrayS32FloatLevel;
2836 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
2837 return NVPTXISD::TexUnified2DArrayS32FloatGrad;
2838 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
2839 return NVPTXISD::TexUnified2DArrayU32S32;
2840 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
2841 return NVPTXISD::TexUnified2DArrayU32Float;
2842 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
2843 return NVPTXISD::TexUnified2DArrayU32FloatLevel;
2844 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
2845 return NVPTXISD::TexUnified2DArrayU32FloatGrad;
2847 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
2848 return NVPTXISD::TexUnified3DFloatS32;
2849 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
2850 return NVPTXISD::TexUnified3DFloatFloat;
2851 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
2852 return NVPTXISD::TexUnified3DFloatFloatLevel;
2853 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
2854 return NVPTXISD::TexUnified3DFloatFloatGrad;
2855 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
2856 return NVPTXISD::TexUnified3DS32S32;
2857 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
2858 return NVPTXISD::TexUnified3DS32Float;
2859 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
2860 return NVPTXISD::TexUnified3DS32FloatLevel;
2861 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
2862 return NVPTXISD::TexUnified3DS32FloatGrad;
2863 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
2864 return NVPTXISD::TexUnified3DU32S32;
2865 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
2866 return NVPTXISD::TexUnified3DU32Float;
2867 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
2868 return NVPTXISD::TexUnified3DU32FloatLevel;
2869 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
2870 return NVPTXISD::TexUnified3DU32FloatGrad;
2872 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
2873 return NVPTXISD::TexUnifiedCubeFloatFloat;
2874 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
2875 return NVPTXISD::TexUnifiedCubeFloatFloatLevel;
2876 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
2877 return NVPTXISD::TexUnifiedCubeS32Float;
2878 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
2879 return NVPTXISD::TexUnifiedCubeS32FloatLevel;
2880 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
2881 return NVPTXISD::TexUnifiedCubeU32Float;
2882 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
2883 return NVPTXISD::TexUnifiedCubeU32FloatLevel;
2885 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
2886 return NVPTXISD::TexUnifiedCubeArrayFloatFloat;
2887 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
2888 return NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel;
2889 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
2890 return NVPTXISD::TexUnifiedCubeArrayS32Float;
2891 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
2892 return NVPTXISD::TexUnifiedCubeArrayS32FloatLevel;
2893 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
2894 return NVPTXISD::TexUnifiedCubeArrayU32Float;
2895 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
2896 return NVPTXISD::TexUnifiedCubeArrayU32FloatLevel;
2898 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
2899 return NVPTXISD::Tld4UnifiedR2DFloatFloat;
2900 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
2901 return NVPTXISD::Tld4UnifiedG2DFloatFloat;
2902 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
2903 return NVPTXISD::Tld4UnifiedB2DFloatFloat;
2904 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
2905 return NVPTXISD::Tld4UnifiedA2DFloatFloat;
2906 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
2907 return NVPTXISD::Tld4UnifiedR2DS64Float;
2908 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
2909 return NVPTXISD::Tld4UnifiedG2DS64Float;
2910 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
2911 return NVPTXISD::Tld4UnifiedB2DS64Float;
2912 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
2913 return NVPTXISD::Tld4UnifiedA2DS64Float;
2914 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
2915 return NVPTXISD::Tld4UnifiedR2DU64Float;
2916 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
2917 return NVPTXISD::Tld4UnifiedG2DU64Float;
2918 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
2919 return NVPTXISD::Tld4UnifiedB2DU64Float;
2920 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
2921 return NVPTXISD::Tld4UnifiedA2DU64Float;
2925 static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
2926 switch (Intrinsic) {
2929 case Intrinsic::nvvm_suld_1d_i8_clamp:
2930 return NVPTXISD::Suld1DI8Clamp;
2931 case Intrinsic::nvvm_suld_1d_i16_clamp:
2932 return NVPTXISD::Suld1DI16Clamp;
2933 case Intrinsic::nvvm_suld_1d_i32_clamp:
2934 return NVPTXISD::Suld1DI32Clamp;
2935 case Intrinsic::nvvm_suld_1d_i64_clamp:
2936 return NVPTXISD::Suld1DI64Clamp;
2937 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
2938 return NVPTXISD::Suld1DV2I8Clamp;
2939 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
2940 return NVPTXISD::Suld1DV2I16Clamp;
2941 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
2942 return NVPTXISD::Suld1DV2I32Clamp;
2943 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
2944 return NVPTXISD::Suld1DV2I64Clamp;
2945 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
2946 return NVPTXISD::Suld1DV4I8Clamp;
2947 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
2948 return NVPTXISD::Suld1DV4I16Clamp;
2949 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
2950 return NVPTXISD::Suld1DV4I32Clamp;
2951 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
2952 return NVPTXISD::Suld1DArrayI8Clamp;
2953 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
2954 return NVPTXISD::Suld1DArrayI16Clamp;
2955 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
2956 return NVPTXISD::Suld1DArrayI32Clamp;
2957 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
2958 return NVPTXISD::Suld1DArrayI64Clamp;
2959 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
2960 return NVPTXISD::Suld1DArrayV2I8Clamp;
2961 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
2962 return NVPTXISD::Suld1DArrayV2I16Clamp;
2963 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
2964 return NVPTXISD::Suld1DArrayV2I32Clamp;
2965 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
2966 return NVPTXISD::Suld1DArrayV2I64Clamp;
2967 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
2968 return NVPTXISD::Suld1DArrayV4I8Clamp;
2969 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
2970 return NVPTXISD::Suld1DArrayV4I16Clamp;
2971 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
2972 return NVPTXISD::Suld1DArrayV4I32Clamp;
2973 case Intrinsic::nvvm_suld_2d_i8_clamp:
2974 return NVPTXISD::Suld2DI8Clamp;
2975 case Intrinsic::nvvm_suld_2d_i16_clamp:
2976 return NVPTXISD::Suld2DI16Clamp;
2977 case Intrinsic::nvvm_suld_2d_i32_clamp:
2978 return NVPTXISD::Suld2DI32Clamp;
2979 case Intrinsic::nvvm_suld_2d_i64_clamp:
2980 return NVPTXISD::Suld2DI64Clamp;
2981 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
2982 return NVPTXISD::Suld2DV2I8Clamp;
2983 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
2984 return NVPTXISD::Suld2DV2I16Clamp;
2985 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
2986 return NVPTXISD::Suld2DV2I32Clamp;
2987 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
2988 return NVPTXISD::Suld2DV2I64Clamp;
2989 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
2990 return NVPTXISD::Suld2DV4I8Clamp;
2991 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
2992 return NVPTXISD::Suld2DV4I16Clamp;
2993 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
2994 return NVPTXISD::Suld2DV4I32Clamp;
2995 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
2996 return NVPTXISD::Suld2DArrayI8Clamp;
2997 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
2998 return NVPTXISD::Suld2DArrayI16Clamp;
2999 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3000 return NVPTXISD::Suld2DArrayI32Clamp;
3001 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3002 return NVPTXISD::Suld2DArrayI64Clamp;
3003 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3004 return NVPTXISD::Suld2DArrayV2I8Clamp;
3005 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3006 return NVPTXISD::Suld2DArrayV2I16Clamp;
3007 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3008 return NVPTXISD::Suld2DArrayV2I32Clamp;
3009 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3010 return NVPTXISD::Suld2DArrayV2I64Clamp;
3011 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3012 return NVPTXISD::Suld2DArrayV4I8Clamp;
3013 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3014 return NVPTXISD::Suld2DArrayV4I16Clamp;
3015 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3016 return NVPTXISD::Suld2DArrayV4I32Clamp;
3017 case Intrinsic::nvvm_suld_3d_i8_clamp:
3018 return NVPTXISD::Suld3DI8Clamp;
3019 case Intrinsic::nvvm_suld_3d_i16_clamp:
3020 return NVPTXISD::Suld3DI16Clamp;
3021 case Intrinsic::nvvm_suld_3d_i32_clamp:
3022 return NVPTXISD::Suld3DI32Clamp;
3023 case Intrinsic::nvvm_suld_3d_i64_clamp:
3024 return NVPTXISD::Suld3DI64Clamp;
3025 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3026 return NVPTXISD::Suld3DV2I8Clamp;
3027 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3028 return NVPTXISD::Suld3DV2I16Clamp;
3029 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3030 return NVPTXISD::Suld3DV2I32Clamp;
3031 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3032 return NVPTXISD::Suld3DV2I64Clamp;
3033 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3034 return NVPTXISD::Suld3DV4I8Clamp;
3035 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3036 return NVPTXISD::Suld3DV4I16Clamp;
3037 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3038 return NVPTXISD::Suld3DV4I32Clamp;
3039 case Intrinsic::nvvm_suld_1d_i8_trap:
3040 return NVPTXISD::Suld1DI8Trap;
3041 case Intrinsic::nvvm_suld_1d_i16_trap:
3042 return NVPTXISD::Suld1DI16Trap;
3043 case Intrinsic::nvvm_suld_1d_i32_trap:
3044 return NVPTXISD::Suld1DI32Trap;
3045 case Intrinsic::nvvm_suld_1d_i64_trap:
3046 return NVPTXISD::Suld1DI64Trap;
3047 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3048 return NVPTXISD::Suld1DV2I8Trap;
3049 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3050 return NVPTXISD::Suld1DV2I16Trap;
3051 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3052 return NVPTXISD::Suld1DV2I32Trap;
3053 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3054 return NVPTXISD::Suld1DV2I64Trap;
3055 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3056 return NVPTXISD::Suld1DV4I8Trap;
3057 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3058 return NVPTXISD::Suld1DV4I16Trap;
3059 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3060 return NVPTXISD::Suld1DV4I32Trap;
3061 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3062 return NVPTXISD::Suld1DArrayI8Trap;
3063 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3064 return NVPTXISD::Suld1DArrayI16Trap;
3065 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3066 return NVPTXISD::Suld1DArrayI32Trap;
3067 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3068 return NVPTXISD::Suld1DArrayI64Trap;
3069 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3070 return NVPTXISD::Suld1DArrayV2I8Trap;
3071 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3072 return NVPTXISD::Suld1DArrayV2I16Trap;
3073 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3074 return NVPTXISD::Suld1DArrayV2I32Trap;
3075 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3076 return NVPTXISD::Suld1DArrayV2I64Trap;
3077 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3078 return NVPTXISD::Suld1DArrayV4I8Trap;
3079 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3080 return NVPTXISD::Suld1DArrayV4I16Trap;
3081 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3082 return NVPTXISD::Suld1DArrayV4I32Trap;
3083 case Intrinsic::nvvm_suld_2d_i8_trap:
3084 return NVPTXISD::Suld2DI8Trap;
3085 case Intrinsic::nvvm_suld_2d_i16_trap:
3086 return NVPTXISD::Suld2DI16Trap;
3087 case Intrinsic::nvvm_suld_2d_i32_trap:
3088 return NVPTXISD::Suld2DI32Trap;
3089 case Intrinsic::nvvm_suld_2d_i64_trap:
3090 return NVPTXISD::Suld2DI64Trap;
3091 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3092 return NVPTXISD::Suld2DV2I8Trap;
3093 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3094 return NVPTXISD::Suld2DV2I16Trap;
3095 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3096 return NVPTXISD::Suld2DV2I32Trap;
3097 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3098 return NVPTXISD::Suld2DV2I64Trap;
3099 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3100 return NVPTXISD::Suld2DV4I8Trap;
3101 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3102 return NVPTXISD::Suld2DV4I16Trap;
3103 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3104 return NVPTXISD::Suld2DV4I32Trap;
3105 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3106 return NVPTXISD::Suld2DArrayI8Trap;
3107 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3108 return NVPTXISD::Suld2DArrayI16Trap;
3109 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3110 return NVPTXISD::Suld2DArrayI32Trap;
3111 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3112 return NVPTXISD::Suld2DArrayI64Trap;
3113 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3114 return NVPTXISD::Suld2DArrayV2I8Trap;
3115 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3116 return NVPTXISD::Suld2DArrayV2I16Trap;
3117 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3118 return NVPTXISD::Suld2DArrayV2I32Trap;
3119 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3120 return NVPTXISD::Suld2DArrayV2I64Trap;
3121 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3122 return NVPTXISD::Suld2DArrayV4I8Trap;
3123 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3124 return NVPTXISD::Suld2DArrayV4I16Trap;
3125 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3126 return NVPTXISD::Suld2DArrayV4I32Trap;
3127 case Intrinsic::nvvm_suld_3d_i8_trap:
3128 return NVPTXISD::Suld3DI8Trap;
3129 case Intrinsic::nvvm_suld_3d_i16_trap:
3130 return NVPTXISD::Suld3DI16Trap;
3131 case Intrinsic::nvvm_suld_3d_i32_trap:
3132 return NVPTXISD::Suld3DI32Trap;
3133 case Intrinsic::nvvm_suld_3d_i64_trap:
3134 return NVPTXISD::Suld3DI64Trap;
3135 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3136 return NVPTXISD::Suld3DV2I8Trap;
3137 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3138 return NVPTXISD::Suld3DV2I16Trap;
3139 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3140 return NVPTXISD::Suld3DV2I32Trap;
3141 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3142 return NVPTXISD::Suld3DV2I64Trap;
3143 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3144 return NVPTXISD::Suld3DV4I8Trap;
3145 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3146 return NVPTXISD::Suld3DV4I16Trap;
3147 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3148 return NVPTXISD::Suld3DV4I32Trap;
3149 case Intrinsic::nvvm_suld_1d_i8_zero:
3150 return NVPTXISD::Suld1DI8Zero;
3151 case Intrinsic::nvvm_suld_1d_i16_zero:
3152 return NVPTXISD::Suld1DI16Zero;
3153 case Intrinsic::nvvm_suld_1d_i32_zero:
3154 return NVPTXISD::Suld1DI32Zero;
3155 case Intrinsic::nvvm_suld_1d_i64_zero:
3156 return NVPTXISD::Suld1DI64Zero;
3157 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3158 return NVPTXISD::Suld1DV2I8Zero;
3159 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3160 return NVPTXISD::Suld1DV2I16Zero;
3161 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3162 return NVPTXISD::Suld1DV2I32Zero;
3163 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3164 return NVPTXISD::Suld1DV2I64Zero;
3165 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3166 return NVPTXISD::Suld1DV4I8Zero;
3167 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3168 return NVPTXISD::Suld1DV4I16Zero;
3169 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3170 return NVPTXISD::Suld1DV4I32Zero;
3171 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3172 return NVPTXISD::Suld1DArrayI8Zero;
3173 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3174 return NVPTXISD::Suld1DArrayI16Zero;
3175 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3176 return NVPTXISD::Suld1DArrayI32Zero;
3177 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3178 return NVPTXISD::Suld1DArrayI64Zero;
3179 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3180 return NVPTXISD::Suld1DArrayV2I8Zero;
3181 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3182 return NVPTXISD::Suld1DArrayV2I16Zero;
3183 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3184 return NVPTXISD::Suld1DArrayV2I32Zero;
3185 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3186 return NVPTXISD::Suld1DArrayV2I64Zero;
3187 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3188 return NVPTXISD::Suld1DArrayV4I8Zero;
3189 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3190 return NVPTXISD::Suld1DArrayV4I16Zero;
3191 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3192 return NVPTXISD::Suld1DArrayV4I32Zero;
3193 case Intrinsic::nvvm_suld_2d_i8_zero:
3194 return NVPTXISD::Suld2DI8Zero;
3195 case Intrinsic::nvvm_suld_2d_i16_zero:
3196 return NVPTXISD::Suld2DI16Zero;
3197 case Intrinsic::nvvm_suld_2d_i32_zero:
3198 return NVPTXISD::Suld2DI32Zero;
3199 case Intrinsic::nvvm_suld_2d_i64_zero:
3200 return NVPTXISD::Suld2DI64Zero;
3201 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3202 return NVPTXISD::Suld2DV2I8Zero;
3203 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3204 return NVPTXISD::Suld2DV2I16Zero;
3205 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3206 return NVPTXISD::Suld2DV2I32Zero;
3207 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3208 return NVPTXISD::Suld2DV2I64Zero;
3209 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3210 return NVPTXISD::Suld2DV4I8Zero;
3211 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3212 return NVPTXISD::Suld2DV4I16Zero;
3213 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3214 return NVPTXISD::Suld2DV4I32Zero;
3215 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3216 return NVPTXISD::Suld2DArrayI8Zero;
3217 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3218 return NVPTXISD::Suld2DArrayI16Zero;
3219 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3220 return NVPTXISD::Suld2DArrayI32Zero;
3221 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3222 return NVPTXISD::Suld2DArrayI64Zero;
3223 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3224 return NVPTXISD::Suld2DArrayV2I8Zero;
3225 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3226 return NVPTXISD::Suld2DArrayV2I16Zero;
3227 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3228 return NVPTXISD::Suld2DArrayV2I32Zero;
3229 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3230 return NVPTXISD::Suld2DArrayV2I64Zero;
3231 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3232 return NVPTXISD::Suld2DArrayV4I8Zero;
3233 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3234 return NVPTXISD::Suld2DArrayV4I16Zero;
3235 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3236 return NVPTXISD::Suld2DArrayV4I32Zero;
3237 case Intrinsic::nvvm_suld_3d_i8_zero:
3238 return NVPTXISD::Suld3DI8Zero;
3239 case Intrinsic::nvvm_suld_3d_i16_zero:
3240 return NVPTXISD::Suld3DI16Zero;
3241 case Intrinsic::nvvm_suld_3d_i32_zero:
3242 return NVPTXISD::Suld3DI32Zero;
3243 case Intrinsic::nvvm_suld_3d_i64_zero:
3244 return NVPTXISD::Suld3DI64Zero;
3245 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3246 return NVPTXISD::Suld3DV2I8Zero;
3247 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3248 return NVPTXISD::Suld3DV2I16Zero;
3249 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3250 return NVPTXISD::Suld3DV2I32Zero;
3251 case Intrinsic::nvvm_suld_3d_v2i64_zero:
3252 return NVPTXISD::Suld3DV2I64Zero;
3253 case Intrinsic::nvvm_suld_3d_v4i8_zero:
3254 return NVPTXISD::Suld3DV4I8Zero;
3255 case Intrinsic::nvvm_suld_3d_v4i16_zero:
3256 return NVPTXISD::Suld3DV4I16Zero;
3257 case Intrinsic::nvvm_suld_3d_v4i32_zero:
3258 return NVPTXISD::Suld3DV4I32Zero;
3262 // llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
3264 // because we need the information that is only available in the "Value" type
3266 // pointer. In particular, the address space information.
3267 bool NVPTXTargetLowering::getTgtMemIntrinsic(
3268 IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
3269 switch (Intrinsic) {
3273 case Intrinsic::nvvm_atomic_load_add_f32:
3274 Info.opc = ISD::INTRINSIC_W_CHAIN;
3275 Info.memVT = MVT::f32;
3276 Info.ptrVal = I.getArgOperand(0);
3279 Info.readMem = true;
3280 Info.writeMem = true;
3284 case Intrinsic::nvvm_atomic_load_inc_32:
3285 case Intrinsic::nvvm_atomic_load_dec_32:
3286 Info.opc = ISD::INTRINSIC_W_CHAIN;
3287 Info.memVT = MVT::i32;
3288 Info.ptrVal = I.getArgOperand(0);
3291 Info.readMem = true;
3292 Info.writeMem = true;
3296 case Intrinsic::nvvm_ldu_global_i:
3297 case Intrinsic::nvvm_ldu_global_f:
3298 case Intrinsic::nvvm_ldu_global_p: {
3299 auto &DL = I.getModule()->getDataLayout();
3300 Info.opc = ISD::INTRINSIC_W_CHAIN;
3301 if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
3302 Info.memVT = getValueType(DL, I.getType());
3303 else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
3304 Info.memVT = getPointerTy(DL);
3306 Info.memVT = getValueType(DL, I.getType());
3307 Info.ptrVal = I.getArgOperand(0);
3310 Info.readMem = true;
3311 Info.writeMem = false;
3312 Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3316 case Intrinsic::nvvm_ldg_global_i:
3317 case Intrinsic::nvvm_ldg_global_f:
3318 case Intrinsic::nvvm_ldg_global_p: {
3319 auto &DL = I.getModule()->getDataLayout();
3321 Info.opc = ISD::INTRINSIC_W_CHAIN;
3322 if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
3323 Info.memVT = getValueType(DL, I.getType());
3324 else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
3325 Info.memVT = getPointerTy(DL);
3327 Info.memVT = getValueType(DL, I.getType());
3328 Info.ptrVal = I.getArgOperand(0);
3331 Info.readMem = true;
3332 Info.writeMem = false;
3333 Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3338 case Intrinsic::nvvm_tex_1d_v4f32_s32:
3339 case Intrinsic::nvvm_tex_1d_v4f32_f32:
3340 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
3341 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
3342 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
3343 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
3344 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
3345 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
3346 case Intrinsic::nvvm_tex_2d_v4f32_s32:
3347 case Intrinsic::nvvm_tex_2d_v4f32_f32:
3348 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
3349 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
3350 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
3351 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
3352 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
3353 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
3354 case Intrinsic::nvvm_tex_3d_v4f32_s32:
3355 case Intrinsic::nvvm_tex_3d_v4f32_f32:
3356 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
3357 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
3358 case Intrinsic::nvvm_tex_cube_v4f32_f32:
3359 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
3360 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
3361 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
3362 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
3363 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
3364 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
3365 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
3366 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
3367 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
3368 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
3369 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
3370 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
3371 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
3372 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
3373 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
3374 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
3375 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
3376 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
3377 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
3378 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3379 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3380 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3381 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3382 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3383 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3384 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3385 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3386 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3387 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3388 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3389 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3390 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3391 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3392 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3393 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32: {
3394 Info.opc = getOpcForTextureInstr(Intrinsic);
3395 Info.memVT = MVT::v4f32;
3396 Info.ptrVal = nullptr;
3399 Info.readMem = true;
3400 Info.writeMem = false;
3404 case Intrinsic::nvvm_tex_1d_v4s32_s32:
3405 case Intrinsic::nvvm_tex_1d_v4s32_f32:
3406 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
3407 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
3408 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
3409 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
3410 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
3411 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
3412 case Intrinsic::nvvm_tex_2d_v4s32_s32:
3413 case Intrinsic::nvvm_tex_2d_v4s32_f32:
3414 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
3415 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
3416 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
3417 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
3418 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
3419 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
3420 case Intrinsic::nvvm_tex_3d_v4s32_s32:
3421 case Intrinsic::nvvm_tex_3d_v4s32_f32:
3422 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
3423 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
3424 case Intrinsic::nvvm_tex_cube_v4s32_f32:
3425 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
3426 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
3427 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
3428 case Intrinsic::nvvm_tex_cube_v4u32_f32:
3429 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
3430 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
3431 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
3432 case Intrinsic::nvvm_tex_1d_v4u32_s32:
3433 case Intrinsic::nvvm_tex_1d_v4u32_f32:
3434 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
3435 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
3436 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
3437 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
3438 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
3439 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
3440 case Intrinsic::nvvm_tex_2d_v4u32_s32:
3441 case Intrinsic::nvvm_tex_2d_v4u32_f32:
3442 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
3443 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
3444 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
3445 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
3446 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
3447 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
3448 case Intrinsic::nvvm_tex_3d_v4u32_s32:
3449 case Intrinsic::nvvm_tex_3d_v4u32_f32:
3450 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
3451 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
3452 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
3453 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
3454 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
3455 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
3456 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
3457 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
3458 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
3459 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
3460 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
3461 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
3462 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
3463 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
3464 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
3465 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
3466 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
3467 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
3468 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
3469 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
3470 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
3471 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3472 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3473 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3474 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3475 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3476 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3477 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3478 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3479 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3480 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
3481 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
3482 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
3483 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
3484 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
3485 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
3486 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
3487 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
3488 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3489 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3490 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3491 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3492 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3493 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3494 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3495 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3496 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3497 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3498 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3499 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3500 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3501 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3502 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3503 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3504 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3505 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3506 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3507 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3508 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3509 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3510 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3511 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
3512 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3513 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3514 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3515 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32: {
3516 Info.opc = getOpcForTextureInstr(Intrinsic);
3517 Info.memVT = MVT::v4i32;
3518 Info.ptrVal = nullptr;
3521 Info.readMem = true;
3522 Info.writeMem = false;
3526 case Intrinsic::nvvm_suld_1d_i8_clamp:
3527 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3528 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3529 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3530 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3531 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3532 case Intrinsic::nvvm_suld_2d_i8_clamp:
3533 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3534 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3535 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3536 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3537 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3538 case Intrinsic::nvvm_suld_3d_i8_clamp:
3539 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3540 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3541 case Intrinsic::nvvm_suld_1d_i8_trap:
3542 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3543 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3544 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3545 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3546 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3547 case Intrinsic::nvvm_suld_2d_i8_trap:
3548 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3549 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3550 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3551 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3552 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3553 case Intrinsic::nvvm_suld_3d_i8_trap:
3554 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3555 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3556 case Intrinsic::nvvm_suld_1d_i8_zero:
3557 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3558 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3559 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3560 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3561 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3562 case Intrinsic::nvvm_suld_2d_i8_zero:
3563 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3564 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3565 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3566 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3567 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3568 case Intrinsic::nvvm_suld_3d_i8_zero:
3569 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3570 case Intrinsic::nvvm_suld_3d_v4i8_zero: {
3571 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3572 Info.memVT = MVT::i8;
3573 Info.ptrVal = nullptr;
3576 Info.readMem = true;
3577 Info.writeMem = false;
3581 case Intrinsic::nvvm_suld_1d_i16_clamp:
3582 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3583 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3584 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3585 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3586 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3587 case Intrinsic::nvvm_suld_2d_i16_clamp:
3588 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3589 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3590 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3591 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3592 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3593 case Intrinsic::nvvm_suld_3d_i16_clamp:
3594 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3595 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3596 case Intrinsic::nvvm_suld_1d_i16_trap:
3597 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3598 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3599 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3600 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3601 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3602 case Intrinsic::nvvm_suld_2d_i16_trap:
3603 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3604 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3605 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3606 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3607 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3608 case Intrinsic::nvvm_suld_3d_i16_trap:
3609 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3610 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3611 case Intrinsic::nvvm_suld_1d_i16_zero:
3612 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3613 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3614 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3615 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3616 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3617 case Intrinsic::nvvm_suld_2d_i16_zero:
3618 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3619 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3620 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3621 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3622 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3623 case Intrinsic::nvvm_suld_3d_i16_zero:
3624 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3625 case Intrinsic::nvvm_suld_3d_v4i16_zero: {
3626 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3627 Info.memVT = MVT::i16;
3628 Info.ptrVal = nullptr;
3631 Info.readMem = true;
3632 Info.writeMem = false;
3636 case Intrinsic::nvvm_suld_1d_i32_clamp:
3637 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3638 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3639 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3640 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3641 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3642 case Intrinsic::nvvm_suld_2d_i32_clamp:
3643 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3644 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3645 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3646 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3647 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3648 case Intrinsic::nvvm_suld_3d_i32_clamp:
3649 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3650 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3651 case Intrinsic::nvvm_suld_1d_i32_trap:
3652 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3653 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3654 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3655 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3656 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3657 case Intrinsic::nvvm_suld_2d_i32_trap:
3658 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3659 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3660 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3661 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3662 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3663 case Intrinsic::nvvm_suld_3d_i32_trap:
3664 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3665 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3666 case Intrinsic::nvvm_suld_1d_i32_zero:
3667 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3668 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3669 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3670 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3671 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3672 case Intrinsic::nvvm_suld_2d_i32_zero:
3673 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3674 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3675 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3676 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3677 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3678 case Intrinsic::nvvm_suld_3d_i32_zero:
3679 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3680 case Intrinsic::nvvm_suld_3d_v4i32_zero: {
3681 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3682 Info.memVT = MVT::i32;
3683 Info.ptrVal = nullptr;
3686 Info.readMem = true;
3687 Info.writeMem = false;
3691 case Intrinsic::nvvm_suld_1d_i64_clamp:
3692 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3693 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3694 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3695 case Intrinsic::nvvm_suld_2d_i64_clamp:
3696 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3697 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3698 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3699 case Intrinsic::nvvm_suld_3d_i64_clamp:
3700 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3701 case Intrinsic::nvvm_suld_1d_i64_trap:
3702 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3703 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3704 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3705 case Intrinsic::nvvm_suld_2d_i64_trap:
3706 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3707 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3708 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3709 case Intrinsic::nvvm_suld_3d_i64_trap:
3710 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3711 case Intrinsic::nvvm_suld_1d_i64_zero:
3712 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3713 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3714 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3715 case Intrinsic::nvvm_suld_2d_i64_zero:
3716 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3717 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3718 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3719 case Intrinsic::nvvm_suld_3d_i64_zero:
3720 case Intrinsic::nvvm_suld_3d_v2i64_zero: {
3721 Info.opc = getOpcForSurfaceInstr(Intrinsic);
3722 Info.memVT = MVT::i64;
3723 Info.ptrVal = nullptr;
3726 Info.readMem = true;
3727 Info.writeMem = false;
3735 /// isLegalAddressingMode - Return true if the addressing mode represented
3736 /// by AM is legal for this target, for a load/store of the specified type.
3737 /// Used to guide target specific optimizations, like loop strength reduction
3738 /// (LoopStrengthReduce.cpp) and memory optimization for address mode
3739 /// (CodeGenPrepare.cpp)
3740 bool NVPTXTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3741 const AddrMode &AM, Type *Ty,
3742 unsigned AS) const {
3744 // AddrMode - This represents an addressing mode of:
3745 // BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
3747 // The legal address modes are
3754 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale;
3758 case 0: // "r", "r+i" or "i" is allowed
3761 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
3763 // Otherwise we have r+i.
3766 // No scale > 1 is allowed
3772 //===----------------------------------------------------------------------===//
3773 // NVPTX Inline Assembly Support
3774 //===----------------------------------------------------------------------===//
3776 /// getConstraintType - Given a constraint letter, return the type of
3777 /// constraint it is for this target.
3778 NVPTXTargetLowering::ConstraintType
3779 NVPTXTargetLowering::getConstraintType(StringRef Constraint) const {
3780 if (Constraint.size() == 1) {
3781 switch (Constraint[0]) {
3793 return C_RegisterClass;
3796 return TargetLowering::getConstraintType(Constraint);
3799 std::pair<unsigned, const TargetRegisterClass *>
3800 NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3801 StringRef Constraint,
3803 if (Constraint.size() == 1) {
3804 switch (Constraint[0]) {
3806 return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
3808 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3810 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3812 return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
3815 return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
3817 return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
3819 return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
3822 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3825 /// getFunctionAlignment - Return the Log2 alignment of this function.
3826 unsigned NVPTXTargetLowering::getFunctionAlignment(const Function *) const {
3830 //===----------------------------------------------------------------------===//
3831 // NVPTX DAG Combining
3832 //===----------------------------------------------------------------------===//
3834 bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
3835 CodeGenOpt::Level OptLevel) const {
3836 const Function *F = MF.getFunction();
3837 const TargetOptions &TO = MF.getTarget().Options;
3839 // Always honor command-line argument
3840 if (FMAContractLevelOpt.getNumOccurrences() > 0) {
3841 return FMAContractLevelOpt > 0;
3842 } else if (OptLevel == 0) {
3843 // Do not contract if we're not optimizing the code
3845 } else if (TO.AllowFPOpFusion == FPOpFusion::Fast || TO.UnsafeFPMath) {
3846 // Honor TargetOptions flags that explicitly say fusion is okay
3848 } else if (F->hasFnAttribute("unsafe-fp-math")) {
3849 // Check for unsafe-fp-math=true coming from Clang
3850 Attribute Attr = F->getFnAttribute("unsafe-fp-math");
3851 StringRef Val = Attr.getValueAsString();
3856 // We did not have a clear indication that fusion is allowed, so assume not
3860 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
3861 /// operands N0 and N1. This is a helper for PerformADDCombine that is
3862 /// called with the default operands, and if that fails, with commuted
3864 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
3865 TargetLowering::DAGCombinerInfo &DCI,
3866 const NVPTXSubtarget &Subtarget,
3867 CodeGenOpt::Level OptLevel) {
3868 SelectionDAG &DAG = DCI.DAG;
3869 // Skip non-integer, non-scalar case
3870 EVT VT=N0.getValueType();
3874 // fold (add (mul a, b), c) -> (mad a, b, c)
3876 if (N0.getOpcode() == ISD::MUL) {
3877 assert (VT.isInteger());
3879 // Since integer multiply-add costs the same as integer multiply
3880 // but is more costly than integer add, do the fusion only when
3881 // the mul is only used in the add.
3882 if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
3883 !N0.getNode()->hasOneUse())
3887 return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
3888 N0.getOperand(0), N0.getOperand(1), N1);
3890 else if (N0.getOpcode() == ISD::FMUL) {
3891 if (VT == MVT::f32 || VT == MVT::f64) {
3892 const auto *TLI = static_cast<const NVPTXTargetLowering *>(
3893 &DAG.getTargetLoweringInfo());
3894 if (!TLI->allowFMA(DAG.getMachineFunction(), OptLevel))
3897 // For floating point:
3898 // Do the fusion only when the mul has less than 5 uses and all
3900 // The heuristic is that if a use is not an add, then that use
3901 // cannot be fused into fma, therefore mul is still needed anyway.
3902 // If there are more than 4 uses, even if they are all add, fusing
3903 // them will increase register pressue.
3906 int nonAddCount = 0;
3907 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3908 UE = N0.getNode()->use_end();
3912 if (User->getOpcode() != ISD::FADD)
3918 int orderNo = N->getIROrder();
3919 int orderNo2 = N0.getNode()->getIROrder();
3920 // simple heuristics here for considering potential register
3921 // pressure, the logics here is that the differnce are used
3922 // to measure the distance between def and use, the longer distance
3923 // more likely cause register pressure.
3924 if (orderNo - orderNo2 < 500)
3927 // Now, check if at least one of the FMUL's operands is live beyond the node N,
3928 // which guarantees that the FMA will not increase register pressure at node N.
3929 bool opIsLive = false;
3930 const SDNode *left = N0.getOperand(0).getNode();
3931 const SDNode *right = N0.getOperand(1).getNode();
3933 if (isa<ConstantSDNode>(left) || isa<ConstantSDNode>(right))
3937 for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
3939 int orderNo3 = User->getIROrder();
3940 if (orderNo3 > orderNo) {
3947 for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
3949 int orderNo3 = User->getIROrder();
3950 if (orderNo3 > orderNo) {
3960 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
3961 N0.getOperand(0), N0.getOperand(1), N1);
3968 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3970 static SDValue PerformADDCombine(SDNode *N,
3971 TargetLowering::DAGCombinerInfo &DCI,
3972 const NVPTXSubtarget &Subtarget,
3973 CodeGenOpt::Level OptLevel) {
3974 SDValue N0 = N->getOperand(0);
3975 SDValue N1 = N->getOperand(1);
3977 // First try with the default operand order.
3978 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget,
3980 if (Result.getNode())
3983 // If that didn't work, try again with the operands commuted.
3984 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
3987 static SDValue PerformANDCombine(SDNode *N,
3988 TargetLowering::DAGCombinerInfo &DCI) {
3989 // The type legalizer turns a vector load of i8 values into a zextload to i16
3990 // registers, optionally ANY_EXTENDs it (if target type is integer),
3991 // and ANDs off the high 8 bits. Since we turn this load into a
3992 // target-specific DAG node, the DAG combiner fails to eliminate these AND
3993 // nodes. Do that here.
3994 SDValue Val = N->getOperand(0);
3995 SDValue Mask = N->getOperand(1);
3997 if (isa<ConstantSDNode>(Val)) {
3998 std::swap(Val, Mask);
4002 // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
4003 if (Val.getOpcode() == ISD::ANY_EXTEND) {
4005 Val = Val->getOperand(0);
4008 if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
4009 Val = Val->getOperand(0);
4012 if (Val->getOpcode() == NVPTXISD::LoadV2 ||
4013 Val->getOpcode() == NVPTXISD::LoadV4) {
4014 ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
4016 // Not an AND with a constant
4020 uint64_t MaskVal = MaskCnst->getZExtValue();
4021 if (MaskVal != 0xff) {
4022 // Not an AND that chops off top 8 bits
4026 MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
4028 // Not a MemSDNode?!?
4032 EVT MemVT = Mem->getMemoryVT();
4033 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
4034 // We only handle the i8 case
4039 cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
4041 if (ExtType == ISD::SEXTLOAD) {
4042 // If for some reason the load is a sextload, the and is needed to zero
4043 // out the high 8 bits
4048 if (AExt.getNode() != 0) {
4049 // Re-insert the ext as a zext.
4050 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
4051 AExt.getValueType(), Val);
4055 // If we get here, the AND is unnecessary. Just replace it with the load
4056 DCI.CombineTo(N, Val, AddTo);
4062 enum OperandSignedness {
4068 /// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
4069 /// that can be demoted to \p OptSize bits without loss of information. The
4070 /// signedness of the operand, if determinable, is placed in \p S.
4071 static bool IsMulWideOperandDemotable(SDValue Op,
4073 OperandSignedness &S) {
4076 if (Op.getOpcode() == ISD::SIGN_EXTEND ||
4077 Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
4078 EVT OrigVT = Op.getOperand(0).getValueType();
4079 if (OrigVT.getSizeInBits() <= OptSize) {
4083 } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
4084 EVT OrigVT = Op.getOperand(0).getValueType();
4085 if (OrigVT.getSizeInBits() <= OptSize) {
4094 /// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
4095 /// be demoted to \p OptSize bits without loss of information. If the operands
4096 /// contain a constant, it should appear as the RHS operand. The signedness of
4097 /// the operands is placed in \p IsSigned.
4098 static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
4102 OperandSignedness LHSSign;
4104 // The LHS operand must be a demotable op
4105 if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
4108 // We should have been able to determine the signedness from the LHS
4109 if (LHSSign == Unknown)
4112 IsSigned = (LHSSign == Signed);
4114 // The RHS can be a demotable op or a constant
4115 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
4116 APInt Val = CI->getAPIntValue();
4117 if (LHSSign == Unsigned) {
4118 return Val.isIntN(OptSize);
4120 return Val.isSignedIntN(OptSize);
4123 OperandSignedness RHSSign;
4124 if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
4127 return LHSSign == RHSSign;
4131 /// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
4132 /// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
4133 /// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
4135 static SDValue TryMULWIDECombine(SDNode *N,
4136 TargetLowering::DAGCombinerInfo &DCI) {
4137 EVT MulType = N->getValueType(0);
4138 if (MulType != MVT::i32 && MulType != MVT::i64) {
4143 unsigned OptSize = MulType.getSizeInBits() >> 1;
4144 SDValue LHS = N->getOperand(0);
4145 SDValue RHS = N->getOperand(1);
4147 // Canonicalize the multiply so the constant (if any) is on the right
4148 if (N->getOpcode() == ISD::MUL) {
4149 if (isa<ConstantSDNode>(LHS)) {
4150 std::swap(LHS, RHS);
4154 // If we have a SHL, determine the actual multiply amount
4155 if (N->getOpcode() == ISD::SHL) {
4156 ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
4161 APInt ShiftAmt = ShlRHS->getAPIntValue();
4162 unsigned BitWidth = MulType.getSizeInBits();
4163 if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
4164 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
4165 RHS = DCI.DAG.getConstant(MulVal, DL, MulType);
4172 // Verify that our operands are demotable
4173 if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
4178 if (MulType == MVT::i32) {
4179 DemotedVT = MVT::i16;
4181 DemotedVT = MVT::i32;
4184 // Truncate the operands to the correct size. Note that these are just for
4185 // type consistency and will (likely) be eliminated in later phases.
4187 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS);
4189 DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS);
4193 Opc = NVPTXISD::MUL_WIDE_SIGNED;
4195 Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
4198 return DCI.DAG.getNode(Opc, DL, MulType, TruncLHS, TruncRHS);
4201 /// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
4202 static SDValue PerformMULCombine(SDNode *N,
4203 TargetLowering::DAGCombinerInfo &DCI,
4204 CodeGenOpt::Level OptLevel) {
4206 // Try mul.wide combining at OptLevel > 0
4207 SDValue Ret = TryMULWIDECombine(N, DCI);
4215 /// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
4216 static SDValue PerformSHLCombine(SDNode *N,
4217 TargetLowering::DAGCombinerInfo &DCI,
4218 CodeGenOpt::Level OptLevel) {
4220 // Try mul.wide combining at OptLevel > 0
4221 SDValue Ret = TryMULWIDECombine(N, DCI);
4229 SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
4230 DAGCombinerInfo &DCI) const {
4231 CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
4232 switch (N->getOpcode()) {
4236 return PerformADDCombine(N, DCI, STI, OptLevel);
4238 return PerformMULCombine(N, DCI, OptLevel);
4240 return PerformSHLCombine(N, DCI, OptLevel);
4242 return PerformANDCombine(N, DCI);
4247 /// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
4248 static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
4249 SmallVectorImpl<SDValue> &Results) {
4250 EVT ResVT = N->getValueType(0);
4253 assert(ResVT.isVector() && "Vector load must have vector type");
4255 // We only handle "native" vector sizes for now, e.g. <4 x double> is not
4256 // legal. We can (and should) split that into 2 loads of <2 x double> here
4257 // but I'm leaving that as a TODO for now.
4258 assert(ResVT.isSimple() && "Can only handle simple types");
4259 switch (ResVT.getSimpleVT().SimpleTy) {
4272 // This is a "native" vector type
4276 LoadSDNode *LD = cast<LoadSDNode>(N);
4278 unsigned Align = LD->getAlignment();
4279 auto &TD = DAG.getDataLayout();
4280 unsigned PrefAlign =
4281 TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext()));
4282 if (Align < PrefAlign) {
4283 // This load is not sufficiently aligned, so bail out and let this vector
4284 // load be scalarized. Note that we may still be able to emit smaller
4285 // vector loads. For example, if we are loading a <4 x float> with an
4286 // alignment of 8, this check will fail but the legalizer will try again
4287 // with 2 x <2 x float>, which will succeed with an alignment of 8.
4291 EVT EltVT = ResVT.getVectorElementType();
4292 unsigned NumElts = ResVT.getVectorNumElements();
4294 // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
4295 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4296 // loaded type to i16 and propagate the "real" type as the memory type.
4297 bool NeedTrunc = false;
4298 if (EltVT.getSizeInBits() < 16) {
4303 unsigned Opcode = 0;
4310 Opcode = NVPTXISD::LoadV2;
4311 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4314 Opcode = NVPTXISD::LoadV4;
4315 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4316 LdResVTs = DAG.getVTList(ListVTs);
4321 // Copy regular operands
4322 SmallVector<SDValue, 8> OtherOps(N->op_begin(), N->op_end());
4324 // The select routine does not have access to the LoadSDNode instance, so
4325 // pass along the extension information
4326 OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType(), DL));
4328 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4330 LD->getMemOperand());
4332 SmallVector<SDValue, 4> ScalarRes;
4334 for (unsigned i = 0; i < NumElts; ++i) {
4335 SDValue Res = NewLD.getValue(i);
4337 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4338 ScalarRes.push_back(Res);
4341 SDValue LoadChain = NewLD.getValue(NumElts);
4343 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
4345 Results.push_back(BuildVec);
4346 Results.push_back(LoadChain);
4349 static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
4350 SmallVectorImpl<SDValue> &Results) {
4351 SDValue Chain = N->getOperand(0);
4352 SDValue Intrin = N->getOperand(1);
4355 // Get the intrinsic ID
4356 unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
4360 case Intrinsic::nvvm_ldg_global_i:
4361 case Intrinsic::nvvm_ldg_global_f:
4362 case Intrinsic::nvvm_ldg_global_p:
4363 case Intrinsic::nvvm_ldu_global_i:
4364 case Intrinsic::nvvm_ldu_global_f:
4365 case Intrinsic::nvvm_ldu_global_p: {
4366 EVT ResVT = N->getValueType(0);
4368 if (ResVT.isVector()) {
4371 unsigned NumElts = ResVT.getVectorNumElements();
4372 EVT EltVT = ResVT.getVectorElementType();
4374 // Since LDU/LDG are target nodes, we cannot rely on DAG type
4376 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
4377 // loaded type to i16 and propagate the "real" type as the memory type.
4378 bool NeedTrunc = false;
4379 if (EltVT.getSizeInBits() < 16) {
4384 unsigned Opcode = 0;
4394 case Intrinsic::nvvm_ldg_global_i:
4395 case Intrinsic::nvvm_ldg_global_f:
4396 case Intrinsic::nvvm_ldg_global_p:
4397 Opcode = NVPTXISD::LDGV2;
4399 case Intrinsic::nvvm_ldu_global_i:
4400 case Intrinsic::nvvm_ldu_global_f:
4401 case Intrinsic::nvvm_ldu_global_p:
4402 Opcode = NVPTXISD::LDUV2;
4405 LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4411 case Intrinsic::nvvm_ldg_global_i:
4412 case Intrinsic::nvvm_ldg_global_f:
4413 case Intrinsic::nvvm_ldg_global_p:
4414 Opcode = NVPTXISD::LDGV4;
4416 case Intrinsic::nvvm_ldu_global_i:
4417 case Intrinsic::nvvm_ldu_global_f:
4418 case Intrinsic::nvvm_ldu_global_p:
4419 Opcode = NVPTXISD::LDUV4;
4422 EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4423 LdResVTs = DAG.getVTList(ListVTs);
4428 SmallVector<SDValue, 8> OtherOps;
4430 // Copy regular operands
4432 OtherOps.push_back(Chain); // Chain
4433 // Skip operand 1 (intrinsic ID)
4435 OtherOps.append(N->op_begin() + 2, N->op_end());
4437 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4439 SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4440 MemSD->getMemoryVT(),
4441 MemSD->getMemOperand());
4443 SmallVector<SDValue, 4> ScalarRes;
4445 for (unsigned i = 0; i < NumElts; ++i) {
4446 SDValue Res = NewLD.getValue(i);
4449 DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4450 ScalarRes.push_back(Res);
4453 SDValue LoadChain = NewLD.getValue(NumElts);
4456 DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
4458 Results.push_back(BuildVec);
4459 Results.push_back(LoadChain);
4462 assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
4463 "Custom handling of non-i8 ldu/ldg?");
4465 // Just copy all operands as-is
4466 SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
4468 // Force output to i16
4469 SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
4471 MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4473 // We make sure the memory type is i8, which will be used during isel
4474 // to select the proper instruction.
4476 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
4477 MVT::i8, MemSD->getMemOperand());
4479 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
4480 NewLD.getValue(0)));
4481 Results.push_back(NewLD.getValue(1));
4487 void NVPTXTargetLowering::ReplaceNodeResults(
4488 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
4489 switch (N->getOpcode()) {
4491 report_fatal_error("Unhandled custom legalization");
4493 ReplaceLoadVector(N, DAG, Results);
4495 case ISD::INTRINSIC_W_CHAIN:
4496 ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
4501 // Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
4502 void NVPTXSection::anchor() {}
4504 NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
4508 delete ReadOnlySection;
4510 delete StaticCtorSection;
4511 delete StaticDtorSection;
4513 delete EHFrameSection;
4514 delete DwarfAbbrevSection;
4515 delete DwarfInfoSection;
4516 delete DwarfLineSection;
4517 delete DwarfFrameSection;
4518 delete DwarfPubTypesSection;
4519 delete DwarfDebugInlineSection;
4520 delete DwarfStrSection;
4521 delete DwarfLocSection;
4522 delete DwarfARangesSection;
4523 delete DwarfRangesSection;
4527 NVPTXTargetObjectFile::SelectSectionForGlobal(const GlobalValue *GV,
4528 SectionKind Kind, Mangler &Mang,
4529 const TargetMachine &TM) const {
4530 return getDataSection();