1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef NVPTXISELLOWERING_H
16 #define NVPTXISELLOWERING_H
19 #include "NVPTXSubtarget.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
40 StoreParamS32, // to sext and store a <32bit value, not used currently
41 StoreParamU32, // to zext and store a <32bit value, not used currently
65 //===--------------------------------------------------------------------===//
66 // TargetLowering Implementation
67 //===--------------------------------------------------------------------===//
68 class NVPTXTargetLowering : public TargetLowering {
70 explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
71 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
73 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
74 SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
75 SelectionDAG &DAG) const;
77 virtual const char *getTargetNodeName(unsigned Opcode) const;
79 bool isTypeSupportedInIntrinsic(MVT VT) const;
81 bool getTgtMemIntrinsic(IntrinsicInfo& Info, const CallInst &I,
82 unsigned Intrinsic) const;
84 /// isLegalAddressingMode - Return true if the addressing mode represented
85 /// by AM is legal for this target, for a load/store of the specified type
86 /// Used to guide target specific optimizations, like loop strength
87 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
88 /// address mode (CodeGenPrepare.cpp)
89 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
91 /// getFunctionAlignment - Return the Log2 alignment of this function.
92 virtual unsigned getFunctionAlignment(const Function *F) const;
94 virtual EVT getSetCCResultType(EVT VT) const {
96 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
100 ConstraintType getConstraintType(const std::string &Constraint) const;
101 std::pair<unsigned, const TargetRegisterClass*>
102 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
105 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
106 const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl,
108 SmallVectorImpl<SDValue> &InVals) const;
111 LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const;
113 std::string getPrototype(Type *, const ArgListTy &,
114 const SmallVectorImpl<ISD::OutputArg> &,
115 unsigned retAlignment) const;
118 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
119 const SmallVectorImpl<ISD::OutputArg> &Outs,
120 const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl,
121 SelectionDAG &DAG) const;
123 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
124 std::vector<SDValue> &Ops,
125 SelectionDAG &DAG) const;
127 NVPTXTargetMachine *nvTM;
129 // PTX always uses 32-bit shift amounts
130 virtual MVT getShiftAmountTy(EVT LHSTy) const {
134 virtual bool shouldSplitVectorElementType(EVT VT) const;
137 const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
139 SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx, EVT =
141 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT = MVT::i32) const;
142 SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
144 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
146 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
147 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
151 #endif // NVPTXISELLOWERING_H