1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef NVPTXISELLOWERING_H
16 #define NVPTXISELLOWERING_H
19 #include "NVPTXSubtarget.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
54 LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
68 StoreParamS32, // to sext and store a <32bit value, not used currently
69 StoreParamU32, // to zext and store a <32bit value, not used currently
76 //===--------------------------------------------------------------------===//
77 // TargetLowering Implementation
78 //===--------------------------------------------------------------------===//
79 class NVPTXTargetLowering : public TargetLowering {
81 explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
82 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
86 SelectionDAG &DAG) const;
88 virtual const char *getTargetNodeName(unsigned Opcode) const;
90 bool isTypeSupportedInIntrinsic(MVT VT) const;
92 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
93 unsigned Intrinsic) const;
95 /// isLegalAddressingMode - Return true if the addressing mode represented
96 /// by AM is legal for this target, for a load/store of the specified type
97 /// Used to guide target specific optimizations, like loop strength
98 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
99 /// address mode (CodeGenPrepare.cpp)
100 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
102 /// getFunctionAlignment - Return the Log2 alignment of this function.
103 virtual unsigned getFunctionAlignment(const Function *F) const;
105 virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const {
107 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
111 ConstraintType getConstraintType(const std::string &Constraint) const;
112 std::pair<unsigned, const TargetRegisterClass *>
113 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
115 virtual SDValue LowerFormalArguments(
116 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
117 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
118 SmallVectorImpl<SDValue> &InVals) const;
121 LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const;
123 std::string getPrototype(Type *, const ArgListTy &,
124 const SmallVectorImpl<ISD::OutputArg> &,
125 unsigned retAlignment,
126 const ImmutableCallSite *CS) const;
129 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
130 const SmallVectorImpl<ISD::OutputArg> &Outs,
131 const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
132 SelectionDAG &DAG) const;
134 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
135 std::vector<SDValue> &Ops,
136 SelectionDAG &DAG) const;
138 NVPTXTargetMachine *nvTM;
140 // PTX always uses 32-bit shift amounts
141 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
143 virtual bool shouldSplitVectorElementType(EVT VT) const;
146 const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
148 SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx,
149 EVT = MVT::i32) const;
150 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
151 SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
153 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
155 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
158 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
159 SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
160 SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
162 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
163 SelectionDAG &DAG) const;
165 unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS,
166 Type *Ty, unsigned Idx) const;
170 #endif // NVPTXISELLOWERING_H