1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef NVPTXISELLOWERING_H
16 #define NVPTXISELLOWERING_H
19 #include "NVPTXSubtarget.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
55 LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
69 StoreParamS32, // to sext and store a <32bit value, not used currently
70 StoreParamU32, // to zext and store a <32bit value, not used currently
86 Tex1DArrayFloatFloatLevel,
87 Tex1DArrayFloatFloatGrad,
90 Tex1DArrayI32FloatLevel,
91 Tex1DArrayI32FloatGrad,
101 Tex2DArrayFloatFloat,
102 Tex2DArrayFloatFloatLevel,
103 Tex2DArrayFloatFloatGrad,
106 Tex2DArrayI32FloatLevel,
107 Tex2DArrayI32FloatGrad,
110 Tex3DFloatFloatLevel,
117 // Surface intrinsics
132 Suld1DArrayV2I16Trap,
133 Suld1DArrayV2I32Trap,
135 Suld1DArrayV4I16Trap,
136 Suld1DArrayV4I32Trap,
152 Suld2DArrayV2I16Trap,
153 Suld2DArrayV2I32Trap,
155 Suld2DArrayV4I16Trap,
156 Suld2DArrayV4I32Trap,
170 //===--------------------------------------------------------------------===//
171 // TargetLowering Implementation
172 //===--------------------------------------------------------------------===//
173 class NVPTXTargetLowering : public TargetLowering {
175 explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
176 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
178 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
179 SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
180 SelectionDAG &DAG) const;
182 virtual const char *getTargetNodeName(unsigned Opcode) const;
184 bool isTypeSupportedInIntrinsic(MVT VT) const;
186 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
187 unsigned Intrinsic) const;
189 /// isLegalAddressingMode - Return true if the addressing mode represented
190 /// by AM is legal for this target, for a load/store of the specified type
191 /// Used to guide target specific optimizations, like loop strength
192 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
193 /// address mode (CodeGenPrepare.cpp)
194 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
196 /// getFunctionAlignment - Return the Log2 alignment of this function.
197 virtual unsigned getFunctionAlignment(const Function *F) const;
199 virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const {
201 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
205 ConstraintType getConstraintType(const std::string &Constraint) const;
206 std::pair<unsigned, const TargetRegisterClass *>
207 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
209 virtual SDValue LowerFormalArguments(
210 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
211 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
212 SmallVectorImpl<SDValue> &InVals) const;
215 LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const;
217 std::string getPrototype(Type *, const ArgListTy &,
218 const SmallVectorImpl<ISD::OutputArg> &,
219 unsigned retAlignment,
220 const ImmutableCallSite *CS) const;
223 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
224 const SmallVectorImpl<ISD::OutputArg> &Outs,
225 const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
226 SelectionDAG &DAG) const;
228 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
229 std::vector<SDValue> &Ops,
230 SelectionDAG &DAG) const;
232 NVPTXTargetMachine *nvTM;
234 // PTX always uses 32-bit shift amounts
235 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
237 virtual bool shouldSplitVectorType(EVT VT) const override;
240 const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
242 SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx,
243 EVT = MVT::i32) const;
244 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
245 SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
247 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
249 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
250 SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
252 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
253 SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
254 SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
256 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
257 SelectionDAG &DAG) const;
259 unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS,
260 Type *Ty, unsigned Idx) const;
264 #endif // NVPTXISELLOWERING_H