1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef NVPTXISELLOWERING_H
16 #define NVPTXISELLOWERING_H
19 #include "NVPTXSubtarget.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
40 StoreParamS32, // to sext and store a <32bit value, not used currently
41 StoreParamU32, // to zext and store a <32bit value, not used currently
63 LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
74 //===--------------------------------------------------------------------===//
75 // TargetLowering Implementation
76 //===--------------------------------------------------------------------===//
77 class NVPTXTargetLowering : public TargetLowering {
79 explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
80 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
84 SelectionDAG &DAG) const;
86 virtual const char *getTargetNodeName(unsigned Opcode) const;
88 bool isTypeSupportedInIntrinsic(MVT VT) const;
90 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
91 unsigned Intrinsic) const;
93 /// isLegalAddressingMode - Return true if the addressing mode represented
94 /// by AM is legal for this target, for a load/store of the specified type
95 /// Used to guide target specific optimizations, like loop strength
96 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
97 /// address mode (CodeGenPrepare.cpp)
98 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
100 /// getFunctionAlignment - Return the Log2 alignment of this function.
101 virtual unsigned getFunctionAlignment(const Function *F) const;
103 virtual EVT getSetCCResultType(EVT VT) const {
105 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
109 ConstraintType getConstraintType(const std::string &Constraint) const;
110 std::pair<unsigned, const TargetRegisterClass *>
111 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
113 virtual SDValue LowerFormalArguments(
114 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
115 const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG,
116 SmallVectorImpl<SDValue> &InVals) const;
119 LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const;
121 std::string getPrototype(Type *, const ArgListTy &,
122 const SmallVectorImpl<ISD::OutputArg> &,
123 unsigned retAlignment) const;
126 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
127 const SmallVectorImpl<ISD::OutputArg> &Outs,
128 const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl,
129 SelectionDAG &DAG) const;
131 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
132 std::vector<SDValue> &Ops,
133 SelectionDAG &DAG) const;
135 NVPTXTargetMachine *nvTM;
137 // PTX always uses 32-bit shift amounts
138 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
140 virtual bool shouldSplitVectorElementType(EVT VT) const;
143 const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
145 SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx,
146 EVT = MVT::i32) const;
147 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT = MVT::i32) const;
148 SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
150 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
152 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
153 SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
155 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
159 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
160 SelectionDAG &DAG) const;
164 #endif // NVPTXISELLOWERING_H