1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef NVPTXISELLOWERING_H
16 #define NVPTXISELLOWERING_H
19 #include "NVPTXSubtarget.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
26 // Start the numbering from where ISD NodeType finishes.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
44 StoreParamS32, // to sext and store a <32bit value, not used currently
45 StoreParamU32, // to zext and store a <32bit value, not used currently
69 LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
80 //===--------------------------------------------------------------------===//
81 // TargetLowering Implementation
82 //===--------------------------------------------------------------------===//
83 class NVPTXTargetLowering : public TargetLowering {
85 explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
86 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
90 SelectionDAG &DAG) const;
92 virtual const char *getTargetNodeName(unsigned Opcode) const;
94 bool isTypeSupportedInIntrinsic(MVT VT) const;
96 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
97 unsigned Intrinsic) const;
99 /// isLegalAddressingMode - Return true if the addressing mode represented
100 /// by AM is legal for this target, for a load/store of the specified type
101 /// Used to guide target specific optimizations, like loop strength
102 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
103 /// address mode (CodeGenPrepare.cpp)
104 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
106 /// getFunctionAlignment - Return the Log2 alignment of this function.
107 virtual unsigned getFunctionAlignment(const Function *F) const;
109 virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const {
111 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
115 ConstraintType getConstraintType(const std::string &Constraint) const;
116 std::pair<unsigned, const TargetRegisterClass *>
117 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
119 virtual SDValue LowerFormalArguments(
120 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
121 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
122 SmallVectorImpl<SDValue> &InVals) const;
125 LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const;
127 std::string getPrototype(Type *, const ArgListTy &,
128 const SmallVectorImpl<ISD::OutputArg> &,
129 unsigned retAlignment) const;
132 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
133 const SmallVectorImpl<ISD::OutputArg> &Outs,
134 const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
135 SelectionDAG &DAG) const;
137 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
138 std::vector<SDValue> &Ops,
139 SelectionDAG &DAG) const;
141 NVPTXTargetMachine *nvTM;
143 // PTX always uses 32-bit shift amounts
144 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
146 virtual bool shouldSplitVectorElementType(EVT VT) const;
149 const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
151 SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx,
152 EVT = MVT::i32) const;
153 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
154 SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
156 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
158 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
159 SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
161 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
162 SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
163 SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
165 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
166 SelectionDAG &DAG) const;
170 #endif // NVPTXISELLOWERING_H