1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef NVPTXISELLOWERING_H
16 #define NVPTXISELLOWERING_H
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
25 // Start the numbering from where ISD NodeType finishes.
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
59 LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
73 StoreParamS32, // to sext and store a <32bit value, not used currently
74 StoreParamU32, // to zext and store a <32bit value, not used currently
90 Tex1DArrayFloatFloatLevel,
91 Tex1DArrayFloatFloatGrad,
94 Tex1DArrayI32FloatLevel,
95 Tex1DArrayI32FloatGrad,
105 Tex2DArrayFloatFloat,
106 Tex2DArrayFloatFloatLevel,
107 Tex2DArrayFloatFloatGrad,
110 Tex2DArrayI32FloatLevel,
111 Tex2DArrayI32FloatGrad,
114 Tex3DFloatFloatLevel,
121 // Surface intrinsics
136 Suld1DArrayV2I16Trap,
137 Suld1DArrayV2I32Trap,
139 Suld1DArrayV4I16Trap,
140 Suld1DArrayV4I32Trap,
156 Suld2DArrayV2I16Trap,
157 Suld2DArrayV2I32Trap,
159 Suld2DArrayV4I16Trap,
160 Suld2DArrayV4I32Trap,
174 class NVPTXSubtarget;
176 //===--------------------------------------------------------------------===//
177 // TargetLowering Implementation
178 //===--------------------------------------------------------------------===//
179 class NVPTXTargetLowering : public TargetLowering {
181 explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
182 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
184 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
185 SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
186 SelectionDAG &DAG) const;
188 const char *getTargetNodeName(unsigned Opcode) const override;
190 bool isTypeSupportedInIntrinsic(MVT VT) const;
192 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
193 unsigned Intrinsic) const override;
195 /// isLegalAddressingMode - Return true if the addressing mode represented
196 /// by AM is legal for this target, for a load/store of the specified type
197 /// Used to guide target specific optimizations, like loop strength
198 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
199 /// address mode (CodeGenPrepare.cpp)
200 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
202 /// getFunctionAlignment - Return the Log2 alignment of this function.
203 unsigned getFunctionAlignment(const Function *F) const;
205 EVT getSetCCResultType(LLVMContext &Ctx, EVT VT) const override {
207 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
212 getConstraintType(const std::string &Constraint) const override;
213 std::pair<unsigned, const TargetRegisterClass *>
214 getRegForInlineAsmConstraint(const std::string &Constraint,
215 MVT VT) const override;
217 SDValue LowerFormalArguments(
218 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
219 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
220 SmallVectorImpl<SDValue> &InVals) const override;
222 SDValue LowerCall(CallLoweringInfo &CLI,
223 SmallVectorImpl<SDValue> &InVals) const override;
225 std::string getPrototype(Type *, const ArgListTy &,
226 const SmallVectorImpl<ISD::OutputArg> &,
227 unsigned retAlignment,
228 const ImmutableCallSite *CS) const;
231 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
232 const SmallVectorImpl<ISD::OutputArg> &Outs,
233 const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
234 SelectionDAG &DAG) const override;
236 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
237 std::vector<SDValue> &Ops,
238 SelectionDAG &DAG) const override;
240 NVPTXTargetMachine *nvTM;
242 // PTX always uses 32-bit shift amounts
243 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
245 bool shouldSplitVectorType(EVT VT) const override;
248 const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
250 SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx,
251 EVT = MVT::i32) const;
252 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
253 SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
255 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
257 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
258 SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
260 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
261 SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
262 SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
264 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
265 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
267 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
268 SelectionDAG &DAG) const override;
269 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
271 unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS,
272 Type *Ty, unsigned Idx) const;
276 #endif // NVPTXISELLOWERING_H