1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
16 #define LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
25 // Start the numbering from where ISD NodeType finishes.
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
59 LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
73 StoreParamS32, // to sext and store a <32bit value, not used currently
74 StoreParamU32, // to zext and store a <32bit value, not used currently
94 Tex1DArrayFloatFloatLevel,
95 Tex1DArrayFloatFloatGrad,
98 Tex1DArrayS32FloatLevel,
99 Tex1DArrayS32FloatGrad,
102 Tex1DArrayU32FloatLevel,
103 Tex1DArrayU32FloatGrad,
106 Tex2DFloatFloatLevel,
117 Tex2DArrayFloatFloat,
118 Tex2DArrayFloatFloatLevel,
119 Tex2DArrayFloatFloatGrad,
122 Tex2DArrayS32FloatLevel,
123 Tex2DArrayS32FloatGrad,
126 Tex2DArrayU32FloatLevel,
127 Tex2DArrayU32FloatGrad,
130 Tex3DFloatFloatLevel,
141 TexCubeFloatFloatLevel,
143 TexCubeS32FloatLevel,
145 TexCubeU32FloatLevel,
146 TexCubeArrayFloatFloat,
147 TexCubeArrayFloatFloatLevel,
148 TexCubeArrayS32Float,
149 TexCubeArrayS32FloatLevel,
150 TexCubeArrayU32Float,
151 TexCubeArrayU32FloatLevel,
164 TexUnified1DFloatS32,
165 TexUnified1DFloatFloat,
166 TexUnified1DFloatFloatLevel,
167 TexUnified1DFloatFloatGrad,
169 TexUnified1DS32Float,
170 TexUnified1DS32FloatLevel,
171 TexUnified1DS32FloatGrad,
173 TexUnified1DU32Float,
174 TexUnified1DU32FloatLevel,
175 TexUnified1DU32FloatGrad,
176 TexUnified1DArrayFloatS32,
177 TexUnified1DArrayFloatFloat,
178 TexUnified1DArrayFloatFloatLevel,
179 TexUnified1DArrayFloatFloatGrad,
180 TexUnified1DArrayS32S32,
181 TexUnified1DArrayS32Float,
182 TexUnified1DArrayS32FloatLevel,
183 TexUnified1DArrayS32FloatGrad,
184 TexUnified1DArrayU32S32,
185 TexUnified1DArrayU32Float,
186 TexUnified1DArrayU32FloatLevel,
187 TexUnified1DArrayU32FloatGrad,
188 TexUnified2DFloatS32,
189 TexUnified2DFloatFloat,
190 TexUnified2DFloatFloatLevel,
191 TexUnified2DFloatFloatGrad,
193 TexUnified2DS32Float,
194 TexUnified2DS32FloatLevel,
195 TexUnified2DS32FloatGrad,
197 TexUnified2DU32Float,
198 TexUnified2DU32FloatLevel,
199 TexUnified2DU32FloatGrad,
200 TexUnified2DArrayFloatS32,
201 TexUnified2DArrayFloatFloat,
202 TexUnified2DArrayFloatFloatLevel,
203 TexUnified2DArrayFloatFloatGrad,
204 TexUnified2DArrayS32S32,
205 TexUnified2DArrayS32Float,
206 TexUnified2DArrayS32FloatLevel,
207 TexUnified2DArrayS32FloatGrad,
208 TexUnified2DArrayU32S32,
209 TexUnified2DArrayU32Float,
210 TexUnified2DArrayU32FloatLevel,
211 TexUnified2DArrayU32FloatGrad,
212 TexUnified3DFloatS32,
213 TexUnified3DFloatFloat,
214 TexUnified3DFloatFloatLevel,
215 TexUnified3DFloatFloatGrad,
217 TexUnified3DS32Float,
218 TexUnified3DS32FloatLevel,
219 TexUnified3DS32FloatGrad,
221 TexUnified3DU32Float,
222 TexUnified3DU32FloatLevel,
223 TexUnified3DU32FloatGrad,
224 TexUnifiedCubeFloatFloat,
225 TexUnifiedCubeFloatFloatLevel,
226 TexUnifiedCubeS32Float,
227 TexUnifiedCubeS32FloatLevel,
228 TexUnifiedCubeU32Float,
229 TexUnifiedCubeU32FloatLevel,
230 TexUnifiedCubeArrayFloatFloat,
231 TexUnifiedCubeArrayFloatFloatLevel,
232 TexUnifiedCubeArrayS32Float,
233 TexUnifiedCubeArrayS32FloatLevel,
234 TexUnifiedCubeArrayU32Float,
235 TexUnifiedCubeArrayU32FloatLevel,
236 Tld4UnifiedR2DFloatFloat,
237 Tld4UnifiedG2DFloatFloat,
238 Tld4UnifiedB2DFloatFloat,
239 Tld4UnifiedA2DFloatFloat,
240 Tld4UnifiedR2DS64Float,
241 Tld4UnifiedG2DS64Float,
242 Tld4UnifiedB2DS64Float,
243 Tld4UnifiedA2DS64Float,
244 Tld4UnifiedR2DU64Float,
245 Tld4UnifiedG2DU64Float,
246 Tld4UnifiedB2DU64Float,
247 Tld4UnifiedA2DU64Float,
249 // Surface intrinsics
266 Suld1DArrayV2I8Clamp,
267 Suld1DArrayV2I16Clamp,
268 Suld1DArrayV2I32Clamp,
269 Suld1DArrayV2I64Clamp,
270 Suld1DArrayV4I8Clamp,
271 Suld1DArrayV4I16Clamp,
272 Suld1DArrayV4I32Clamp,
290 Suld2DArrayV2I8Clamp,
291 Suld2DArrayV2I16Clamp,
292 Suld2DArrayV2I32Clamp,
293 Suld2DArrayV2I64Clamp,
294 Suld2DArrayV4I8Clamp,
295 Suld2DArrayV4I16Clamp,
296 Suld2DArrayV4I32Clamp,
327 Suld1DArrayV2I16Trap,
328 Suld1DArrayV2I32Trap,
329 Suld1DArrayV2I64Trap,
331 Suld1DArrayV4I16Trap,
332 Suld1DArrayV4I32Trap,
351 Suld2DArrayV2I16Trap,
352 Suld2DArrayV2I32Trap,
353 Suld2DArrayV2I64Trap,
355 Suld2DArrayV4I16Trap,
356 Suld2DArrayV4I32Trap,
387 Suld1DArrayV2I16Zero,
388 Suld1DArrayV2I32Zero,
389 Suld1DArrayV2I64Zero,
391 Suld1DArrayV4I16Zero,
392 Suld1DArrayV4I32Zero,
411 Suld2DArrayV2I16Zero,
412 Suld2DArrayV2I32Zero,
413 Suld2DArrayV2I64Zero,
415 Suld2DArrayV4I16Zero,
416 Suld2DArrayV4I32Zero,
432 class NVPTXSubtarget;
434 //===--------------------------------------------------------------------===//
435 // TargetLowering Implementation
436 //===--------------------------------------------------------------------===//
437 class NVPTXTargetLowering : public TargetLowering {
439 explicit NVPTXTargetLowering(const NVPTXTargetMachine &TM,
440 const NVPTXSubtarget &STI);
441 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
443 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
444 SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
445 SelectionDAG &DAG) const;
447 const char *getTargetNodeName(unsigned Opcode) const override;
449 bool isTypeSupportedInIntrinsic(MVT VT) const;
451 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
452 unsigned Intrinsic) const override;
454 /// isLegalAddressingMode - Return true if the addressing mode represented
455 /// by AM is legal for this target, for a load/store of the specified type
456 /// Used to guide target specific optimizations, like loop strength
457 /// reduction (LoopStrengthReduce.cpp) and memory optimization for
458 /// address mode (CodeGenPrepare.cpp)
459 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
461 /// getFunctionAlignment - Return the Log2 alignment of this function.
462 unsigned getFunctionAlignment(const Function *F) const;
464 EVT getSetCCResultType(LLVMContext &Ctx, EVT VT) const override {
466 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
471 getConstraintType(const std::string &Constraint) const override;
472 std::pair<unsigned, const TargetRegisterClass *>
473 getRegForInlineAsmConstraint(const std::string &Constraint,
474 MVT VT) const override;
476 SDValue LowerFormalArguments(
477 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
478 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
479 SmallVectorImpl<SDValue> &InVals) const override;
481 SDValue LowerCall(CallLoweringInfo &CLI,
482 SmallVectorImpl<SDValue> &InVals) const override;
484 std::string getPrototype(Type *, const ArgListTy &,
485 const SmallVectorImpl<ISD::OutputArg> &,
486 unsigned retAlignment,
487 const ImmutableCallSite *CS) const;
490 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
491 const SmallVectorImpl<ISD::OutputArg> &Outs,
492 const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
493 SelectionDAG &DAG) const override;
495 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
496 std::vector<SDValue> &Ops,
497 SelectionDAG &DAG) const override;
499 const NVPTXTargetMachine *nvTM;
501 // PTX always uses 32-bit shift amounts
502 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
504 TargetLoweringBase::LegalizeTypeAction
505 getPreferredVectorAction(EVT VT) const override;
507 bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const;
509 bool isFMAFasterThanFMulAndFAdd(EVT) const override { return true; }
511 bool enableAggressiveFMAFusion(EVT VT) const override { return true; }
514 const NVPTXSubtarget &STI; // cache the subtarget here
516 SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx,
517 EVT = MVT::i32) const;
518 SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
519 SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
521 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
523 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
524 SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
526 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
527 SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
528 SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
530 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
531 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
533 SDValue LowerSelect(SDValue Op, SelectionDAG &DAG) const;
535 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
536 SelectionDAG &DAG) const override;
537 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
539 unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS,
540 Type *Ty, unsigned Idx) const;