1 //===- NVPTXInstrInfo.cpp - NVPTX Instruction Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the NVPTX implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "NVPTXInstrInfo.h"
16 #include "NVPTXTargetMachine.h"
17 #define GET_INSTRINFO_CTOR
18 #include "NVPTXGenInstrInfo.inc"
19 #include "llvm/IR/Function.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 // FIXME: Add the subtarget support on this constructor.
29 NVPTXInstrInfo::NVPTXInstrInfo(NVPTXTargetMachine &tm)
30 : NVPTXGenInstrInfo(), TM(tm), RegInfo(*this, *TM.getSubtargetImpl()) {}
32 void NVPTXInstrInfo::copyPhysReg(
33 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
34 unsigned DestReg, unsigned SrcReg, bool KillSrc) const {
35 if (NVPTX::Int32RegsRegClass.contains(DestReg) &&
36 NVPTX::Int32RegsRegClass.contains(SrcReg))
37 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg)
38 .addReg(SrcReg, getKillRegState(KillSrc));
39 else if (NVPTX::Int8RegsRegClass.contains(DestReg) &&
40 NVPTX::Int8RegsRegClass.contains(SrcReg))
41 BuildMI(MBB, I, DL, get(NVPTX::IMOV8rr), DestReg)
42 .addReg(SrcReg, getKillRegState(KillSrc));
43 else if (NVPTX::Int1RegsRegClass.contains(DestReg) &&
44 NVPTX::Int1RegsRegClass.contains(SrcReg))
45 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg)
46 .addReg(SrcReg, getKillRegState(KillSrc));
47 else if (NVPTX::Float32RegsRegClass.contains(DestReg) &&
48 NVPTX::Float32RegsRegClass.contains(SrcReg))
49 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg)
50 .addReg(SrcReg, getKillRegState(KillSrc));
51 else if (NVPTX::Int16RegsRegClass.contains(DestReg) &&
52 NVPTX::Int16RegsRegClass.contains(SrcReg))
53 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg)
54 .addReg(SrcReg, getKillRegState(KillSrc));
55 else if (NVPTX::Int64RegsRegClass.contains(DestReg) &&
56 NVPTX::Int64RegsRegClass.contains(SrcReg))
57 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg)
58 .addReg(SrcReg, getKillRegState(KillSrc));
59 else if (NVPTX::Float64RegsRegClass.contains(DestReg) &&
60 NVPTX::Float64RegsRegClass.contains(SrcReg))
61 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg)
62 .addReg(SrcReg, getKillRegState(KillSrc));
64 llvm_unreachable("Don't know how to copy a register");
68 bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
69 unsigned &DestReg) const {
70 // Look for the appropriate part of TSFlags
74 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
75 isMove = (TSFlags == 1);
78 MachineOperand dest = MI.getOperand(0);
79 MachineOperand src = MI.getOperand(1);
80 assert(dest.isReg() && "dest of a movrr is not a reg");
81 assert(src.isReg() && "src of a movrr is not a reg");
83 SrcReg = src.getReg();
84 DestReg = dest.getReg();
91 bool NVPTXInstrInfo::isReadSpecialReg(MachineInstr &MI) const {
92 switch (MI.getOpcode()) {
95 case NVPTX::INT_PTX_SREG_NTID_X:
96 case NVPTX::INT_PTX_SREG_NTID_Y:
97 case NVPTX::INT_PTX_SREG_NTID_Z:
98 case NVPTX::INT_PTX_SREG_TID_X:
99 case NVPTX::INT_PTX_SREG_TID_Y:
100 case NVPTX::INT_PTX_SREG_TID_Z:
101 case NVPTX::INT_PTX_SREG_CTAID_X:
102 case NVPTX::INT_PTX_SREG_CTAID_Y:
103 case NVPTX::INT_PTX_SREG_CTAID_Z:
104 case NVPTX::INT_PTX_SREG_NCTAID_X:
105 case NVPTX::INT_PTX_SREG_NCTAID_Y:
106 case NVPTX::INT_PTX_SREG_NCTAID_Z:
107 case NVPTX::INT_PTX_SREG_WARPSIZE:
112 bool NVPTXInstrInfo::isLoadInstr(const MachineInstr &MI,
113 unsigned &AddrSpace) const {
116 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
117 isLoad = (TSFlags == 1);
119 AddrSpace = getLdStCodeAddrSpace(MI);
123 bool NVPTXInstrInfo::isStoreInstr(const MachineInstr &MI,
124 unsigned &AddrSpace) const {
125 bool isStore = false;
127 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
128 isStore = (TSFlags == 1);
130 AddrSpace = getLdStCodeAddrSpace(MI);
134 bool NVPTXInstrInfo::CanTailMerge(const MachineInstr *MI) const {
135 unsigned addrspace = 0;
136 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS)
138 if (isLoadInstr(*MI, addrspace))
139 if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
141 if (isStoreInstr(*MI, addrspace))
142 if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
147 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
148 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
149 /// implemented for a target). Upon success, this returns false and returns
150 /// with the following information in various cases:
152 /// 1. If this block ends with no branches (it just falls through to its succ)
153 /// just return false, leaving TBB/FBB null.
154 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
155 /// the destination block.
156 /// 3. If this block ends with an conditional branch and it falls through to
157 /// an successor block, it sets TBB to be the branch destination block and a
158 /// list of operands that evaluate the condition. These
159 /// operands can be passed to other TargetInstrInfo methods to create new
161 /// 4. If this block ends with an conditional branch and an unconditional
162 /// block, it returns the 'true' destination in TBB, the 'false' destination
163 /// in FBB, and a list of operands that evaluate the condition. These
164 /// operands can be passed to other TargetInstrInfo methods to create new
167 /// Note that RemoveBranch and InsertBranch must be implemented to support
168 /// cases where this method returns success.
170 bool NVPTXInstrInfo::AnalyzeBranch(
171 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
172 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {
173 // If the block has no terminators, it just falls into the block after it.
174 MachineBasicBlock::iterator I = MBB.end();
175 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
178 // Get the last instruction in the block.
179 MachineInstr *LastInst = I;
181 // If there is only one terminator instruction, process it.
182 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
183 if (LastInst->getOpcode() == NVPTX::GOTO) {
184 TBB = LastInst->getOperand(0).getMBB();
186 } else if (LastInst->getOpcode() == NVPTX::CBranch) {
187 // Block ends with fall-through condbranch.
188 TBB = LastInst->getOperand(1).getMBB();
189 Cond.push_back(LastInst->getOperand(0));
192 // Otherwise, don't know what this is.
196 // Get the instruction before it if it's a terminator.
197 MachineInstr *SecondLastInst = I;
199 // If there are three terminators, we don't know what sort of block this is.
200 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
203 // If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.
204 if (SecondLastInst->getOpcode() == NVPTX::CBranch &&
205 LastInst->getOpcode() == NVPTX::GOTO) {
206 TBB = SecondLastInst->getOperand(1).getMBB();
207 Cond.push_back(SecondLastInst->getOperand(0));
208 FBB = LastInst->getOperand(0).getMBB();
212 // If the block ends with two NVPTX:GOTOs, handle it. The second one is not
213 // executed, so remove it.
214 if (SecondLastInst->getOpcode() == NVPTX::GOTO &&
215 LastInst->getOpcode() == NVPTX::GOTO) {
216 TBB = SecondLastInst->getOperand(0).getMBB();
219 I->eraseFromParent();
223 // Otherwise, can't handle this.
227 unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
228 MachineBasicBlock::iterator I = MBB.end();
229 if (I == MBB.begin())
232 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
235 // Remove the branch.
236 I->eraseFromParent();
240 if (I == MBB.begin())
243 if (I->getOpcode() != NVPTX::CBranch)
246 // Remove the branch.
247 I->eraseFromParent();
251 unsigned NVPTXInstrInfo::InsertBranch(
252 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
253 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
254 // Shouldn't be a fall through.
255 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
256 assert((Cond.size() == 1 || Cond.size() == 0) &&
257 "NVPTX branch conditions have two components!");
261 if (Cond.empty()) // Unconditional branch
262 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
263 else // Conditional branch
264 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
269 // Two-way Conditional Branch.
270 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
271 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);