1 //===- NVPTXInstrInfo.cpp - NVPTX Instruction Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the NVPTX implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "NVPTXInstrInfo.h"
16 #include "NVPTXTargetMachine.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/IR/Function.h"
25 #define GET_INSTRINFO_CTOR_DTOR
26 #include "NVPTXGenInstrInfo.inc"
28 // Pin the vtable to this file.
29 void NVPTXInstrInfo::anchor() {}
31 NVPTXInstrInfo::NVPTXInstrInfo() : NVPTXGenInstrInfo(), RegInfo() {}
33 void NVPTXInstrInfo::copyPhysReg(
34 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
35 unsigned DestReg, unsigned SrcReg, bool KillSrc) const {
36 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
40 if (DestRC->getSize() != SrcRC->getSize())
41 report_fatal_error("Copy one register into another with a different width");
44 if (DestRC == &NVPTX::Int1RegsRegClass) {
46 } else if (DestRC == &NVPTX::Int16RegsRegClass) {
48 } else if (DestRC == &NVPTX::Int32RegsRegClass) {
49 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
50 : NVPTX::BITCONVERT_32_F2I);
51 } else if (DestRC == &NVPTX::Int64RegsRegClass) {
52 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
53 : NVPTX::BITCONVERT_64_F2I);
54 } else if (DestRC == &NVPTX::Float32RegsRegClass) {
55 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
56 : NVPTX::BITCONVERT_32_I2F);
57 } else if (DestRC == &NVPTX::Float64RegsRegClass) {
58 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
59 : NVPTX::BITCONVERT_64_I2F);
61 llvm_unreachable("Bad register copy");
63 BuildMI(MBB, I, DL, get(Op), DestReg)
64 .addReg(SrcReg, getKillRegState(KillSrc));
67 bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
68 unsigned &DestReg) const {
69 // Look for the appropriate part of TSFlags
73 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
74 isMove = (TSFlags == 1);
77 MachineOperand dest = MI.getOperand(0);
78 MachineOperand src = MI.getOperand(1);
79 assert(dest.isReg() && "dest of a movrr is not a reg");
80 assert(src.isReg() && "src of a movrr is not a reg");
82 SrcReg = src.getReg();
83 DestReg = dest.getReg();
90 bool NVPTXInstrInfo::isLoadInstr(const MachineInstr &MI,
91 unsigned &AddrSpace) const {
94 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
95 isLoad = (TSFlags == 1);
97 AddrSpace = getLdStCodeAddrSpace(MI);
101 bool NVPTXInstrInfo::isStoreInstr(const MachineInstr &MI,
102 unsigned &AddrSpace) const {
103 bool isStore = false;
105 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
106 isStore = (TSFlags == 1);
108 AddrSpace = getLdStCodeAddrSpace(MI);
112 bool NVPTXInstrInfo::CanTailMerge(const MachineInstr *MI) const {
113 unsigned addrspace = 0;
114 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS)
116 if (isLoadInstr(*MI, addrspace))
117 if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
119 if (isStoreInstr(*MI, addrspace))
120 if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
125 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
126 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
127 /// implemented for a target). Upon success, this returns false and returns
128 /// with the following information in various cases:
130 /// 1. If this block ends with no branches (it just falls through to its succ)
131 /// just return false, leaving TBB/FBB null.
132 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
133 /// the destination block.
134 /// 3. If this block ends with an conditional branch and it falls through to
135 /// an successor block, it sets TBB to be the branch destination block and a
136 /// list of operands that evaluate the condition. These
137 /// operands can be passed to other TargetInstrInfo methods to create new
139 /// 4. If this block ends with an conditional branch and an unconditional
140 /// block, it returns the 'true' destination in TBB, the 'false' destination
141 /// in FBB, and a list of operands that evaluate the condition. These
142 /// operands can be passed to other TargetInstrInfo methods to create new
145 /// Note that RemoveBranch and InsertBranch must be implemented to support
146 /// cases where this method returns success.
148 bool NVPTXInstrInfo::AnalyzeBranch(
149 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
150 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {
151 // If the block has no terminators, it just falls into the block after it.
152 MachineBasicBlock::iterator I = MBB.end();
153 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
156 // Get the last instruction in the block.
157 MachineInstr *LastInst = I;
159 // If there is only one terminator instruction, process it.
160 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
161 if (LastInst->getOpcode() == NVPTX::GOTO) {
162 TBB = LastInst->getOperand(0).getMBB();
164 } else if (LastInst->getOpcode() == NVPTX::CBranch) {
165 // Block ends with fall-through condbranch.
166 TBB = LastInst->getOperand(1).getMBB();
167 Cond.push_back(LastInst->getOperand(0));
170 // Otherwise, don't know what this is.
174 // Get the instruction before it if it's a terminator.
175 MachineInstr *SecondLastInst = I;
177 // If there are three terminators, we don't know what sort of block this is.
178 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
181 // If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.
182 if (SecondLastInst->getOpcode() == NVPTX::CBranch &&
183 LastInst->getOpcode() == NVPTX::GOTO) {
184 TBB = SecondLastInst->getOperand(1).getMBB();
185 Cond.push_back(SecondLastInst->getOperand(0));
186 FBB = LastInst->getOperand(0).getMBB();
190 // If the block ends with two NVPTX:GOTOs, handle it. The second one is not
191 // executed, so remove it.
192 if (SecondLastInst->getOpcode() == NVPTX::GOTO &&
193 LastInst->getOpcode() == NVPTX::GOTO) {
194 TBB = SecondLastInst->getOperand(0).getMBB();
197 I->eraseFromParent();
201 // Otherwise, can't handle this.
205 unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
206 MachineBasicBlock::iterator I = MBB.end();
207 if (I == MBB.begin())
210 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
213 // Remove the branch.
214 I->eraseFromParent();
218 if (I == MBB.begin())
221 if (I->getOpcode() != NVPTX::CBranch)
224 // Remove the branch.
225 I->eraseFromParent();
229 unsigned NVPTXInstrInfo::InsertBranch(
230 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
231 ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
232 // Shouldn't be a fall through.
233 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
234 assert((Cond.size() == 1 || Cond.size() == 0) &&
235 "NVPTX branch conditions have two components!");
239 if (Cond.empty()) // Unconditional branch
240 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
241 else // Conditional branch
242 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
247 // Two-way Conditional Branch.
248 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
249 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);