1 //===- NVPTXInstrInfo.cpp - NVPTX Instruction Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the NVPTX implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "NVPTXInstrInfo.h"
16 #include "NVPTXTargetMachine.h"
17 #define GET_INSTRINFO_CTOR
18 #include "NVPTXGenInstrInfo.inc"
19 #include "llvm/IR/Function.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 // FIXME: Add the subtarget support on this constructor.
29 NVPTXInstrInfo::NVPTXInstrInfo(NVPTXTargetMachine &tm)
30 : NVPTXGenInstrInfo(), TM(tm), RegInfo(*TM.getSubtargetImpl()) {}
32 void NVPTXInstrInfo::copyPhysReg(
33 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
34 unsigned DestReg, unsigned SrcReg, bool KillSrc) const {
35 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
36 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
37 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
40 report_fatal_error("Attempted to created cross-class register copy");
42 if (DestRC == &NVPTX::Int32RegsRegClass)
43 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg)
44 .addReg(SrcReg, getKillRegState(KillSrc));
45 else if (DestRC == &NVPTX::Int1RegsRegClass)
46 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg)
47 .addReg(SrcReg, getKillRegState(KillSrc));
48 else if (DestRC == &NVPTX::Float32RegsRegClass)
49 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg)
50 .addReg(SrcReg, getKillRegState(KillSrc));
51 else if (DestRC == &NVPTX::Int16RegsRegClass)
52 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg)
53 .addReg(SrcReg, getKillRegState(KillSrc));
54 else if (DestRC == &NVPTX::Int64RegsRegClass)
55 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg)
56 .addReg(SrcReg, getKillRegState(KillSrc));
57 else if (DestRC == &NVPTX::Float64RegsRegClass)
58 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg)
59 .addReg(SrcReg, getKillRegState(KillSrc));
61 llvm_unreachable("Bad register copy");
65 bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
66 unsigned &DestReg) const {
67 // Look for the appropriate part of TSFlags
71 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
72 isMove = (TSFlags == 1);
75 MachineOperand dest = MI.getOperand(0);
76 MachineOperand src = MI.getOperand(1);
77 assert(dest.isReg() && "dest of a movrr is not a reg");
78 assert(src.isReg() && "src of a movrr is not a reg");
80 SrcReg = src.getReg();
81 DestReg = dest.getReg();
88 bool NVPTXInstrInfo::isReadSpecialReg(MachineInstr &MI) const {
89 switch (MI.getOpcode()) {
92 case NVPTX::INT_PTX_SREG_NTID_X:
93 case NVPTX::INT_PTX_SREG_NTID_Y:
94 case NVPTX::INT_PTX_SREG_NTID_Z:
95 case NVPTX::INT_PTX_SREG_TID_X:
96 case NVPTX::INT_PTX_SREG_TID_Y:
97 case NVPTX::INT_PTX_SREG_TID_Z:
98 case NVPTX::INT_PTX_SREG_CTAID_X:
99 case NVPTX::INT_PTX_SREG_CTAID_Y:
100 case NVPTX::INT_PTX_SREG_CTAID_Z:
101 case NVPTX::INT_PTX_SREG_NCTAID_X:
102 case NVPTX::INT_PTX_SREG_NCTAID_Y:
103 case NVPTX::INT_PTX_SREG_NCTAID_Z:
104 case NVPTX::INT_PTX_SREG_WARPSIZE:
109 bool NVPTXInstrInfo::isLoadInstr(const MachineInstr &MI,
110 unsigned &AddrSpace) const {
113 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
114 isLoad = (TSFlags == 1);
116 AddrSpace = getLdStCodeAddrSpace(MI);
120 bool NVPTXInstrInfo::isStoreInstr(const MachineInstr &MI,
121 unsigned &AddrSpace) const {
122 bool isStore = false;
124 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
125 isStore = (TSFlags == 1);
127 AddrSpace = getLdStCodeAddrSpace(MI);
131 bool NVPTXInstrInfo::CanTailMerge(const MachineInstr *MI) const {
132 unsigned addrspace = 0;
133 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS)
135 if (isLoadInstr(*MI, addrspace))
136 if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
138 if (isStoreInstr(*MI, addrspace))
139 if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
144 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
145 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
146 /// implemented for a target). Upon success, this returns false and returns
147 /// with the following information in various cases:
149 /// 1. If this block ends with no branches (it just falls through to its succ)
150 /// just return false, leaving TBB/FBB null.
151 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
152 /// the destination block.
153 /// 3. If this block ends with an conditional branch and it falls through to
154 /// an successor block, it sets TBB to be the branch destination block and a
155 /// list of operands that evaluate the condition. These
156 /// operands can be passed to other TargetInstrInfo methods to create new
158 /// 4. If this block ends with an conditional branch and an unconditional
159 /// block, it returns the 'true' destination in TBB, the 'false' destination
160 /// in FBB, and a list of operands that evaluate the condition. These
161 /// operands can be passed to other TargetInstrInfo methods to create new
164 /// Note that RemoveBranch and InsertBranch must be implemented to support
165 /// cases where this method returns success.
167 bool NVPTXInstrInfo::AnalyzeBranch(
168 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
169 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {
170 // If the block has no terminators, it just falls into the block after it.
171 MachineBasicBlock::iterator I = MBB.end();
172 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
175 // Get the last instruction in the block.
176 MachineInstr *LastInst = I;
178 // If there is only one terminator instruction, process it.
179 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
180 if (LastInst->getOpcode() == NVPTX::GOTO) {
181 TBB = LastInst->getOperand(0).getMBB();
183 } else if (LastInst->getOpcode() == NVPTX::CBranch) {
184 // Block ends with fall-through condbranch.
185 TBB = LastInst->getOperand(1).getMBB();
186 Cond.push_back(LastInst->getOperand(0));
189 // Otherwise, don't know what this is.
193 // Get the instruction before it if it's a terminator.
194 MachineInstr *SecondLastInst = I;
196 // If there are three terminators, we don't know what sort of block this is.
197 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
200 // If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.
201 if (SecondLastInst->getOpcode() == NVPTX::CBranch &&
202 LastInst->getOpcode() == NVPTX::GOTO) {
203 TBB = SecondLastInst->getOperand(1).getMBB();
204 Cond.push_back(SecondLastInst->getOperand(0));
205 FBB = LastInst->getOperand(0).getMBB();
209 // If the block ends with two NVPTX:GOTOs, handle it. The second one is not
210 // executed, so remove it.
211 if (SecondLastInst->getOpcode() == NVPTX::GOTO &&
212 LastInst->getOpcode() == NVPTX::GOTO) {
213 TBB = SecondLastInst->getOperand(0).getMBB();
216 I->eraseFromParent();
220 // Otherwise, can't handle this.
224 unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
225 MachineBasicBlock::iterator I = MBB.end();
226 if (I == MBB.begin())
229 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
232 // Remove the branch.
233 I->eraseFromParent();
237 if (I == MBB.begin())
240 if (I->getOpcode() != NVPTX::CBranch)
243 // Remove the branch.
244 I->eraseFromParent();
248 unsigned NVPTXInstrInfo::InsertBranch(
249 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
250 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
251 // Shouldn't be a fall through.
252 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
253 assert((Cond.size() == 1 || Cond.size() == 0) &&
254 "NVPTX branch conditions have two components!");
258 if (Cond.empty()) // Unconditional branch
259 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
260 else // Conditional branch
261 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
266 // Two-way Conditional Branch.
267 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
268 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);