1 //===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the niversity of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the NVPTX implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef NVPTXINSTRUCTIONINFO_H
15 #define NVPTXINSTRUCTIONINFO_H
18 #include "NVPTXRegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "NVPTXGenInstrInfo.inc"
26 class NVPTXInstrInfo : public NVPTXGenInstrInfo {
27 NVPTXTargetMachine &TM;
28 const NVPTXRegisterInfo RegInfo;
29 virtual void anchor();
31 explicit NVPTXInstrInfo(NVPTXTargetMachine &TM);
33 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
35 /* The following virtual functions are used in register allocation.
36 * They are not implemented because the existing interface and the logic
37 * at the caller side do not work for the elementized vector load and store.
39 * virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
40 * int &FrameIndex) const;
41 * virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
42 * int &FrameIndex) const;
43 * virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
44 * MachineBasicBlock::iterator MBBI,
45 * unsigned SrcReg, bool isKill, int FrameIndex,
46 * const TargetRegisterClass *RC) const;
47 * virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
48 * MachineBasicBlock::iterator MBBI,
49 * unsigned DestReg, int FrameIndex,
50 * const TargetRegisterClass *RC) const;
54 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
55 unsigned DestReg, unsigned SrcReg, bool KillSrc) const override;
56 virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
57 unsigned &DestReg) const;
58 bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
59 bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
60 bool isReadSpecialReg(MachineInstr &MI) const;
62 virtual bool CanTailMerge(const MachineInstr *MI) const;
65 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
66 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override;
67 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
68 unsigned InsertBranch(
69 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
70 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override;
71 unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const {
72 return MI.getOperand(2).getImm();