1 //===- NVPTXInstrInfo.td - NVPTX Instruction defs -------------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PTX instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "NVPTXInstrFormats.td"
17 def NOP : NVPTXInst<(outs), (ins), "", []>;
19 // List of vector specific properties
20 def isVecLD : VecInstTypeEnum<1>;
21 def isVecST : VecInstTypeEnum<2>;
22 def isVecBuild : VecInstTypeEnum<3>;
23 def isVecShuffle : VecInstTypeEnum<4>;
24 def isVecExtract : VecInstTypeEnum<5>;
25 def isVecInsert : VecInstTypeEnum<6>;
26 def isVecDest : VecInstTypeEnum<7>;
27 def isVecOther : VecInstTypeEnum<15>;
29 //===----------------------------------------------------------------------===//
30 // NVPTX Operand Definitions.
31 //===----------------------------------------------------------------------===//
33 def brtarget : Operand<OtherVT>;
35 // CVT conversion modes
36 // These must match the enum in NVPTX.h
37 def CvtNONE : PatLeaf<(i32 0x0)>;
38 def CvtRNI : PatLeaf<(i32 0x1)>;
39 def CvtRZI : PatLeaf<(i32 0x2)>;
40 def CvtRMI : PatLeaf<(i32 0x3)>;
41 def CvtRPI : PatLeaf<(i32 0x4)>;
42 def CvtRN : PatLeaf<(i32 0x5)>;
43 def CvtRZ : PatLeaf<(i32 0x6)>;
44 def CvtRM : PatLeaf<(i32 0x7)>;
45 def CvtRP : PatLeaf<(i32 0x8)>;
47 def CvtNONE_FTZ : PatLeaf<(i32 0x10)>;
48 def CvtRNI_FTZ : PatLeaf<(i32 0x11)>;
49 def CvtRZI_FTZ : PatLeaf<(i32 0x12)>;
50 def CvtRMI_FTZ : PatLeaf<(i32 0x13)>;
51 def CvtRPI_FTZ : PatLeaf<(i32 0x14)>;
52 def CvtRN_FTZ : PatLeaf<(i32 0x15)>;
53 def CvtRZ_FTZ : PatLeaf<(i32 0x16)>;
54 def CvtRM_FTZ : PatLeaf<(i32 0x17)>;
55 def CvtRP_FTZ : PatLeaf<(i32 0x18)>;
57 def CvtSAT : PatLeaf<(i32 0x20)>;
58 def CvtSAT_FTZ : PatLeaf<(i32 0x30)>;
60 def CvtMode : Operand<i32> {
61 let PrintMethod = "printCvtMode";
65 // These must match the enum in NVPTX.h
66 def CmpEQ : PatLeaf<(i32 0)>;
67 def CmpNE : PatLeaf<(i32 1)>;
68 def CmpLT : PatLeaf<(i32 2)>;
69 def CmpLE : PatLeaf<(i32 3)>;
70 def CmpGT : PatLeaf<(i32 4)>;
71 def CmpGE : PatLeaf<(i32 5)>;
72 def CmpLO : PatLeaf<(i32 6)>;
73 def CmpLS : PatLeaf<(i32 7)>;
74 def CmpHI : PatLeaf<(i32 8)>;
75 def CmpHS : PatLeaf<(i32 9)>;
76 def CmpEQU : PatLeaf<(i32 10)>;
77 def CmpNEU : PatLeaf<(i32 11)>;
78 def CmpLTU : PatLeaf<(i32 12)>;
79 def CmpLEU : PatLeaf<(i32 13)>;
80 def CmpGTU : PatLeaf<(i32 14)>;
81 def CmpGEU : PatLeaf<(i32 15)>;
82 def CmpNUM : PatLeaf<(i32 16)>;
83 def CmpNAN : PatLeaf<(i32 17)>;
85 def CmpEQ_FTZ : PatLeaf<(i32 0x100)>;
86 def CmpNE_FTZ : PatLeaf<(i32 0x101)>;
87 def CmpLT_FTZ : PatLeaf<(i32 0x102)>;
88 def CmpLE_FTZ : PatLeaf<(i32 0x103)>;
89 def CmpGT_FTZ : PatLeaf<(i32 0x104)>;
90 def CmpGE_FTZ : PatLeaf<(i32 0x105)>;
91 def CmpLO_FTZ : PatLeaf<(i32 0x106)>;
92 def CmpLS_FTZ : PatLeaf<(i32 0x107)>;
93 def CmpHI_FTZ : PatLeaf<(i32 0x108)>;
94 def CmpHS_FTZ : PatLeaf<(i32 0x109)>;
95 def CmpEQU_FTZ : PatLeaf<(i32 0x10A)>;
96 def CmpNEU_FTZ : PatLeaf<(i32 0x10B)>;
97 def CmpLTU_FTZ : PatLeaf<(i32 0x10C)>;
98 def CmpLEU_FTZ : PatLeaf<(i32 0x10D)>;
99 def CmpGTU_FTZ : PatLeaf<(i32 0x10E)>;
100 def CmpGEU_FTZ : PatLeaf<(i32 0x10F)>;
101 def CmpNUM_FTZ : PatLeaf<(i32 0x110)>;
102 def CmpNAN_FTZ : PatLeaf<(i32 0x111)>;
104 def CmpMode : Operand<i32> {
105 let PrintMethod = "printCmpMode";
108 def F32ConstZero : Operand<f32>, PatLeaf<(f32 fpimm)>, SDNodeXForm<fpimm, [{
109 return CurDAG->getTargetConstantFP(0.0, MVT::f32);
111 def F32ConstOne : Operand<f32>, PatLeaf<(f32 fpimm)>, SDNodeXForm<fpimm, [{
112 return CurDAG->getTargetConstantFP(1.0, MVT::f32);
115 //===----------------------------------------------------------------------===//
116 // NVPTX Instruction Predicate Definitions
117 //===----------------------------------------------------------------------===//
120 def hasAtomRedG32 : Predicate<"Subtarget.hasAtomRedG32()">;
121 def hasAtomRedS32 : Predicate<"Subtarget.hasAtomRedS32()">;
122 def hasAtomRedGen32 : Predicate<"Subtarget.hasAtomRedGen32()">;
123 def useAtomRedG32forGen32 :
124 Predicate<"!Subtarget.hasAtomRedGen32() && Subtarget.hasAtomRedG32()">;
125 def hasBrkPt : Predicate<"Subtarget.hasBrkPt()">;
126 def hasAtomRedG64 : Predicate<"Subtarget.hasAtomRedG64()">;
127 def hasAtomRedS64 : Predicate<"Subtarget.hasAtomRedS64()">;
128 def hasAtomRedGen64 : Predicate<"Subtarget.hasAtomRedGen64()">;
129 def useAtomRedG64forGen64 :
130 Predicate<"!Subtarget.hasAtomRedGen64() && Subtarget.hasAtomRedG64()">;
131 def hasAtomAddF32 : Predicate<"Subtarget.hasAtomAddF32()">;
132 def hasVote : Predicate<"Subtarget.hasVote()">;
133 def hasDouble : Predicate<"Subtarget.hasDouble()">;
134 def reqPTX20 : Predicate<"Subtarget.reqPTX20()">;
135 def hasLDG : Predicate<"Subtarget.hasLDG()">;
136 def hasLDU : Predicate<"Subtarget.hasLDU()">;
137 def hasGenericLdSt : Predicate<"Subtarget.hasGenericLdSt()">;
139 def doF32FTZ : Predicate<"UseF32FTZ==1">;
140 def doNoF32FTZ : Predicate<"UseF32FTZ==0">;
142 def doFMAF32 : Predicate<"doFMAF32">;
143 def doFMAF32_ftz : Predicate<"(doFMAF32 && UseF32FTZ)">;
144 def doFMAF32AGG : Predicate<"doFMAF32AGG">;
145 def doFMAF32AGG_ftz : Predicate<"(doFMAF32AGG && UseF32FTZ)">;
146 def doFMAF64 : Predicate<"doFMAF64">;
147 def doFMAF64AGG : Predicate<"doFMAF64AGG">;
148 def doFMADF32 : Predicate<"doFMADF32">;
149 def doFMADF32_ftz : Predicate<"(doFMADF32 && UseF32FTZ)">;
151 def doMulWide : Predicate<"doMulWide">;
153 def allowFMA : Predicate<"allowFMA">;
154 def allowFMA_ftz : Predicate<"(allowFMA && UseF32FTZ)">;
156 def do_DIVF32_APPROX : Predicate<"do_DIVF32_PREC==0">;
157 def do_DIVF32_FULL : Predicate<"do_DIVF32_PREC==1">;
159 def do_SQRTF32_APPROX : Predicate<"do_SQRTF32_PREC==0">;
160 def do_SQRTF32_RN : Predicate<"do_SQRTF32_PREC==1">;
162 def hasHWROT32 : Predicate<"Subtarget.hasHWROT32()">;
164 def true : Predicate<"1">;
167 //===----------------------------------------------------------------------===//
168 // Some Common Instruction Class Templates
169 //===----------------------------------------------------------------------===//
171 multiclass I3<string OpcStr, SDNode OpNode> {
172 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int64Regs:$b),
173 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
174 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
176 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i64imm:$b),
177 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
178 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
179 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
180 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
181 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
183 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
184 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
185 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
186 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
187 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
188 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
190 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
191 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
192 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
195 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
196 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
198 !strconcat(OpcStr, ".s32 \t$dst, $a, $b;"),
199 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
201 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
202 !strconcat(OpcStr, ".s32 \t$dst, $a, $b;"),
203 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
206 multiclass F3<string OpcStr, SDNode OpNode> {
207 def f64rr : NVPTXInst<(outs Float64Regs:$dst),
208 (ins Float64Regs:$a, Float64Regs:$b),
209 !strconcat(OpcStr, ".f64 \t$dst, $a, $b;"),
210 [(set Float64Regs:$dst,
211 (OpNode Float64Regs:$a, Float64Regs:$b))]>,
212 Requires<[allowFMA]>;
213 def f64ri : NVPTXInst<(outs Float64Regs:$dst),
214 (ins Float64Regs:$a, f64imm:$b),
215 !strconcat(OpcStr, ".f64 \t$dst, $a, $b;"),
216 [(set Float64Regs:$dst,
217 (OpNode Float64Regs:$a, fpimm:$b))]>,
218 Requires<[allowFMA]>;
219 def f32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
220 (ins Float32Regs:$a, Float32Regs:$b),
221 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a, $b;"),
222 [(set Float32Regs:$dst,
223 (OpNode Float32Regs:$a, Float32Regs:$b))]>,
224 Requires<[allowFMA_ftz]>;
225 def f32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
226 (ins Float32Regs:$a, f32imm:$b),
227 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a, $b;"),
228 [(set Float32Regs:$dst,
229 (OpNode Float32Regs:$a, fpimm:$b))]>,
230 Requires<[allowFMA_ftz]>;
231 def f32rr : NVPTXInst<(outs Float32Regs:$dst),
232 (ins Float32Regs:$a, Float32Regs:$b),
233 !strconcat(OpcStr, ".f32 \t$dst, $a, $b;"),
234 [(set Float32Regs:$dst,
235 (OpNode Float32Regs:$a, Float32Regs:$b))]>,
236 Requires<[allowFMA]>;
237 def f32ri : NVPTXInst<(outs Float32Regs:$dst),
238 (ins Float32Regs:$a, f32imm:$b),
239 !strconcat(OpcStr, ".f32 \t$dst, $a, $b;"),
240 [(set Float32Regs:$dst,
241 (OpNode Float32Regs:$a, fpimm:$b))]>,
242 Requires<[allowFMA]>;
245 multiclass F3_rn<string OpcStr, SDNode OpNode> {
246 def f64rr : NVPTXInst<(outs Float64Regs:$dst),
247 (ins Float64Regs:$a, Float64Regs:$b),
248 !strconcat(OpcStr, ".rn.f64 \t$dst, $a, $b;"),
249 [(set Float64Regs:$dst,
250 (OpNode Float64Regs:$a, Float64Regs:$b))]>;
251 def f64ri : NVPTXInst<(outs Float64Regs:$dst),
252 (ins Float64Regs:$a, f64imm:$b),
253 !strconcat(OpcStr, ".rn.f64 \t$dst, $a, $b;"),
254 [(set Float64Regs:$dst,
255 (OpNode Float64Regs:$a, fpimm:$b))]>;
256 def f32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
257 (ins Float32Regs:$a, Float32Regs:$b),
258 !strconcat(OpcStr, ".rn.ftz.f32 \t$dst, $a, $b;"),
259 [(set Float32Regs:$dst,
260 (OpNode Float32Regs:$a, Float32Regs:$b))]>,
261 Requires<[doF32FTZ]>;
262 def f32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
263 (ins Float32Regs:$a, f32imm:$b),
264 !strconcat(OpcStr, ".rn.ftz.f32 \t$dst, $a, $b;"),
265 [(set Float32Regs:$dst,
266 (OpNode Float32Regs:$a, fpimm:$b))]>,
267 Requires<[doF32FTZ]>;
268 def f32rr : NVPTXInst<(outs Float32Regs:$dst),
269 (ins Float32Regs:$a, Float32Regs:$b),
270 !strconcat(OpcStr, ".rn.f32 \t$dst, $a, $b;"),
271 [(set Float32Regs:$dst,
272 (OpNode Float32Regs:$a, Float32Regs:$b))]>;
273 def f32ri : NVPTXInst<(outs Float32Regs:$dst),
274 (ins Float32Regs:$a, f32imm:$b),
275 !strconcat(OpcStr, ".rn.f32 \t$dst, $a, $b;"),
276 [(set Float32Regs:$dst,
277 (OpNode Float32Regs:$a, fpimm:$b))]>;
280 multiclass F2<string OpcStr, SDNode OpNode> {
281 def f64 : NVPTXInst<(outs Float64Regs:$dst), (ins Float64Regs:$a),
282 !strconcat(OpcStr, ".f64 \t$dst, $a;"),
283 [(set Float64Regs:$dst, (OpNode Float64Regs:$a))]>;
284 def f32_ftz : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$a),
285 !strconcat(OpcStr, ".ftz.f32 \t$dst, $a;"),
286 [(set Float32Regs:$dst, (OpNode Float32Regs:$a))]>,
287 Requires<[doF32FTZ]>;
288 def f32 : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$a),
289 !strconcat(OpcStr, ".f32 \t$dst, $a;"),
290 [(set Float32Regs:$dst, (OpNode Float32Regs:$a))]>;
293 //===----------------------------------------------------------------------===//
294 // NVPTX Instructions.
295 //===----------------------------------------------------------------------===//
297 //-----------------------------------
298 // General Type Conversion
299 //-----------------------------------
301 let neverHasSideEffects = 1 in {
302 // Generate a cvt to the given type from all possible types.
303 // Each instance takes a CvtMode immediate that defines the conversion mode to
304 // use. It can be CvtNONE to omit a conversion mode.
305 multiclass CVT_FROM_ALL<string FromName, RegisterClass RC> {
306 def _s16 : NVPTXInst<(outs RC:$dst),
307 (ins Int16Regs:$src, CvtMode:$mode),
308 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
309 FromName, ".s16\t$dst, $src;"),
311 def _u16 : NVPTXInst<(outs RC:$dst),
312 (ins Int16Regs:$src, CvtMode:$mode),
313 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
314 FromName, ".u16\t$dst, $src;"),
316 def _f16 : NVPTXInst<(outs RC:$dst),
317 (ins Int16Regs:$src, CvtMode:$mode),
318 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
319 FromName, ".f16\t$dst, $src;"),
321 def _s32 : NVPTXInst<(outs RC:$dst),
322 (ins Int32Regs:$src, CvtMode:$mode),
323 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
324 FromName, ".s32\t$dst, $src;"),
326 def _u32 : NVPTXInst<(outs RC:$dst),
327 (ins Int32Regs:$src, CvtMode:$mode),
328 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
329 FromName, ".u32\t$dst, $src;"),
331 def _s64 : NVPTXInst<(outs RC:$dst),
332 (ins Int64Regs:$src, CvtMode:$mode),
333 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
334 FromName, ".s64\t$dst, $src;"),
336 def _u64 : NVPTXInst<(outs RC:$dst),
337 (ins Int64Regs:$src, CvtMode:$mode),
338 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
339 FromName, ".u64\t$dst, $src;"),
341 def _f32 : NVPTXInst<(outs RC:$dst),
342 (ins Float32Regs:$src, CvtMode:$mode),
343 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
344 FromName, ".f32\t$dst, $src;"),
346 def _f64 : NVPTXInst<(outs RC:$dst),
347 (ins Float64Regs:$src, CvtMode:$mode),
348 !strconcat("cvt${mode:base}${mode:ftz}${mode:sat}.",
349 FromName, ".f64\t$dst, $src;"),
353 // Generate a cvt to all possible types.
354 defm CVT_s16 : CVT_FROM_ALL<"s16", Int16Regs>;
355 defm CVT_u16 : CVT_FROM_ALL<"u16", Int16Regs>;
356 defm CVT_f16 : CVT_FROM_ALL<"f16", Int16Regs>;
357 defm CVT_s32 : CVT_FROM_ALL<"s32", Int32Regs>;
358 defm CVT_u32 : CVT_FROM_ALL<"u32", Int32Regs>;
359 defm CVT_s64 : CVT_FROM_ALL<"s64", Int64Regs>;
360 defm CVT_u64 : CVT_FROM_ALL<"u64", Int64Regs>;
361 defm CVT_f32 : CVT_FROM_ALL<"f32", Float32Regs>;
362 defm CVT_f64 : CVT_FROM_ALL<"f64", Float64Regs>;
364 // This set of cvt is different from the above. The type of the source
365 // and target are the same.
367 def CVT_INREG_s16_s8 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
368 "cvt.s16.s8 \t$dst, $src;", []>;
369 def CVT_INREG_s32_s8 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
370 "cvt.s32.s8 \t$dst, $src;", []>;
371 def CVT_INREG_s32_s16 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
372 "cvt.s32.s16 \t$dst, $src;", []>;
373 def CVT_INREG_s64_s8 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
374 "cvt.s64.s8 \t$dst, $src;", []>;
375 def CVT_INREG_s64_s16 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
376 "cvt.s64.s16 \t$dst, $src;", []>;
377 def CVT_INREG_s64_s32 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
378 "cvt.s64.s32 \t$dst, $src;", []>;
381 //-----------------------------------
382 // Integer Arithmetic
383 //-----------------------------------
385 multiclass ADD_SUB_i1<SDNode OpNode> {
386 def _rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b),
387 "xor.pred \t$dst, $a, $b;",
388 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>;
389 def _ri: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, i1imm:$b),
390 "xor.pred \t$dst, $a, $b;",
391 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, (imm):$b))]>;
394 defm ADD_i1 : ADD_SUB_i1<add>;
395 defm SUB_i1 : ADD_SUB_i1<sub>;
398 defm ADD : I3<"add.s", add>;
399 defm SUB : I3<"sub.s", sub>;
401 defm ADDCC : ADD_SUB_INT_32<"add.cc", addc>;
402 defm SUBCC : ADD_SUB_INT_32<"sub.cc", subc>;
404 defm ADDCCC : ADD_SUB_INT_32<"addc.cc", adde>;
405 defm SUBCCC : ADD_SUB_INT_32<"subc.cc", sube>;
407 //mul.wide PTX instruction
408 def SInt32Const : PatLeaf<(imm), [{
409 const APInt &v = N->getAPIntValue();
410 if (v.isSignedIntN(32))
415 def UInt32Const : PatLeaf<(imm), [{
416 const APInt &v = N->getAPIntValue();
422 def SInt16Const : PatLeaf<(imm), [{
423 const APInt &v = N->getAPIntValue();
424 if (v.isSignedIntN(16))
429 def UInt16Const : PatLeaf<(imm), [{
430 const APInt &v = N->getAPIntValue();
436 def Int5Const : PatLeaf<(imm), [{
437 const APInt &v = N->getAPIntValue();
438 // Check if 0 <= v < 32
439 // Only then the result from (x << v) will be i32
440 if (v.sge(0) && v.slt(32))
445 def Int4Const : PatLeaf<(imm), [{
446 const APInt &v = N->getAPIntValue();
447 // Check if 0 <= v < 16
448 // Only then the result from (x << v) will be i16
449 if (v.sge(0) && v.slt(16))
454 def SHL2MUL32 : SDNodeXForm<imm, [{
455 const APInt &v = N->getAPIntValue();
457 return CurDAG->getTargetConstant(temp.shl(v), MVT::i32);
460 def SHL2MUL16 : SDNodeXForm<imm, [{
461 const APInt &v = N->getAPIntValue();
463 return CurDAG->getTargetConstant(temp.shl(v), MVT::i16);
466 def MULWIDES64 : NVPTXInst<(outs Int64Regs:$dst),
467 (ins Int32Regs:$a, Int32Regs:$b),
468 "mul.wide.s32 \t$dst, $a, $b;", []>;
469 def MULWIDES64Imm : NVPTXInst<(outs Int64Regs:$dst),
470 (ins Int32Regs:$a, i64imm:$b),
471 "mul.wide.s32 \t$dst, $a, $b;", []>;
473 def MULWIDEU64 : NVPTXInst<(outs Int64Regs:$dst),
474 (ins Int32Regs:$a, Int32Regs:$b),
475 "mul.wide.u32 \t$dst, $a, $b;", []>;
476 def MULWIDEU64Imm : NVPTXInst<(outs Int64Regs:$dst),
477 (ins Int32Regs:$a, i64imm:$b),
478 "mul.wide.u32 \t$dst, $a, $b;", []>;
480 def MULWIDES32 : NVPTXInst<(outs Int32Regs:$dst),
481 (ins Int16Regs:$a, Int16Regs:$b),
482 "mul.wide.s16 \t$dst, $a, $b;", []>;
483 def MULWIDES32Imm : NVPTXInst<(outs Int32Regs:$dst),
484 (ins Int16Regs:$a, i32imm:$b),
485 "mul.wide.s16 \t$dst, $a, $b;", []>;
487 def MULWIDEU32 : NVPTXInst<(outs Int32Regs:$dst),
488 (ins Int16Regs:$a, Int16Regs:$b),
489 "mul.wide.u16 \t$dst, $a, $b;", []>;
490 def MULWIDEU32Imm : NVPTXInst<(outs Int32Regs:$dst),
491 (ins Int16Regs:$a, i32imm:$b),
492 "mul.wide.u16 \t$dst, $a, $b;", []>;
494 def : Pat<(shl (sext Int32Regs:$a), (i32 Int5Const:$b)),
495 (MULWIDES64Imm Int32Regs:$a, (SHL2MUL32 node:$b))>,
496 Requires<[doMulWide]>;
497 def : Pat<(shl (zext Int32Regs:$a), (i32 Int5Const:$b)),
498 (MULWIDEU64Imm Int32Regs:$a, (SHL2MUL32 node:$b))>,
499 Requires<[doMulWide]>;
501 def : Pat<(shl (sext Int16Regs:$a), (i16 Int4Const:$b)),
502 (MULWIDES32Imm Int16Regs:$a, (SHL2MUL16 node:$b))>,
503 Requires<[doMulWide]>;
504 def : Pat<(shl (zext Int16Regs:$a), (i16 Int4Const:$b)),
505 (MULWIDEU32Imm Int16Regs:$a, (SHL2MUL16 node:$b))>,
506 Requires<[doMulWide]>;
508 def : Pat<(mul (sext Int32Regs:$a), (sext Int32Regs:$b)),
509 (MULWIDES64 Int32Regs:$a, Int32Regs:$b)>,
510 Requires<[doMulWide]>;
511 def : Pat<(mul (sext Int32Regs:$a), (i64 SInt32Const:$b)),
512 (MULWIDES64Imm Int32Regs:$a, (i64 SInt32Const:$b))>,
513 Requires<[doMulWide]>;
515 def : Pat<(mul (zext Int32Regs:$a), (zext Int32Regs:$b)),
516 (MULWIDEU64 Int32Regs:$a, Int32Regs:$b)>, Requires<[doMulWide]>;
517 def : Pat<(mul (zext Int32Regs:$a), (i64 UInt32Const:$b)),
518 (MULWIDEU64Imm Int32Regs:$a, (i64 UInt32Const:$b))>,
519 Requires<[doMulWide]>;
521 def : Pat<(mul (sext Int16Regs:$a), (sext Int16Regs:$b)),
522 (MULWIDES32 Int16Regs:$a, Int16Regs:$b)>, Requires<[doMulWide]>;
523 def : Pat<(mul (sext Int16Regs:$a), (i32 SInt16Const:$b)),
524 (MULWIDES32Imm Int16Regs:$a, (i32 SInt16Const:$b))>,
525 Requires<[doMulWide]>;
527 def : Pat<(mul (zext Int16Regs:$a), (zext Int16Regs:$b)),
528 (MULWIDEU32 Int16Regs:$a, Int16Regs:$b)>, Requires<[doMulWide]>;
529 def : Pat<(mul (zext Int16Regs:$a), (i32 UInt16Const:$b)),
530 (MULWIDEU32Imm Int16Regs:$a, (i32 UInt16Const:$b))>,
531 Requires<[doMulWide]>;
533 defm MULT : I3<"mul.lo.s", mul>;
535 defm MULTHS : I3<"mul.hi.s", mulhs>;
536 defm MULTHU : I3<"mul.hi.u", mulhu>;
538 defm SDIV : I3<"div.s", sdiv>;
539 defm UDIV : I3<"div.u", udiv>;
541 defm SREM : I3<"rem.s", srem>;
542 // The ri version will not be selected as DAGCombiner::visitSREM will lower it.
543 defm UREM : I3<"rem.u", urem>;
544 // The ri version will not be selected as DAGCombiner::visitUREM will lower it.
546 def MAD16rrr : NVPTXInst<(outs Int16Regs:$dst),
547 (ins Int16Regs:$a, Int16Regs:$b, Int16Regs:$c),
548 "mad.lo.s16 \t$dst, $a, $b, $c;",
549 [(set Int16Regs:$dst, (add
550 (mul Int16Regs:$a, Int16Regs:$b), Int16Regs:$c))]>;
551 def MAD16rri : NVPTXInst<(outs Int16Regs:$dst),
552 (ins Int16Regs:$a, Int16Regs:$b, i16imm:$c),
553 "mad.lo.s16 \t$dst, $a, $b, $c;",
554 [(set Int16Regs:$dst, (add
555 (mul Int16Regs:$a, Int16Regs:$b), imm:$c))]>;
556 def MAD16rir : NVPTXInst<(outs Int16Regs:$dst),
557 (ins Int16Regs:$a, i16imm:$b, Int16Regs:$c),
558 "mad.lo.s16 \t$dst, $a, $b, $c;",
559 [(set Int16Regs:$dst, (add
560 (mul Int16Regs:$a, imm:$b), Int16Regs:$c))]>;
561 def MAD16rii : NVPTXInst<(outs Int16Regs:$dst),
562 (ins Int16Regs:$a, i16imm:$b, i16imm:$c),
563 "mad.lo.s16 \t$dst, $a, $b, $c;",
564 [(set Int16Regs:$dst, (add (mul Int16Regs:$a, imm:$b),
567 def MAD32rrr : NVPTXInst<(outs Int32Regs:$dst),
568 (ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
569 "mad.lo.s32 \t$dst, $a, $b, $c;",
570 [(set Int32Regs:$dst, (add
571 (mul Int32Regs:$a, Int32Regs:$b), Int32Regs:$c))]>;
572 def MAD32rri : NVPTXInst<(outs Int32Regs:$dst),
573 (ins Int32Regs:$a, Int32Regs:$b, i32imm:$c),
574 "mad.lo.s32 \t$dst, $a, $b, $c;",
575 [(set Int32Regs:$dst, (add
576 (mul Int32Regs:$a, Int32Regs:$b), imm:$c))]>;
577 def MAD32rir : NVPTXInst<(outs Int32Regs:$dst),
578 (ins Int32Regs:$a, i32imm:$b, Int32Regs:$c),
579 "mad.lo.s32 \t$dst, $a, $b, $c;",
580 [(set Int32Regs:$dst, (add
581 (mul Int32Regs:$a, imm:$b), Int32Regs:$c))]>;
582 def MAD32rii : NVPTXInst<(outs Int32Regs:$dst),
583 (ins Int32Regs:$a, i32imm:$b, i32imm:$c),
584 "mad.lo.s32 \t$dst, $a, $b, $c;",
585 [(set Int32Regs:$dst, (add
586 (mul Int32Regs:$a, imm:$b), imm:$c))]>;
588 def MAD64rrr : NVPTXInst<(outs Int64Regs:$dst),
589 (ins Int64Regs:$a, Int64Regs:$b, Int64Regs:$c),
590 "mad.lo.s64 \t$dst, $a, $b, $c;",
591 [(set Int64Regs:$dst, (add
592 (mul Int64Regs:$a, Int64Regs:$b), Int64Regs:$c))]>;
593 def MAD64rri : NVPTXInst<(outs Int64Regs:$dst),
594 (ins Int64Regs:$a, Int64Regs:$b, i64imm:$c),
595 "mad.lo.s64 \t$dst, $a, $b, $c;",
596 [(set Int64Regs:$dst, (add
597 (mul Int64Regs:$a, Int64Regs:$b), imm:$c))]>;
598 def MAD64rir : NVPTXInst<(outs Int64Regs:$dst),
599 (ins Int64Regs:$a, i64imm:$b, Int64Regs:$c),
600 "mad.lo.s64 \t$dst, $a, $b, $c;",
601 [(set Int64Regs:$dst, (add
602 (mul Int64Regs:$a, imm:$b), Int64Regs:$c))]>;
603 def MAD64rii : NVPTXInst<(outs Int64Regs:$dst),
604 (ins Int64Regs:$a, i64imm:$b, i64imm:$c),
605 "mad.lo.s64 \t$dst, $a, $b, $c;",
606 [(set Int64Regs:$dst, (add
607 (mul Int64Regs:$a, imm:$b), imm:$c))]>;
610 def INEG16 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
611 "neg.s16 \t$dst, $src;",
612 [(set Int16Regs:$dst, (ineg Int16Regs:$src))]>;
613 def INEG32 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
614 "neg.s32 \t$dst, $src;",
615 [(set Int32Regs:$dst, (ineg Int32Regs:$src))]>;
616 def INEG64 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
617 "neg.s64 \t$dst, $src;",
618 [(set Int64Regs:$dst, (ineg Int64Regs:$src))]>;
620 //-----------------------------------
621 // Floating Point Arithmetic
622 //-----------------------------------
625 def FloatConst1 : PatLeaf<(fpimm), [{
626 if (&(N->getValueAPF().getSemantics()) != &llvm::APFloat::IEEEsingle)
628 float f = (float)N->getValueAPF().convertToFloat();
631 // Constand (double)1.0
632 def DoubleConst1 : PatLeaf<(fpimm), [{
633 if (&(N->getValueAPF().getSemantics()) != &llvm::APFloat::IEEEdouble)
635 double d = (double)N->getValueAPF().convertToDouble();
639 defm FADD : F3<"add", fadd>;
640 defm FSUB : F3<"sub", fsub>;
641 defm FMUL : F3<"mul", fmul>;
643 defm FADD_rn : F3_rn<"add", fadd>;
644 defm FSUB_rn : F3_rn<"sub", fsub>;
645 defm FMUL_rn : F3_rn<"mul", fmul>;
647 defm FABS : F2<"abs", fabs>;
648 defm FNEG : F2<"neg", fneg>;
649 defm FSQRT : F2<"sqrt.rn", fsqrt>;
654 def FDIV641r : NVPTXInst<(outs Float64Regs:$dst),
655 (ins f64imm:$a, Float64Regs:$b),
656 "rcp.rn.f64 \t$dst, $b;",
657 [(set Float64Regs:$dst,
658 (fdiv DoubleConst1:$a, Float64Regs:$b))]>;
659 def FDIV64rr : NVPTXInst<(outs Float64Regs:$dst),
660 (ins Float64Regs:$a, Float64Regs:$b),
661 "div.rn.f64 \t$dst, $a, $b;",
662 [(set Float64Regs:$dst,
663 (fdiv Float64Regs:$a, Float64Regs:$b))]>;
664 def FDIV64ri : NVPTXInst<(outs Float64Regs:$dst),
665 (ins Float64Regs:$a, f64imm:$b),
666 "div.rn.f64 \t$dst, $a, $b;",
667 [(set Float64Regs:$dst,
668 (fdiv Float64Regs:$a, fpimm:$b))]>;
671 // F32 Approximate reciprocal
673 def FDIV321r_ftz : NVPTXInst<(outs Float32Regs:$dst),
674 (ins f32imm:$a, Float32Regs:$b),
675 "rcp.approx.ftz.f32 \t$dst, $b;",
676 [(set Float32Regs:$dst,
677 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
678 Requires<[do_DIVF32_APPROX, doF32FTZ]>;
679 def FDIV321r : NVPTXInst<(outs Float32Regs:$dst),
680 (ins f32imm:$a, Float32Regs:$b),
681 "rcp.approx.f32 \t$dst, $b;",
682 [(set Float32Regs:$dst,
683 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
684 Requires<[do_DIVF32_APPROX]>;
686 // F32 Approximate division
688 def FDIV32approxrr_ftz : NVPTXInst<(outs Float32Regs:$dst),
689 (ins Float32Regs:$a, Float32Regs:$b),
690 "div.approx.ftz.f32 \t$dst, $a, $b;",
691 [(set Float32Regs:$dst,
692 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
693 Requires<[do_DIVF32_APPROX, doF32FTZ]>;
694 def FDIV32approxrr : NVPTXInst<(outs Float32Regs:$dst),
695 (ins Float32Regs:$a, Float32Regs:$b),
696 "div.approx.f32 \t$dst, $a, $b;",
697 [(set Float32Regs:$dst,
698 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
699 Requires<[do_DIVF32_APPROX]>;
701 // F32 Semi-accurate reciprocal
703 // rcp.approx gives the same result as div.full(1.0f, a) and is faster.
705 def FDIV321r_approx_ftz : NVPTXInst<(outs Float32Regs:$dst),
706 (ins f32imm:$a, Float32Regs:$b),
707 "rcp.approx.ftz.f32 \t$dst, $b;",
708 [(set Float32Regs:$dst,
709 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
710 Requires<[do_DIVF32_FULL, doF32FTZ]>;
711 def FDIV321r_approx : NVPTXInst<(outs Float32Regs:$dst),
712 (ins f32imm:$a, Float32Regs:$b),
713 "rcp.approx.f32 \t$dst, $b;",
714 [(set Float32Regs:$dst,
715 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
716 Requires<[do_DIVF32_FULL]>;
718 // F32 Semi-accurate division
720 def FDIV32rr_ftz : NVPTXInst<(outs Float32Regs:$dst),
721 (ins Float32Regs:$a, Float32Regs:$b),
722 "div.full.ftz.f32 \t$dst, $a, $b;",
723 [(set Float32Regs:$dst,
724 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
725 Requires<[do_DIVF32_FULL, doF32FTZ]>;
726 def FDIV32ri_ftz : NVPTXInst<(outs Float32Regs:$dst),
727 (ins Float32Regs:$a, f32imm:$b),
728 "div.full.ftz.f32 \t$dst, $a, $b;",
729 [(set Float32Regs:$dst,
730 (fdiv Float32Regs:$a, fpimm:$b))]>,
731 Requires<[do_DIVF32_FULL, doF32FTZ]>;
732 def FDIV32rr : NVPTXInst<(outs Float32Regs:$dst),
733 (ins Float32Regs:$a, Float32Regs:$b),
734 "div.full.f32 \t$dst, $a, $b;",
735 [(set Float32Regs:$dst,
736 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
737 Requires<[do_DIVF32_FULL]>;
738 def FDIV32ri : NVPTXInst<(outs Float32Regs:$dst),
739 (ins Float32Regs:$a, f32imm:$b),
740 "div.full.f32 \t$dst, $a, $b;",
741 [(set Float32Regs:$dst,
742 (fdiv Float32Regs:$a, fpimm:$b))]>,
743 Requires<[do_DIVF32_FULL]>;
745 // F32 Accurate reciprocal
747 def FDIV321r_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
748 (ins f32imm:$a, Float32Regs:$b),
749 "rcp.rn.ftz.f32 \t$dst, $b;",
750 [(set Float32Regs:$dst,
751 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
752 Requires<[reqPTX20, doF32FTZ]>;
753 def FDIV321r_prec : NVPTXInst<(outs Float32Regs:$dst),
754 (ins f32imm:$a, Float32Regs:$b),
755 "rcp.rn.f32 \t$dst, $b;",
756 [(set Float32Regs:$dst,
757 (fdiv FloatConst1:$a, Float32Regs:$b))]>,
758 Requires<[reqPTX20]>;
760 // F32 Accurate division
762 def FDIV32rr_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
763 (ins Float32Regs:$a, Float32Regs:$b),
764 "div.rn.ftz.f32 \t$dst, $a, $b;",
765 [(set Float32Regs:$dst,
766 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
767 Requires<[doF32FTZ, reqPTX20]>;
768 def FDIV32ri_prec_ftz : NVPTXInst<(outs Float32Regs:$dst),
769 (ins Float32Regs:$a, f32imm:$b),
770 "div.rn.ftz.f32 \t$dst, $a, $b;",
771 [(set Float32Regs:$dst,
772 (fdiv Float32Regs:$a, fpimm:$b))]>,
773 Requires<[doF32FTZ, reqPTX20]>;
774 def FDIV32rr_prec : NVPTXInst<(outs Float32Regs:$dst),
775 (ins Float32Regs:$a, Float32Regs:$b),
776 "div.rn.f32 \t$dst, $a, $b;",
777 [(set Float32Regs:$dst,
778 (fdiv Float32Regs:$a, Float32Regs:$b))]>,
779 Requires<[reqPTX20]>;
780 def FDIV32ri_prec : NVPTXInst<(outs Float32Regs:$dst),
781 (ins Float32Regs:$a, f32imm:$b),
782 "div.rn.f32 \t$dst, $a, $b;",
783 [(set Float32Regs:$dst,
784 (fdiv Float32Regs:$a, fpimm:$b))]>,
785 Requires<[reqPTX20]>;
791 def RSQRTF32approx1r : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$b),
792 "rsqrt.approx.f32 \t$dst, $b;", []>;
794 def: Pat<(fdiv FloatConst1, (int_nvvm_sqrt_f Float32Regs:$b)),
795 (RSQRTF32approx1r Float32Regs:$b)>,
796 Requires<[do_DIVF32_FULL, do_SQRTF32_APPROX, doNoF32FTZ]>;
798 multiclass FPCONTRACT32<string OpcStr, Predicate Pred> {
799 def rrr : NVPTXInst<(outs Float32Regs:$dst),
800 (ins Float32Regs:$a, Float32Regs:$b, Float32Regs:$c),
801 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
802 [(set Float32Regs:$dst, (fadd
803 (fmul Float32Regs:$a, Float32Regs:$b),
804 Float32Regs:$c))]>, Requires<[Pred]>;
805 // This is to WAR a weird bug in Tablegen that does not automatically
806 // generate the following permutated rule rrr2 from the above rrr.
807 // So we explicitly add it here. This happens to FMA32 only.
808 // See the comments at FMAD32 and FMA32 for more information.
809 def rrr2 : NVPTXInst<(outs Float32Regs:$dst),
810 (ins Float32Regs:$a, Float32Regs:$b, Float32Regs:$c),
811 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
812 [(set Float32Regs:$dst, (fadd Float32Regs:$c,
813 (fmul Float32Regs:$a, Float32Regs:$b)))]>,
815 def rri : NVPTXInst<(outs Float32Regs:$dst),
816 (ins Float32Regs:$a, Float32Regs:$b, f32imm:$c),
817 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
818 [(set Float32Regs:$dst, (fadd
819 (fmul Float32Regs:$a, Float32Regs:$b), fpimm:$c))]>,
821 def rir : NVPTXInst<(outs Float32Regs:$dst),
822 (ins Float32Regs:$a, f32imm:$b, Float32Regs:$c),
823 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
824 [(set Float32Regs:$dst, (fadd
825 (fmul Float32Regs:$a, fpimm:$b), Float32Regs:$c))]>,
827 def rii : NVPTXInst<(outs Float32Regs:$dst),
828 (ins Float32Regs:$a, f32imm:$b, f32imm:$c),
829 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
830 [(set Float32Regs:$dst, (fadd
831 (fmul Float32Regs:$a, fpimm:$b), fpimm:$c))]>,
835 multiclass FPCONTRACT64<string OpcStr, Predicate Pred> {
836 def rrr : NVPTXInst<(outs Float64Regs:$dst),
837 (ins Float64Regs:$a, Float64Regs:$b, Float64Regs:$c),
838 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
839 [(set Float64Regs:$dst, (fadd
840 (fmul Float64Regs:$a, Float64Regs:$b),
841 Float64Regs:$c))]>, Requires<[Pred]>;
842 def rri : NVPTXInst<(outs Float64Regs:$dst),
843 (ins Float64Regs:$a, Float64Regs:$b, f64imm:$c),
844 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
845 [(set Float64Regs:$dst, (fadd (fmul Float64Regs:$a,
846 Float64Regs:$b), fpimm:$c))]>, Requires<[Pred]>;
847 def rir : NVPTXInst<(outs Float64Regs:$dst),
848 (ins Float64Regs:$a, f64imm:$b, Float64Regs:$c),
849 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
850 [(set Float64Regs:$dst, (fadd
851 (fmul Float64Regs:$a, fpimm:$b), Float64Regs:$c))]>,
853 def rii : NVPTXInst<(outs Float64Regs:$dst),
854 (ins Float64Regs:$a, f64imm:$b, f64imm:$c),
855 !strconcat(OpcStr, " \t$dst, $a, $b, $c;"),
856 [(set Float64Regs:$dst, (fadd
857 (fmul Float64Regs:$a, fpimm:$b), fpimm:$c))]>,
861 // Due to a unknown reason (most likely a bug in tablegen), tablegen does not
862 // automatically generate the rrr2 rule from
863 // the rrr rule (see FPCONTRACT32) for FMA32, though it does for FMAD32.
864 // If we reverse the order of the following two lines, then rrr2 rule will be
865 // generated for FMA32, but not for rrr.
866 // Therefore, we manually write the rrr2 rule in FPCONTRACT32.
867 defm FMAD32_ftz : FPCONTRACT32<"mad.ftz.f32", doFMADF32_ftz>;
868 defm FMAD32 : FPCONTRACT32<"mad.f32", doFMADF32>;
869 defm FMA32_ftz : FPCONTRACT32<"fma.rn.ftz.f32", doFMAF32_ftz>;
870 defm FMA32 : FPCONTRACT32<"fma.rn.f32", doFMAF32>;
871 defm FMA64 : FPCONTRACT64<"fma.rn.f64", doFMAF64>;
873 // b*c-a => fmad(b, c, -a)
874 multiclass FPCONTRACT32_SUB_PAT_MAD<NVPTXInst Inst, Predicate Pred> {
875 def : Pat<(fsub (fmul Float32Regs:$b, Float32Regs:$c), Float32Regs:$a),
876 (Inst Float32Regs:$b, Float32Regs:$c, (FNEGf32 Float32Regs:$a))>,
880 // a-b*c => fmad(-b,c, a)
881 // - legal because a-b*c <=> a+(-b*c) <=> a+(-b)*c
882 // b*c-a => fmad(b, c, -a)
883 // - legal because b*c-a <=> b*c+(-a)
884 multiclass FPCONTRACT32_SUB_PAT<NVPTXInst Inst, Predicate Pred> {
885 def : Pat<(fsub Float32Regs:$a, (fmul Float32Regs:$b, Float32Regs:$c)),
886 (Inst (FNEGf32 Float32Regs:$b), Float32Regs:$c, Float32Regs:$a)>,
888 def : Pat<(fsub (fmul Float32Regs:$b, Float32Regs:$c), Float32Regs:$a),
889 (Inst Float32Regs:$b, Float32Regs:$c, (FNEGf32 Float32Regs:$a))>,
893 // a-b*c => fmad(-b,c, a)
894 // b*c-a => fmad(b, c, -a)
895 multiclass FPCONTRACT64_SUB_PAT<NVPTXInst Inst, Predicate Pred> {
896 def : Pat<(fsub Float64Regs:$a, (fmul Float64Regs:$b, Float64Regs:$c)),
897 (Inst (FNEGf64 Float64Regs:$b), Float64Regs:$c, Float64Regs:$a)>,
900 def : Pat<(fsub (fmul Float64Regs:$b, Float64Regs:$c), Float64Regs:$a),
901 (Inst Float64Regs:$b, Float64Regs:$c, (FNEGf64 Float64Regs:$a))>,
905 defm FMAF32ext_ftz : FPCONTRACT32_SUB_PAT<FMA32_ftzrrr, doFMAF32AGG_ftz>;
906 defm FMAF32ext : FPCONTRACT32_SUB_PAT<FMA32rrr, doFMAF32AGG>;
907 defm FMADF32ext_ftz : FPCONTRACT32_SUB_PAT_MAD<FMAD32_ftzrrr, doFMADF32_ftz>;
908 defm FMADF32ext : FPCONTRACT32_SUB_PAT_MAD<FMAD32rrr, doFMADF32>;
909 defm FMAF64ext : FPCONTRACT64_SUB_PAT<FMA64rrr, doFMAF64AGG>;
911 def SINF: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
912 "sin.approx.f32 \t$dst, $src;",
913 [(set Float32Regs:$dst, (fsin Float32Regs:$src))]>;
914 def COSF: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
915 "cos.approx.f32 \t$dst, $src;",
916 [(set Float32Regs:$dst, (fcos Float32Regs:$src))]>;
918 // Lower (frem x, y) into (sub x, (mul (floor (div x, y)) y))
919 // e.g. "poor man's fmod()"
922 def : Pat<(frem Float32Regs:$x, Float32Regs:$y),
923 (FSUBf32rr_ftz Float32Regs:$x, (FMULf32rr_ftz (CVT_f32_f32
924 (FDIV32rr_prec_ftz Float32Regs:$x, Float32Regs:$y), CvtRMI_FTZ),
926 Requires<[doF32FTZ]>;
927 def : Pat<(frem Float32Regs:$x, fpimm:$y),
928 (FSUBf32rr_ftz Float32Regs:$x, (FMULf32ri_ftz (CVT_f32_f32
929 (FDIV32ri_prec_ftz Float32Regs:$x, fpimm:$y), CvtRMI_FTZ),
931 Requires<[doF32FTZ]>;
934 def : Pat<(frem Float32Regs:$x, Float32Regs:$y),
935 (FSUBf32rr Float32Regs:$x, (FMULf32rr (CVT_f32_f32
936 (FDIV32rr_prec Float32Regs:$x, Float32Regs:$y), CvtRMI),
938 def : Pat<(frem Float32Regs:$x, fpimm:$y),
939 (FSUBf32rr Float32Regs:$x, (FMULf32ri (CVT_f32_f32
940 (FDIV32ri_prec Float32Regs:$x, fpimm:$y), CvtRMI),
944 def : Pat<(frem Float64Regs:$x, Float64Regs:$y),
945 (FSUBf64rr Float64Regs:$x, (FMULf64rr (CVT_f64_f64
946 (FDIV64rr Float64Regs:$x, Float64Regs:$y), CvtRMI),
948 def : Pat<(frem Float64Regs:$x, fpimm:$y),
949 (FSUBf64rr Float64Regs:$x, (FMULf64ri (CVT_f64_f64
950 (FDIV64ri Float64Regs:$x, fpimm:$y), CvtRMI),
953 //-----------------------------------
954 // Logical Arithmetic
955 //-----------------------------------
957 multiclass LOG_FORMAT<string OpcStr, SDNode OpNode> {
958 def b1rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b),
959 !strconcat(OpcStr, ".pred \t$dst, $a, $b;"),
960 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>;
961 def b1ri: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, i1imm:$b),
962 !strconcat(OpcStr, ".pred \t$dst, $a, $b;"),
963 [(set Int1Regs:$dst, (OpNode Int1Regs:$a, imm:$b))]>;
964 def b16rr: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
965 !strconcat(OpcStr, ".b16 \t$dst, $a, $b;"),
966 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
968 def b16ri: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i16imm:$b),
969 !strconcat(OpcStr, ".b16 \t$dst, $a, $b;"),
970 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, imm:$b))]>;
971 def b32rr: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
972 !strconcat(OpcStr, ".b32 \t$dst, $a, $b;"),
973 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
975 def b32ri: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
976 !strconcat(OpcStr, ".b32 \t$dst, $a, $b;"),
977 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
978 def b64rr: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int64Regs:$b),
979 !strconcat(OpcStr, ".b64 \t$dst, $a, $b;"),
980 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
982 def b64ri: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i64imm:$b),
983 !strconcat(OpcStr, ".b64 \t$dst, $a, $b;"),
984 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
987 defm OR : LOG_FORMAT<"or", or>;
988 defm AND : LOG_FORMAT<"and", and>;
989 defm XOR : LOG_FORMAT<"xor", xor>;
991 def NOT1: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$src),
992 "not.pred \t$dst, $src;",
993 [(set Int1Regs:$dst, (not Int1Regs:$src))]>;
994 def NOT16: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
995 "not.b16 \t$dst, $src;",
996 [(set Int16Regs:$dst, (not Int16Regs:$src))]>;
997 def NOT32: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
998 "not.b32 \t$dst, $src;",
999 [(set Int32Regs:$dst, (not Int32Regs:$src))]>;
1000 def NOT64: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
1001 "not.b64 \t$dst, $src;",
1002 [(set Int64Regs:$dst, (not Int64Regs:$src))]>;
1004 // For shifts, the second src operand must be 32-bit value
1005 multiclass LSHIFT_FORMAT<string OpcStr, SDNode OpNode> {
1006 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a,
1008 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
1009 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
1011 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i32imm:$b),
1012 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
1013 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
1015 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
1017 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1018 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
1020 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
1021 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1022 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
1024 def i32ii : NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$a, i32imm:$b),
1025 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1026 [(set Int32Regs:$dst, (OpNode (i32 imm:$a),
1028 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a,
1030 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1031 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1033 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
1034 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1035 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1039 defm SHL : LSHIFT_FORMAT<"shl.b", shl>;
1041 // For shifts, the second src operand must be 32-bit value
1042 // Need to add cvt for the 8-bits.
1043 multiclass RSHIFT_FORMAT<string OpcStr, SDNode OpNode> {
1044 def i64rr : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a,
1046 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
1047 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
1049 def i64ri : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i32imm:$b),
1050 !strconcat(OpcStr, "64 \t$dst, $a, $b;"),
1051 [(set Int64Regs:$dst, (OpNode Int64Regs:$a,
1053 def i32rr : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a,
1055 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1056 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
1058 def i32ri : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
1059 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1060 [(set Int32Regs:$dst, (OpNode Int32Regs:$a,
1062 def i32ii : NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$a, i32imm:$b),
1063 !strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1064 [(set Int32Regs:$dst, (OpNode (i32 imm:$a),
1066 def i16rr : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a,
1068 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1069 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1071 def i16ri : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
1072 !strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1073 [(set Int16Regs:$dst, (OpNode Int16Regs:$a,
1077 defm SRA : RSHIFT_FORMAT<"shr.s", sra>;
1078 defm SRL : RSHIFT_FORMAT<"shr.u", srl>;
1081 def ROT32imm_sw : NVPTXInst<(outs Int32Regs:$dst),
1082 (ins Int32Regs:$src, i32imm:$amt1, i32imm:$amt2),
1083 !strconcat("{{\n\t",
1084 !strconcat(".reg .b32 %lhs;\n\t",
1085 !strconcat(".reg .b32 %rhs;\n\t",
1086 !strconcat("shl.b32 \t%lhs, $src, $amt1;\n\t",
1087 !strconcat("shr.b32 \t%rhs, $src, $amt2;\n\t",
1088 !strconcat("add.u32 \t$dst, %lhs, %rhs;\n\t",
1089 !strconcat("}}", ""))))))),
1092 def SUB_FRM_32 : SDNodeXForm<imm, [{
1093 return CurDAG->getTargetConstant(32-N->getZExtValue(), MVT::i32);
1096 def : Pat<(rotl Int32Regs:$src, (i32 imm:$amt)),
1097 (ROT32imm_sw Int32Regs:$src, imm:$amt, (SUB_FRM_32 node:$amt))>;
1098 def : Pat<(rotr Int32Regs:$src, (i32 imm:$amt)),
1099 (ROT32imm_sw Int32Regs:$src, (SUB_FRM_32 node:$amt), imm:$amt)>;
1101 def ROTL32reg_sw : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src,
1103 !strconcat("{{\n\t",
1104 !strconcat(".reg .b32 %lhs;\n\t",
1105 !strconcat(".reg .b32 %rhs;\n\t",
1106 !strconcat(".reg .b32 %amt2;\n\t",
1107 !strconcat("shl.b32 \t%lhs, $src, $amt;\n\t",
1108 !strconcat("sub.s32 \t%amt2, 32, $amt;\n\t",
1109 !strconcat("shr.b32 \t%rhs, $src, %amt2;\n\t",
1110 !strconcat("add.u32 \t$dst, %lhs, %rhs;\n\t",
1111 !strconcat("}}", ""))))))))),
1112 [(set Int32Regs:$dst, (rotl Int32Regs:$src, Int32Regs:$amt))]>;
1114 def ROTR32reg_sw : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src,
1116 !strconcat("{{\n\t",
1117 !strconcat(".reg .b32 %lhs;\n\t",
1118 !strconcat(".reg .b32 %rhs;\n\t",
1119 !strconcat(".reg .b32 %amt2;\n\t",
1120 !strconcat("shr.b32 \t%lhs, $src, $amt;\n\t",
1121 !strconcat("sub.s32 \t%amt2, 32, $amt;\n\t",
1122 !strconcat("shl.b32 \t%rhs, $src, %amt2;\n\t",
1123 !strconcat("add.u32 \t$dst, %lhs, %rhs;\n\t",
1124 !strconcat("}}", ""))))))))),
1125 [(set Int32Regs:$dst, (rotr Int32Regs:$src, Int32Regs:$amt))]>;
1128 def ROT64imm_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1129 i32imm:$amt1, i32imm:$amt2),
1130 !strconcat("{{\n\t",
1131 !strconcat(".reg .b64 %lhs;\n\t",
1132 !strconcat(".reg .b64 %rhs;\n\t",
1133 !strconcat("shl.b64 \t%lhs, $src, $amt1;\n\t",
1134 !strconcat("shr.b64 \t%rhs, $src, $amt2;\n\t",
1135 !strconcat("add.u64 \t$dst, %lhs, %rhs;\n\t",
1136 !strconcat("}}", ""))))))),
1139 def SUB_FRM_64 : SDNodeXForm<imm, [{
1140 return CurDAG->getTargetConstant(64-N->getZExtValue(), MVT::i32);
1143 def : Pat<(rotl Int64Regs:$src, (i32 imm:$amt)),
1144 (ROT64imm_sw Int64Regs:$src, imm:$amt, (SUB_FRM_64 node:$amt))>;
1145 def : Pat<(rotr Int64Regs:$src, (i32 imm:$amt)),
1146 (ROT64imm_sw Int64Regs:$src, (SUB_FRM_64 node:$amt), imm:$amt)>;
1148 def ROTL64reg_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1150 !strconcat("{{\n\t",
1151 !strconcat(".reg .b64 %lhs;\n\t",
1152 !strconcat(".reg .b64 %rhs;\n\t",
1153 !strconcat(".reg .u32 %amt2;\n\t",
1154 !strconcat("shl.b64 \t%lhs, $src, $amt;\n\t",
1155 !strconcat("sub.u32 \t%amt2, 64, $amt;\n\t",
1156 !strconcat("shr.b64 \t%rhs, $src, %amt2;\n\t",
1157 !strconcat("add.u64 \t$dst, %lhs, %rhs;\n\t",
1158 !strconcat("}}", ""))))))))),
1159 [(set Int64Regs:$dst, (rotl Int64Regs:$src, Int32Regs:$amt))]>;
1161 def ROTR64reg_sw : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src,
1163 !strconcat("{{\n\t",
1164 !strconcat(".reg .b64 %lhs;\n\t",
1165 !strconcat(".reg .b64 %rhs;\n\t",
1166 !strconcat(".reg .u32 %amt2;\n\t",
1167 !strconcat("shr.b64 \t%lhs, $src, $amt;\n\t",
1168 !strconcat("sub.u32 \t%amt2, 64, $amt;\n\t",
1169 !strconcat("shl.b64 \t%rhs, $src, %amt2;\n\t",
1170 !strconcat("add.u64 \t$dst, %lhs, %rhs;\n\t",
1171 !strconcat("}}", ""))))))))),
1172 [(set Int64Regs:$dst, (rotr Int64Regs:$src, Int32Regs:$amt))]>;
1175 //-----------------------------------
1176 // General Comparison
1177 //-----------------------------------
1179 // General setp instructions
1180 multiclass SETP<string TypeStr, RegisterClass RC, Operand ImmCls> {
1181 def rr : NVPTXInst<(outs Int1Regs:$dst),
1182 (ins RC:$a, RC:$b, CmpMode:$cmp),
1183 !strconcat("setp${cmp:base}${cmp:ftz}.", TypeStr, "\t$dst, $a, $b;"),
1185 def ri : NVPTXInst<(outs Int1Regs:$dst),
1186 (ins RC:$a, ImmCls:$b, CmpMode:$cmp),
1187 !strconcat("setp${cmp:base}${cmp:ftz}.", TypeStr, "\t$dst, $a, $b;"),
1189 def ir : NVPTXInst<(outs Int1Regs:$dst),
1190 (ins ImmCls:$a, RC:$b, CmpMode:$cmp),
1191 !strconcat("setp${cmp:base}${cmp:ftz}.", TypeStr, "\t$dst, $a, $b;"),
1195 defm SETP_b16 : SETP<"b16", Int16Regs, i16imm>;
1196 defm SETP_s16 : SETP<"s16", Int16Regs, i16imm>;
1197 defm SETP_u16 : SETP<"u16", Int16Regs, i16imm>;
1198 defm SETP_b32 : SETP<"b32", Int32Regs, i32imm>;
1199 defm SETP_s32 : SETP<"s32", Int32Regs, i32imm>;
1200 defm SETP_u32 : SETP<"u32", Int32Regs, i32imm>;
1201 defm SETP_b64 : SETP<"b64", Int64Regs, i64imm>;
1202 defm SETP_s64 : SETP<"s64", Int64Regs, i64imm>;
1203 defm SETP_u64 : SETP<"u64", Int64Regs, i64imm>;
1204 defm SETP_f32 : SETP<"f32", Float32Regs, f32imm>;
1205 defm SETP_f64 : SETP<"f64", Float64Regs, f64imm>;
1207 // General set instructions
1208 multiclass SET<string TypeStr, RegisterClass RC, Operand ImmCls> {
1209 def rr : NVPTXInst<(outs Int32Regs:$dst),
1210 (ins RC:$a, RC:$b, CmpMode:$cmp),
1211 !strconcat("set$cmp.", TypeStr, "\t$dst, $a, $b;"), []>;
1212 def ri : NVPTXInst<(outs Int32Regs:$dst),
1213 (ins RC:$a, ImmCls:$b, CmpMode:$cmp),
1214 !strconcat("set$cmp.", TypeStr, "\t$dst, $a, $b;"), []>;
1215 def ir : NVPTXInst<(outs Int32Regs:$dst),
1216 (ins ImmCls:$a, RC:$b, CmpMode:$cmp),
1217 !strconcat("set$cmp.", TypeStr, "\t$dst, $a, $b;"), []>;
1220 defm SET_b16 : SET<"b16", Int16Regs, i16imm>;
1221 defm SET_s16 : SET<"s16", Int16Regs, i16imm>;
1222 defm SET_u16 : SET<"u16", Int16Regs, i16imm>;
1223 defm SET_b32 : SET<"b32", Int32Regs, i32imm>;
1224 defm SET_s32 : SET<"s32", Int32Regs, i32imm>;
1225 defm SET_u32 : SET<"u32", Int32Regs, i32imm>;
1226 defm SET_b64 : SET<"b64", Int64Regs, i64imm>;
1227 defm SET_s64 : SET<"s64", Int64Regs, i64imm>;
1228 defm SET_u64 : SET<"u64", Int64Regs, i64imm>;
1229 defm SET_f32 : SET<"f32", Float32Regs, f32imm>;
1230 defm SET_f64 : SET<"f64", Float64Regs, f64imm>;
1232 //-----------------------------------
1233 // General Selection
1234 //-----------------------------------
1236 // General selp instructions
1237 multiclass SELP<string TypeStr, RegisterClass RC, Operand ImmCls> {
1238 def rr : NVPTXInst<(outs RC:$dst),
1239 (ins RC:$a, RC:$b, Int1Regs:$p),
1240 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1241 def ri : NVPTXInst<(outs RC:$dst),
1242 (ins RC:$a, ImmCls:$b, Int1Regs:$p),
1243 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1244 def ir : NVPTXInst<(outs RC:$dst),
1245 (ins ImmCls:$a, RC:$b, Int1Regs:$p),
1246 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1247 def ii : NVPTXInst<(outs RC:$dst),
1248 (ins ImmCls:$a, ImmCls:$b, Int1Regs:$p),
1249 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"), []>;
1252 multiclass SELP_PATTERN<string TypeStr, RegisterClass RC, Operand ImmCls,
1254 def rr : NVPTXInst<(outs RC:$dst),
1255 (ins RC:$a, RC:$b, Int1Regs:$p),
1256 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1257 [(set RC:$dst, (select Int1Regs:$p, RC:$a, RC:$b))]>;
1258 def ri : NVPTXInst<(outs RC:$dst),
1259 (ins RC:$a, ImmCls:$b, Int1Regs:$p),
1260 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1261 [(set RC:$dst, (select Int1Regs:$p, RC:$a, ImmNode:$b))]>;
1262 def ir : NVPTXInst<(outs RC:$dst),
1263 (ins ImmCls:$a, RC:$b, Int1Regs:$p),
1264 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1265 [(set RC:$dst, (select Int1Regs:$p, ImmNode:$a, RC:$b))]>;
1266 def ii : NVPTXInst<(outs RC:$dst),
1267 (ins ImmCls:$a, ImmCls:$b, Int1Regs:$p),
1268 !strconcat("selp.", TypeStr, "\t$dst, $a, $b, $p;"),
1269 [(set RC:$dst, (select Int1Regs:$p, ImmNode:$a, ImmNode:$b))]>;
1272 defm SELP_b16 : SELP_PATTERN<"b16", Int16Regs, i16imm, imm>;
1273 defm SELP_s16 : SELP<"s16", Int16Regs, i16imm>;
1274 defm SELP_u16 : SELP<"u16", Int16Regs, i16imm>;
1275 defm SELP_b32 : SELP_PATTERN<"b32", Int32Regs, i32imm, imm>;
1276 defm SELP_s32 : SELP<"s32", Int32Regs, i32imm>;
1277 defm SELP_u32 : SELP<"u32", Int32Regs, i32imm>;
1278 defm SELP_b64 : SELP_PATTERN<"b64", Int64Regs, i64imm, imm>;
1279 defm SELP_s64 : SELP<"s64", Int64Regs, i64imm>;
1280 defm SELP_u64 : SELP<"u64", Int64Regs, i64imm>;
1281 defm SELP_f32 : SELP_PATTERN<"f32", Float32Regs, f32imm, fpimm>;
1282 defm SELP_f64 : SELP_PATTERN<"f64", Float64Regs, f64imm, fpimm>;
1284 // Special select for predicate operands
1285 def : Pat<(i1 (select Int1Regs:$p, Int1Regs:$a, Int1Regs:$b)),
1286 (ORb1rr (ANDb1rr Int1Regs:$p, Int1Regs:$a),
1287 (ANDb1rr (NOT1 Int1Regs:$p), Int1Regs:$b))>;
1289 //-----------------------------------
1290 // Data Movement (Load / Store, Move)
1291 //-----------------------------------
1293 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex],
1295 def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri64", [frameindex],
1298 def MEMri : Operand<i32> {
1299 let PrintMethod = "printMemOperand";
1300 let MIOperandInfo = (ops Int32Regs, i32imm);
1302 def MEMri64 : Operand<i64> {
1303 let PrintMethod = "printMemOperand";
1304 let MIOperandInfo = (ops Int64Regs, i64imm);
1307 def imem : Operand<iPTR> {
1308 let PrintMethod = "printOperand";
1311 def imemAny : Operand<iPTRAny> {
1312 let PrintMethod = "printOperand";
1315 def LdStCode : Operand<i32> {
1316 let PrintMethod = "printLdStCode";
1319 def SDTWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
1320 def Wrapper : SDNode<"NVPTXISD::Wrapper", SDTWrapper>;
1322 def MOV_ADDR : NVPTXInst<(outs Int32Regs:$dst), (ins imem:$a),
1323 "mov.u32 \t$dst, $a;",
1324 [(set Int32Regs:$dst, (Wrapper tglobaladdr:$a))]>;
1326 def MOV_ADDR64 : NVPTXInst<(outs Int64Regs:$dst), (ins imem:$a),
1327 "mov.u64 \t$dst, $a;",
1328 [(set Int64Regs:$dst, (Wrapper tglobaladdr:$a))]>;
1330 // copyPhysreg is hard-coded in NVPTXInstrInfo.cpp
1331 let IsSimpleMove=1 in {
1332 def IMOV1rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$sss),
1333 "mov.pred \t$dst, $sss;", []>;
1334 def IMOV16rr: NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$sss),
1335 "mov.u16 \t$dst, $sss;", []>;
1336 def IMOV32rr: NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$sss),
1337 "mov.u32 \t$dst, $sss;", []>;
1338 def IMOV64rr: NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$sss),
1339 "mov.u64 \t$dst, $sss;", []>;
1341 def FMOV32rr: NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$src),
1342 "mov.f32 \t$dst, $src;", []>;
1343 def FMOV64rr: NVPTXInst<(outs Float64Regs:$dst), (ins Float64Regs:$src),
1344 "mov.f64 \t$dst, $src;", []>;
1346 def IMOV1ri: NVPTXInst<(outs Int1Regs:$dst), (ins i1imm:$src),
1347 "mov.pred \t$dst, $src;",
1348 [(set Int1Regs:$dst, imm:$src)]>;
1349 def IMOV16ri: NVPTXInst<(outs Int16Regs:$dst), (ins i16imm:$src),
1350 "mov.u16 \t$dst, $src;",
1351 [(set Int16Regs:$dst, imm:$src)]>;
1352 def IMOV32ri: NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$src),
1353 "mov.u32 \t$dst, $src;",
1354 [(set Int32Regs:$dst, imm:$src)]>;
1355 def IMOV64i: NVPTXInst<(outs Int64Regs:$dst), (ins i64imm:$src),
1356 "mov.u64 \t$dst, $src;",
1357 [(set Int64Regs:$dst, imm:$src)]>;
1359 def FMOV32ri: NVPTXInst<(outs Float32Regs:$dst), (ins f32imm:$src),
1360 "mov.f32 \t$dst, $src;",
1361 [(set Float32Regs:$dst, fpimm:$src)]>;
1362 def FMOV64ri: NVPTXInst<(outs Float64Regs:$dst), (ins f64imm:$src),
1363 "mov.f64 \t$dst, $src;",
1364 [(set Float64Regs:$dst, fpimm:$src)]>;
1366 def : Pat<(i32 (Wrapper texternalsym:$dst)), (IMOV32ri texternalsym:$dst)>;
1368 //---- Copy Frame Index ----
1369 def LEA_ADDRi : NVPTXInst<(outs Int32Regs:$dst), (ins MEMri:$addr),
1370 "add.u32 \t$dst, ${addr:add};",
1371 [(set Int32Regs:$dst, ADDRri:$addr)]>;
1372 def LEA_ADDRi64 : NVPTXInst<(outs Int64Regs:$dst), (ins MEMri64:$addr),
1373 "add.u64 \t$dst, ${addr:add};",
1374 [(set Int64Regs:$dst, ADDRri64:$addr)]>;
1376 //-----------------------------------
1377 // Comparison and Selection
1378 //-----------------------------------
1380 multiclass ISET_FORMAT<PatFrag OpNode, PatLeaf Mode,
1381 Instruction setp_16rr,
1382 Instruction setp_16ri,
1383 Instruction setp_16ir,
1384 Instruction setp_32rr,
1385 Instruction setp_32ri,
1386 Instruction setp_32ir,
1387 Instruction setp_64rr,
1388 Instruction setp_64ri,
1389 Instruction setp_64ir,
1390 Instruction set_16rr,
1391 Instruction set_16ri,
1392 Instruction set_16ir,
1393 Instruction set_32rr,
1394 Instruction set_32ri,
1395 Instruction set_32ir,
1396 Instruction set_64rr,
1397 Instruction set_64ri,
1398 Instruction set_64ir> {
1400 def : Pat<(i1 (OpNode Int16Regs:$a, Int16Regs:$b)),
1401 (setp_16rr Int16Regs:$a, Int16Regs:$b, Mode)>;
1402 def : Pat<(i1 (OpNode Int16Regs:$a, imm:$b)),
1403 (setp_16ri Int16Regs:$a, imm:$b, Mode)>;
1404 def : Pat<(i1 (OpNode imm:$a, Int16Regs:$b)),
1405 (setp_16ir imm:$a, Int16Regs:$b, Mode)>;
1407 def : Pat<(i1 (OpNode Int32Regs:$a, Int32Regs:$b)),
1408 (setp_32rr Int32Regs:$a, Int32Regs:$b, Mode)>;
1409 def : Pat<(i1 (OpNode Int32Regs:$a, imm:$b)),
1410 (setp_32ri Int32Regs:$a, imm:$b, Mode)>;
1411 def : Pat<(i1 (OpNode imm:$a, Int32Regs:$b)),
1412 (setp_32ir imm:$a, Int32Regs:$b, Mode)>;
1414 def : Pat<(i1 (OpNode Int64Regs:$a, Int64Regs:$b)),
1415 (setp_64rr Int64Regs:$a, Int64Regs:$b, Mode)>;
1416 def : Pat<(i1 (OpNode Int64Regs:$a, imm:$b)),
1417 (setp_64ri Int64Regs:$a, imm:$b, Mode)>;
1418 def : Pat<(i1 (OpNode imm:$a, Int64Regs:$b)),
1419 (setp_64ir imm:$a, Int64Regs:$b, Mode)>;
1422 def : Pat<(i32 (OpNode Int16Regs:$a, Int16Regs:$b)),
1423 (set_16rr Int16Regs:$a, Int16Regs:$b, Mode)>;
1424 def : Pat<(i32 (OpNode Int16Regs:$a, imm:$b)),
1425 (set_16ri Int16Regs:$a, imm:$b, Mode)>;
1426 def : Pat<(i32 (OpNode imm:$a, Int16Regs:$b)),
1427 (set_16ir imm:$a, Int16Regs:$b, Mode)>;
1429 def : Pat<(i32 (OpNode Int32Regs:$a, Int32Regs:$b)),
1430 (set_32rr Int32Regs:$a, Int32Regs:$b, Mode)>;
1431 def : Pat<(i32 (OpNode Int32Regs:$a, imm:$b)),
1432 (set_32ri Int32Regs:$a, imm:$b, Mode)>;
1433 def : Pat<(i32 (OpNode imm:$a, Int32Regs:$b)),
1434 (set_32ir imm:$a, Int32Regs:$b, Mode)>;
1436 def : Pat<(i32 (OpNode Int64Regs:$a, Int64Regs:$b)),
1437 (set_64rr Int64Regs:$a, Int64Regs:$b, Mode)>;
1438 def : Pat<(i32 (OpNode Int64Regs:$a, imm:$b)),
1439 (set_64ri Int64Regs:$a, imm:$b, Mode)>;
1440 def : Pat<(i32 (OpNode imm:$a, Int64Regs:$b)),
1441 (set_64ir imm:$a, Int64Regs:$b, Mode)>;
1444 multiclass ISET_FORMAT_SIGNED<PatFrag OpNode, PatLeaf Mode>
1445 : ISET_FORMAT<OpNode, Mode,
1446 SETP_s16rr, SETP_s16ri, SETP_s16ir,
1447 SETP_s32rr, SETP_s32ri, SETP_s32ir,
1448 SETP_s64rr, SETP_s64ri, SETP_s64ir,
1449 SET_s16rr, SET_s16ri, SET_s16ir,
1450 SET_s32rr, SET_s32ri, SET_s32ir,
1451 SET_s64rr, SET_s64ri, SET_s64ir> {
1452 // TableGen doesn't like empty multiclasses
1453 def : PatLeaf<(i32 0)>;
1456 multiclass ISET_FORMAT_UNSIGNED<PatFrag OpNode, PatLeaf Mode>
1457 : ISET_FORMAT<OpNode, Mode,
1458 SETP_u16rr, SETP_u16ri, SETP_u16ir,
1459 SETP_u32rr, SETP_u32ri, SETP_u32ir,
1460 SETP_u64rr, SETP_u64ri, SETP_u64ir,
1461 SET_u16rr, SET_u16ri, SET_u16ir,
1462 SET_u32rr, SET_u32ri, SET_u32ir,
1463 SET_u64rr, SET_u64ri, SET_u64ir> {
1464 // TableGen doesn't like empty multiclasses
1465 def : PatLeaf<(i32 0)>;
1468 defm : ISET_FORMAT_SIGNED<setgt, CmpGT>;
1469 defm : ISET_FORMAT_UNSIGNED<setugt, CmpGT>;
1470 defm : ISET_FORMAT_SIGNED<setlt, CmpLT>;
1471 defm : ISET_FORMAT_UNSIGNED<setult, CmpLT>;
1472 defm : ISET_FORMAT_SIGNED<setge, CmpGE>;
1473 defm : ISET_FORMAT_UNSIGNED<setuge, CmpGE>;
1474 defm : ISET_FORMAT_SIGNED<setle, CmpLE>;
1475 defm : ISET_FORMAT_UNSIGNED<setule, CmpLE>;
1476 defm : ISET_FORMAT_SIGNED<seteq, CmpEQ>;
1477 defm : ISET_FORMAT_UNSIGNED<setueq, CmpEQ>;
1478 defm : ISET_FORMAT_SIGNED<setne, CmpNE>;
1479 defm : ISET_FORMAT_UNSIGNED<setune, CmpNE>;
1482 def : Pat<(setne Int1Regs:$a, Int1Regs:$b),
1483 (XORb1rr Int1Regs:$a, Int1Regs:$b)>;
1484 def : Pat<(setune Int1Regs:$a, Int1Regs:$b),
1485 (XORb1rr Int1Regs:$a, Int1Regs:$b)>;
1487 def : Pat<(seteq Int1Regs:$a, Int1Regs:$b),
1488 (NOT1 (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1489 def : Pat<(setueq Int1Regs:$a, Int1Regs:$b),
1490 (NOT1 (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1492 // i1 compare -> i32
1493 def : Pat<(i32 (setne Int1Regs:$a, Int1Regs:$b)),
1494 (SELP_u32ii -1, 0, (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1495 def : Pat<(i32 (setne Int1Regs:$a, Int1Regs:$b)),
1496 (SELP_u32ii 0, -1, (XORb1rr Int1Regs:$a, Int1Regs:$b))>;
1500 multiclass FSET_FORMAT<PatFrag OpNode, PatLeaf Mode, PatLeaf ModeFTZ> {
1502 def : Pat<(i1 (OpNode Float32Regs:$a, Float32Regs:$b)),
1503 (SETP_f32rr Float32Regs:$a, Float32Regs:$b, ModeFTZ)>,
1504 Requires<[doF32FTZ]>;
1505 def : Pat<(i1 (OpNode Float32Regs:$a, Float32Regs:$b)),
1506 (SETP_f32rr Float32Regs:$a, Float32Regs:$b, Mode)>;
1507 def : Pat<(i1 (OpNode Float32Regs:$a, fpimm:$b)),
1508 (SETP_f32ri Float32Regs:$a, fpimm:$b, ModeFTZ)>,
1509 Requires<[doF32FTZ]>;
1510 def : Pat<(i1 (OpNode Float32Regs:$a, fpimm:$b)),
1511 (SETP_f32ri Float32Regs:$a, fpimm:$b, Mode)>;
1512 def : Pat<(i1 (OpNode fpimm:$a, Float32Regs:$b)),
1513 (SETP_f32ir fpimm:$a, Float32Regs:$b, ModeFTZ)>,
1514 Requires<[doF32FTZ]>;
1515 def : Pat<(i1 (OpNode fpimm:$a, Float32Regs:$b)),
1516 (SETP_f32ir fpimm:$a, Float32Regs:$b, Mode)>;
1519 def : Pat<(i1 (OpNode Float64Regs:$a, Float64Regs:$b)),
1520 (SETP_f64rr Float64Regs:$a, Float64Regs:$b, Mode)>;
1521 def : Pat<(i1 (OpNode Float64Regs:$a, fpimm:$b)),
1522 (SETP_f64ri Float64Regs:$a, fpimm:$b, Mode)>;
1523 def : Pat<(i1 (OpNode fpimm:$a, Float64Regs:$b)),
1524 (SETP_f64ir fpimm:$a, Float64Regs:$b, Mode)>;
1527 def : Pat<(i32 (OpNode Float32Regs:$a, Float32Regs:$b)),
1528 (SET_f32rr Float32Regs:$a, Float32Regs:$b, ModeFTZ)>,
1529 Requires<[doF32FTZ]>;
1530 def : Pat<(i32 (OpNode Float32Regs:$a, Float32Regs:$b)),
1531 (SET_f32rr Float32Regs:$a, Float32Regs:$b, Mode)>;
1532 def : Pat<(i32 (OpNode Float32Regs:$a, fpimm:$b)),
1533 (SET_f32ri Float32Regs:$a, fpimm:$b, ModeFTZ)>,
1534 Requires<[doF32FTZ]>;
1535 def : Pat<(i32 (OpNode Float32Regs:$a, fpimm:$b)),
1536 (SET_f32ri Float32Regs:$a, fpimm:$b, Mode)>;
1537 def : Pat<(i32 (OpNode fpimm:$a, Float32Regs:$b)),
1538 (SET_f32ir fpimm:$a, Float32Regs:$b, ModeFTZ)>,
1539 Requires<[doF32FTZ]>;
1540 def : Pat<(i32 (OpNode fpimm:$a, Float32Regs:$b)),
1541 (SET_f32ir fpimm:$a, Float32Regs:$b, Mode)>;
1544 def : Pat<(i32 (OpNode Float64Regs:$a, Float64Regs:$b)),
1545 (SET_f64rr Float64Regs:$a, Float64Regs:$b, Mode)>;
1546 def : Pat<(i32 (OpNode Float64Regs:$a, fpimm:$b)),
1547 (SET_f64ri Float64Regs:$a, fpimm:$b, Mode)>;
1548 def : Pat<(i32 (OpNode fpimm:$a, Float64Regs:$b)),
1549 (SET_f64ir fpimm:$a, Float64Regs:$b, Mode)>;
1552 defm FSetGT : FSET_FORMAT<setogt, CmpGT, CmpGT_FTZ>;
1553 defm FSetLT : FSET_FORMAT<setolt, CmpLT, CmpLT_FTZ>;
1554 defm FSetGE : FSET_FORMAT<setoge, CmpGE, CmpGE_FTZ>;
1555 defm FSetLE : FSET_FORMAT<setole, CmpLE, CmpLE_FTZ>;
1556 defm FSetEQ : FSET_FORMAT<setoeq, CmpEQ, CmpEQ_FTZ>;
1557 defm FSetNE : FSET_FORMAT<setone, CmpNE, CmpNE_FTZ>;
1559 defm FSetUGT : FSET_FORMAT<setugt, CmpGTU, CmpGTU_FTZ>;
1560 defm FSetULT : FSET_FORMAT<setult, CmpLTU, CmpLTU_FTZ>;
1561 defm FSetUGE : FSET_FORMAT<setuge, CmpGEU, CmpGEU_FTZ>;
1562 defm FSetULE : FSET_FORMAT<setule, CmpLEU, CmpLEU_FTZ>;
1563 defm FSetUEQ : FSET_FORMAT<setueq, CmpEQU, CmpEQU_FTZ>;
1564 defm FSetUNE : FSET_FORMAT<setune, CmpNEU, CmpNEU_FTZ>;
1566 defm FSetNUM : FSET_FORMAT<seto, CmpNUM, CmpNUM_FTZ>;
1567 defm FSetNAN : FSET_FORMAT<setuo, CmpNAN, CmpNAN_FTZ>;
1569 //def ld_param : SDNode<"NVPTXISD::LOAD_PARAM", SDTLoad,
1570 // [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
1572 def SDTDeclareParamProfile : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
1574 def SDTDeclareScalarParamProfile : SDTypeProfile<0, 3, [SDTCisInt<0>,
1575 SDTCisInt<1>, SDTCisInt<2>]>;
1576 def SDTLoadParamProfile : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
1577 def SDTLoadParamV2Profile : SDTypeProfile<2, 2, [SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisInt<3>]>;
1578 def SDTLoadParamV4Profile : SDTypeProfile<4, 2, [SDTCisInt<4>, SDTCisInt<5>]>;
1579 def SDTPrintCallProfile : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
1580 def SDTPrintCallUniProfile : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
1581 def SDTStoreParamProfile : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>]>;
1582 def SDTStoreParamV2Profile : SDTypeProfile<0, 4, [SDTCisInt<0>, SDTCisInt<1>]>;
1583 def SDTStoreParamV4Profile : SDTypeProfile<0, 6, [SDTCisInt<0>, SDTCisInt<1>]>;
1584 def SDTStoreParam32Profile : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>]>;
1585 def SDTCallArgProfile : SDTypeProfile<0, 2, [SDTCisInt<0>]>;
1586 def SDTCallArgMarkProfile : SDTypeProfile<0, 0, []>;
1587 def SDTCallVoidProfile : SDTypeProfile<0, 1, []>;
1588 def SDTCallValProfile : SDTypeProfile<1, 0, []>;
1589 def SDTMoveParamProfile : SDTypeProfile<1, 1, []>;
1590 def SDTStoreRetvalProfile : SDTypeProfile<0, 2, [SDTCisInt<0>]>;
1591 def SDTStoreRetvalV2Profile : SDTypeProfile<0, 3, [SDTCisInt<0>]>;
1592 def SDTStoreRetvalV4Profile : SDTypeProfile<0, 5, [SDTCisInt<0>]>;
1593 def SDTPseudoUseParamProfile : SDTypeProfile<0, 1, []>;
1595 def DeclareParam : SDNode<"NVPTXISD::DeclareParam", SDTDeclareParamProfile,
1596 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1597 def DeclareScalarParam : SDNode<"NVPTXISD::DeclareScalarParam",
1598 SDTDeclareScalarParamProfile,
1599 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1600 def DeclareRetParam : SDNode<"NVPTXISD::DeclareRetParam",
1601 SDTDeclareParamProfile,
1602 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1603 def DeclareRet : SDNode<"NVPTXISD::DeclareRet", SDTDeclareScalarParamProfile,
1604 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1605 def LoadParam : SDNode<"NVPTXISD::LoadParam", SDTLoadParamProfile,
1606 [SDNPHasChain, SDNPMayLoad, SDNPOutGlue, SDNPInGlue]>;
1607 def LoadParamV2 : SDNode<"NVPTXISD::LoadParamV2", SDTLoadParamV2Profile,
1608 [SDNPHasChain, SDNPMayLoad, SDNPOutGlue, SDNPInGlue]>;
1609 def LoadParamV4 : SDNode<"NVPTXISD::LoadParamV4", SDTLoadParamV4Profile,
1610 [SDNPHasChain, SDNPMayLoad, SDNPOutGlue, SDNPInGlue]>;
1611 def PrintCall : SDNode<"NVPTXISD::PrintCall", SDTPrintCallProfile,
1612 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1613 def PrintCallUni : SDNode<"NVPTXISD::PrintCallUni", SDTPrintCallUniProfile,
1614 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1615 def StoreParam : SDNode<"NVPTXISD::StoreParam", SDTStoreParamProfile,
1616 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1617 def StoreParamV2 : SDNode<"NVPTXISD::StoreParamV2", SDTStoreParamV2Profile,
1618 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1619 def StoreParamV4 : SDNode<"NVPTXISD::StoreParamV4", SDTStoreParamV4Profile,
1620 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1621 def StoreParamU32 : SDNode<"NVPTXISD::StoreParamU32", SDTStoreParam32Profile,
1622 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1623 def StoreParamS32 : SDNode<"NVPTXISD::StoreParamS32", SDTStoreParam32Profile,
1624 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1625 def CallArgBegin : SDNode<"NVPTXISD::CallArgBegin", SDTCallArgMarkProfile,
1626 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1627 def CallArg : SDNode<"NVPTXISD::CallArg", SDTCallArgProfile,
1628 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1629 def LastCallArg : SDNode<"NVPTXISD::LastCallArg", SDTCallArgProfile,
1630 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1631 def CallArgEnd : SDNode<"NVPTXISD::CallArgEnd", SDTCallVoidProfile,
1632 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1633 def CallVoid : SDNode<"NVPTXISD::CallVoid", SDTCallVoidProfile,
1634 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1635 def Prototype : SDNode<"NVPTXISD::Prototype", SDTCallVoidProfile,
1636 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1637 def CallVal : SDNode<"NVPTXISD::CallVal", SDTCallValProfile,
1638 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1639 def MoveParam : SDNode<"NVPTXISD::MoveParam", SDTMoveParamProfile,
1641 def StoreRetval : SDNode<"NVPTXISD::StoreRetval", SDTStoreRetvalProfile,
1642 [SDNPHasChain, SDNPSideEffect]>;
1643 def StoreRetvalV2 : SDNode<"NVPTXISD::StoreRetvalV2", SDTStoreRetvalV2Profile,
1644 [SDNPHasChain, SDNPSideEffect]>;
1645 def StoreRetvalV4 : SDNode<"NVPTXISD::StoreRetvalV4", SDTStoreRetvalV4Profile,
1646 [SDNPHasChain, SDNPSideEffect]>;
1647 def PseudoUseParam : SDNode<"NVPTXISD::PseudoUseParam",
1648 SDTPseudoUseParamProfile,
1649 [SDNPHasChain, SDNPOutGlue, SDNPInGlue, SDNPSideEffect]>;
1650 def RETURNNode : SDNode<"NVPTXISD::RETURN", SDTCallArgMarkProfile,
1651 [SDNPHasChain, SDNPSideEffect]>;
1653 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1654 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1655 !strconcat(!strconcat("ld.param", opstr),
1656 "\t$dst, [retval0+$b];"),
1659 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
1660 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1661 !strconcat(!strconcat("mov", opstr),
1662 "\t$dst, retval$b;"),
1663 [(set regclass:$dst, (LoadParam (i32 0), (i32 imm:$b)))]>;
1665 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1666 NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
1667 !strconcat(!strconcat("ld.param.v2", opstr),
1668 "\t{{$dst, $dst2}}, [retval0+$b];"), []>;
1670 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
1671 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
1674 !strconcat(!strconcat("ld.param.v4", opstr),
1675 "\t{{$dst, $dst2, $dst3, $dst4}}, [retval0+$b];"), []>;
1677 class StoreParamInst<NVPTXRegClass regclass, string opstr> :
1678 NVPTXInst<(outs), (ins regclass:$val, i32imm:$a, i32imm:$b),
1679 !strconcat(!strconcat("st.param", opstr),
1680 "\t[param$a+$b], $val;"),
1683 class StoreParamV2Inst<NVPTXRegClass regclass, string opstr> :
1684 NVPTXInst<(outs), (ins regclass:$val, regclass:$val2,
1685 i32imm:$a, i32imm:$b),
1686 !strconcat(!strconcat("st.param.v2", opstr),
1687 "\t[param$a+$b], {{$val, $val2}};"),
1690 class StoreParamV4Inst<NVPTXRegClass regclass, string opstr> :
1691 NVPTXInst<(outs), (ins regclass:$val, regclass:$val1, regclass:$val2,
1692 regclass:$val3, i32imm:$a, i32imm:$b),
1693 !strconcat(!strconcat("st.param.v4", opstr),
1694 "\t[param$a+$b], {{$val, $val2, $val3, $val4}};"),
1697 class StoreRetvalInst<NVPTXRegClass regclass, string opstr> :
1698 NVPTXInst<(outs), (ins regclass:$val, i32imm:$a),
1699 !strconcat(!strconcat("st.param", opstr),
1700 "\t[func_retval0+$a], $val;"),
1703 class StoreRetvalV2Inst<NVPTXRegClass regclass, string opstr> :
1704 NVPTXInst<(outs), (ins regclass:$val, regclass:$val2, i32imm:$a),
1705 !strconcat(!strconcat("st.param.v2", opstr),
1706 "\t[func_retval0+$a], {{$val, $val2}};"),
1709 class StoreRetvalV4Inst<NVPTXRegClass regclass, string opstr> :
1711 (ins regclass:$val, regclass:$val2, regclass:$val3,
1712 regclass:$val4, i32imm:$a),
1713 !strconcat(!strconcat("st.param.v4", opstr),
1714 "\t[func_retval0+$a], {{$val, $val2, $val3, $val4}};"),
1717 def PrintCallRetInst1 : NVPTXInst<(outs), (ins),
1719 [(PrintCall (i32 1))]>;
1720 def PrintCallRetInst2 : NVPTXInst<(outs), (ins),
1721 "call (retval0, retval1), ",
1722 [(PrintCall (i32 2))]>;
1723 def PrintCallRetInst3 : NVPTXInst<(outs), (ins),
1724 "call (retval0, retval1, retval2), ",
1725 [(PrintCall (i32 3))]>;
1726 def PrintCallRetInst4 : NVPTXInst<(outs), (ins),
1727 "call (retval0, retval1, retval2, retval3), ",
1728 [(PrintCall (i32 4))]>;
1729 def PrintCallRetInst5 : NVPTXInst<(outs), (ins),
1730 "call (retval0, retval1, retval2, retval3, retval4), ",
1731 [(PrintCall (i32 5))]>;
1732 def PrintCallRetInst6 : NVPTXInst<(outs), (ins),
1733 "call (retval0, retval1, retval2, retval3, retval4, retval5), ",
1734 [(PrintCall (i32 6))]>;
1735 def PrintCallRetInst7 : NVPTXInst<(outs), (ins),
1736 "call (retval0, retval1, retval2, retval3, retval4, retval5, retval6), ",
1737 [(PrintCall (i32 7))]>;
1738 def PrintCallRetInst8 : NVPTXInst<(outs), (ins),
1739 !strconcat("call (retval0, retval1, retval2, retval3, retval4",
1740 ", retval5, retval6, retval7), "),
1741 [(PrintCall (i32 8))]>;
1743 def PrintCallNoRetInst : NVPTXInst<(outs), (ins), "call ",
1744 [(PrintCall (i32 0))]>;
1746 def PrintCallUniRetInst1 : NVPTXInst<(outs), (ins),
1747 "call.uni (retval0), ",
1748 [(PrintCallUni (i32 1))]>;
1749 def PrintCallUniRetInst2 : NVPTXInst<(outs), (ins),
1750 "call.uni (retval0, retval1), ",
1751 [(PrintCallUni (i32 2))]>;
1752 def PrintCallUniRetInst3 : NVPTXInst<(outs), (ins),
1753 "call.uni (retval0, retval1, retval2), ",
1754 [(PrintCallUni (i32 3))]>;
1755 def PrintCallUniRetInst4 : NVPTXInst<(outs), (ins),
1756 "call.uni (retval0, retval1, retval2, retval3), ",
1757 [(PrintCallUni (i32 4))]>;
1758 def PrintCallUniRetInst5 : NVPTXInst<(outs), (ins),
1759 "call.uni (retval0, retval1, retval2, retval3, retval4), ",
1760 [(PrintCallUni (i32 5))]>;
1761 def PrintCallUniRetInst6 : NVPTXInst<(outs), (ins),
1762 "call.uni (retval0, retval1, retval2, retval3, retval4, retval5), ",
1763 [(PrintCallUni (i32 6))]>;
1764 def PrintCallUniRetInst7 : NVPTXInst<(outs), (ins),
1765 "call.uni (retval0, retval1, retval2, retval3, retval4, retval5, retval6), ",
1766 [(PrintCallUni (i32 7))]>;
1767 def PrintCallUniRetInst8 : NVPTXInst<(outs), (ins),
1768 !strconcat("call.uni (retval0, retval1, retval2, retval3, retval4",
1769 ", retval5, retval6, retval7), "),
1770 [(PrintCallUni (i32 8))]>;
1772 def PrintCallUniNoRetInst : NVPTXInst<(outs), (ins), "call.uni ",
1773 [(PrintCallUni (i32 0))]>;
1775 def LoadParamMemI64 : LoadParamMemInst<Int64Regs, ".b64">;
1776 def LoadParamMemI32 : LoadParamMemInst<Int32Regs, ".b32">;
1777 def LoadParamMemI16 : LoadParamMemInst<Int16Regs, ".b16">;
1778 def LoadParamMemI8 : LoadParamMemInst<Int16Regs, ".b8">;
1779 def LoadParamMemV2I64 : LoadParamV2MemInst<Int64Regs, ".b64">;
1780 def LoadParamMemV2I32 : LoadParamV2MemInst<Int32Regs, ".b32">;
1781 def LoadParamMemV2I16 : LoadParamV2MemInst<Int16Regs, ".b16">;
1782 def LoadParamMemV2I8 : LoadParamV2MemInst<Int16Regs, ".b8">;
1783 def LoadParamMemV4I32 : LoadParamV4MemInst<Int32Regs, ".b32">;
1784 def LoadParamMemV4I16 : LoadParamV4MemInst<Int16Regs, ".b16">;
1785 def LoadParamMemV4I8 : LoadParamV4MemInst<Int16Regs, ".b8">;
1786 def LoadParamMemF32 : LoadParamMemInst<Float32Regs, ".f32">;
1787 def LoadParamMemF64 : LoadParamMemInst<Float64Regs, ".f64">;
1788 def LoadParamMemV2F32 : LoadParamV2MemInst<Float32Regs, ".f32">;
1789 def LoadParamMemV2F64 : LoadParamV2MemInst<Float64Regs, ".f64">;
1790 def LoadParamMemV4F32 : LoadParamV4MemInst<Float32Regs, ".f32">;
1792 def StoreParamI64 : StoreParamInst<Int64Regs, ".b64">;
1793 def StoreParamI32 : StoreParamInst<Int32Regs, ".b32">;
1795 def StoreParamI16 : StoreParamInst<Int16Regs, ".b16">;
1796 def StoreParamI8 : StoreParamInst<Int16Regs, ".b8">;
1797 def StoreParamV2I64 : StoreParamV2Inst<Int64Regs, ".b64">;
1798 def StoreParamV2I32 : StoreParamV2Inst<Int32Regs, ".b32">;
1799 def StoreParamV2I16 : StoreParamV2Inst<Int16Regs, ".b16">;
1800 def StoreParamV2I8 : StoreParamV2Inst<Int16Regs, ".b8">;
1802 // FIXME: StoreParamV4Inst crashes llvm-tblgen :(
1803 //def StoreParamV4I32 : StoreParamV4Inst<Int32Regs, ".b32">;
1804 def StoreParamV4I32 : NVPTXInst<(outs), (ins Int32Regs:$val, Int32Regs:$val2,
1805 Int32Regs:$val3, Int32Regs:$val4,
1806 i32imm:$a, i32imm:$b),
1807 "st.param.b32\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1810 def StoreParamV4I16 : NVPTXInst<(outs), (ins Int16Regs:$val, Int16Regs:$val2,
1811 Int16Regs:$val3, Int16Regs:$val4,
1812 i32imm:$a, i32imm:$b),
1813 "st.param.v4.b16\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1816 def StoreParamV4I8 : NVPTXInst<(outs), (ins Int16Regs:$val, Int16Regs:$val2,
1817 Int16Regs:$val3, Int16Regs:$val4,
1818 i32imm:$a, i32imm:$b),
1819 "st.param.v4.b8\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1822 def StoreParamF32 : StoreParamInst<Float32Regs, ".f32">;
1823 def StoreParamF64 : StoreParamInst<Float64Regs, ".f64">;
1824 def StoreParamV2F32 : StoreParamV2Inst<Float32Regs, ".f32">;
1825 def StoreParamV2F64 : StoreParamV2Inst<Float64Regs, ".f64">;
1826 // FIXME: StoreParamV4Inst crashes llvm-tblgen :(
1827 //def StoreParamV4F32 : StoreParamV4Inst<Float32Regs, ".f32">;
1828 def StoreParamV4F32 : NVPTXInst<(outs),
1829 (ins Float32Regs:$val, Float32Regs:$val2,
1830 Float32Regs:$val3, Float32Regs:$val4,
1831 i32imm:$a, i32imm:$b),
1832 "st.param.v4.f32\t[param$a+$b], {{$val, $val2, $val3, $val4}};",
1836 def StoreRetvalI64 : StoreRetvalInst<Int64Regs, ".b64">;
1837 def StoreRetvalI32 : StoreRetvalInst<Int32Regs, ".b32">;
1838 def StoreRetvalI16 : StoreRetvalInst<Int16Regs, ".b16">;
1839 def StoreRetvalI8 : StoreRetvalInst<Int16Regs, ".b8">;
1840 def StoreRetvalV2I64 : StoreRetvalV2Inst<Int64Regs, ".b64">;
1841 def StoreRetvalV2I32 : StoreRetvalV2Inst<Int32Regs, ".b32">;
1842 def StoreRetvalV2I16 : StoreRetvalV2Inst<Int16Regs, ".b16">;
1843 def StoreRetvalV2I8 : StoreRetvalV2Inst<Int16Regs, ".b8">;
1844 def StoreRetvalV4I32 : StoreRetvalV4Inst<Int32Regs, ".b32">;
1845 def StoreRetvalV4I16 : StoreRetvalV4Inst<Int16Regs, ".b16">;
1846 def StoreRetvalV4I8 : StoreRetvalV4Inst<Int16Regs, ".b8">;
1848 def StoreRetvalF64 : StoreRetvalInst<Float64Regs, ".f64">;
1849 def StoreRetvalF32 : StoreRetvalInst<Float32Regs, ".f32">;
1850 def StoreRetvalV2F64 : StoreRetvalV2Inst<Float64Regs, ".f64">;
1851 def StoreRetvalV2F32 : StoreRetvalV2Inst<Float32Regs, ".f32">;
1852 def StoreRetvalV4F32 : StoreRetvalV4Inst<Float32Regs, ".f32">;
1854 def CallArgBeginInst : NVPTXInst<(outs), (ins), "(", [(CallArgBegin)]>;
1855 def CallArgEndInst1 : NVPTXInst<(outs), (ins), ");", [(CallArgEnd (i32 1))]>;
1856 def CallArgEndInst0 : NVPTXInst<(outs), (ins), ")", [(CallArgEnd (i32 0))]>;
1857 def RETURNInst : NVPTXInst<(outs), (ins), "ret;", [(RETURNNode)]>;
1859 class CallArgInst<NVPTXRegClass regclass> :
1860 NVPTXInst<(outs), (ins regclass:$a), "$a, ",
1861 [(CallArg (i32 0), regclass:$a)]>;
1863 class LastCallArgInst<NVPTXRegClass regclass> :
1864 NVPTXInst<(outs), (ins regclass:$a), "$a",
1865 [(LastCallArg (i32 0), regclass:$a)]>;
1867 def CallArgI64 : CallArgInst<Int64Regs>;
1868 def CallArgI32 : CallArgInst<Int32Regs>;
1869 def CallArgI16 : CallArgInst<Int16Regs>;
1871 def CallArgF64 : CallArgInst<Float64Regs>;
1872 def CallArgF32 : CallArgInst<Float32Regs>;
1874 def LastCallArgI64 : LastCallArgInst<Int64Regs>;
1875 def LastCallArgI32 : LastCallArgInst<Int32Regs>;
1876 def LastCallArgI16 : LastCallArgInst<Int16Regs>;
1878 def LastCallArgF64 : LastCallArgInst<Float64Regs>;
1879 def LastCallArgF32 : LastCallArgInst<Float32Regs>;
1881 def CallArgI32imm : NVPTXInst<(outs), (ins i32imm:$a), "$a, ",
1882 [(CallArg (i32 0), (i32 imm:$a))]>;
1883 def LastCallArgI32imm : NVPTXInst<(outs), (ins i32imm:$a), "$a",
1884 [(LastCallArg (i32 0), (i32 imm:$a))]>;
1886 def CallArgParam : NVPTXInst<(outs), (ins i32imm:$a), "param$a, ",
1887 [(CallArg (i32 1), (i32 imm:$a))]>;
1888 def LastCallArgParam : NVPTXInst<(outs), (ins i32imm:$a), "param$a",
1889 [(LastCallArg (i32 1), (i32 imm:$a))]>;
1891 def CallVoidInst : NVPTXInst<(outs), (ins imem:$addr),
1893 [(CallVoid (Wrapper tglobaladdr:$addr))]>;
1894 def CallVoidInstReg : NVPTXInst<(outs), (ins Int32Regs:$addr),
1896 [(CallVoid Int32Regs:$addr)]>;
1897 def CallVoidInstReg64 : NVPTXInst<(outs), (ins Int64Regs:$addr),
1899 [(CallVoid Int64Regs:$addr)]>;
1900 def PrototypeInst : NVPTXInst<(outs), (ins i32imm:$val),
1901 ", prototype_$val;",
1902 [(Prototype (i32 imm:$val))]>;
1904 def DeclareRetMemInst : NVPTXInst<(outs),
1905 (ins i32imm:$align, i32imm:$size, i32imm:$num),
1906 ".param .align $align .b8 retval$num[$size];",
1907 [(DeclareRetParam (i32 imm:$align), (i32 imm:$size), (i32 imm:$num))]>;
1908 def DeclareRetScalarInst : NVPTXInst<(outs), (ins i32imm:$size, i32imm:$num),
1909 ".param .b$size retval$num;",
1910 [(DeclareRet (i32 1), (i32 imm:$size), (i32 imm:$num))]>;
1911 def DeclareRetRegInst : NVPTXInst<(outs), (ins i32imm:$size, i32imm:$num),
1912 ".reg .b$size retval$num;",
1913 [(DeclareRet (i32 2), (i32 imm:$size), (i32 imm:$num))]>;
1915 def DeclareParamInst : NVPTXInst<(outs),
1916 (ins i32imm:$align, i32imm:$a, i32imm:$size),
1917 ".param .align $align .b8 param$a[$size];",
1918 [(DeclareParam (i32 imm:$align), (i32 imm:$a), (i32 imm:$size))]>;
1919 def DeclareScalarParamInst : NVPTXInst<(outs), (ins i32imm:$a, i32imm:$size),
1920 ".param .b$size param$a;",
1921 [(DeclareScalarParam (i32 imm:$a), (i32 imm:$size), (i32 0))]>;
1922 def DeclareScalarRegInst : NVPTXInst<(outs), (ins i32imm:$a, i32imm:$size),
1923 ".reg .b$size param$a;",
1924 [(DeclareScalarParam (i32 imm:$a), (i32 imm:$size), (i32 1))]>;
1926 class MoveParamInst<NVPTXRegClass regclass, string asmstr> :
1927 NVPTXInst<(outs regclass:$dst), (ins regclass:$src),
1928 !strconcat(!strconcat("mov", asmstr), "\t$dst, $src;"),
1929 [(set regclass:$dst, (MoveParam regclass:$src))]>;
1931 def MoveParamI64 : MoveParamInst<Int64Regs, ".b64">;
1932 def MoveParamI32 : MoveParamInst<Int32Regs, ".b32">;
1933 def MoveParamI16 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
1934 "cvt.u16.u32\t$dst, $src;",
1935 [(set Int16Regs:$dst, (MoveParam Int16Regs:$src))]>;
1936 def MoveParamF64 : MoveParamInst<Float64Regs, ".f64">;
1937 def MoveParamF32 : MoveParamInst<Float32Regs, ".f32">;
1939 class PseudoUseParamInst<NVPTXRegClass regclass> :
1940 NVPTXInst<(outs), (ins regclass:$src),
1941 "// Pseudo use of $src",
1942 [(PseudoUseParam regclass:$src)]>;
1944 def PseudoUseParamI64 : PseudoUseParamInst<Int64Regs>;
1945 def PseudoUseParamI32 : PseudoUseParamInst<Int32Regs>;
1946 def PseudoUseParamI16 : PseudoUseParamInst<Int16Regs>;
1947 def PseudoUseParamF64 : PseudoUseParamInst<Float64Regs>;
1948 def PseudoUseParamF32 : PseudoUseParamInst<Float32Regs>;
1952 // Load / Store Handling
1954 multiclass LD<NVPTXRegClass regclass> {
1955 def _avar : NVPTXInst<(outs regclass:$dst),
1956 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1957 i32imm:$fromWidth, imem:$addr),
1958 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
1959 "$fromWidth \t$dst, [$addr];"), []>;
1960 def _areg : NVPTXInst<(outs regclass:$dst),
1961 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1962 i32imm:$fromWidth, Int32Regs:$addr),
1963 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
1964 "$fromWidth \t$dst, [$addr];"), []>;
1965 def _areg_64 : NVPTXInst<(outs regclass:$dst),
1966 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1967 i32imm:$fromWidth, Int64Regs:$addr),
1968 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$fromWidth",
1969 " \t$dst, [$addr];"), []>;
1970 def _ari : NVPTXInst<(outs regclass:$dst),
1971 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1972 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
1973 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
1974 "$fromWidth \t$dst, [$addr+$offset];"), []>;
1975 def _ari_64 : NVPTXInst<(outs regclass:$dst),
1976 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1977 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
1978 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$fromWidth",
1979 " \t$dst, [$addr+$offset];"), []>;
1980 def _asi : NVPTXInst<(outs regclass:$dst),
1981 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
1982 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
1983 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
1984 "$fromWidth \t$dst, [$addr+$offset];"), []>;
1987 let mayLoad=1, neverHasSideEffects=1 in {
1988 defm LD_i8 : LD<Int16Regs>;
1989 defm LD_i16 : LD<Int16Regs>;
1990 defm LD_i32 : LD<Int32Regs>;
1991 defm LD_i64 : LD<Int64Regs>;
1992 defm LD_f32 : LD<Float32Regs>;
1993 defm LD_f64 : LD<Float64Regs>;
1996 multiclass ST<NVPTXRegClass regclass> {
1997 def _avar : NVPTXInst<(outs),
1998 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
1999 LdStCode:$Sign, i32imm:$toWidth, imem:$addr),
2000 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
2001 " \t[$addr], $src;"), []>;
2002 def _areg : NVPTXInst<(outs),
2003 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2004 LdStCode:$Sign, i32imm:$toWidth, Int32Regs:$addr),
2005 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
2006 " \t[$addr], $src;"), []>;
2007 def _areg_64 : NVPTXInst<(outs),
2008 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2009 LdStCode:$Sign, i32imm:$toWidth, Int64Regs:$addr),
2010 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth ",
2011 "\t[$addr], $src;"), []>;
2012 def _ari : NVPTXInst<(outs),
2013 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2014 LdStCode:$Sign, i32imm:$toWidth, Int32Regs:$addr, i32imm:$offset),
2015 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
2016 " \t[$addr+$offset], $src;"), []>;
2017 def _ari_64 : NVPTXInst<(outs),
2018 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2019 LdStCode:$Sign, i32imm:$toWidth, Int64Regs:$addr, i32imm:$offset),
2020 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth ",
2021 "\t[$addr+$offset], $src;"), []>;
2022 def _asi : NVPTXInst<(outs),
2023 (ins regclass:$src, LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec,
2024 LdStCode:$Sign, i32imm:$toWidth, imem:$addr, i32imm:$offset),
2025 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}$toWidth",
2026 " \t[$addr+$offset], $src;"), []>;
2029 let mayStore=1, neverHasSideEffects=1 in {
2030 defm ST_i8 : ST<Int16Regs>;
2031 defm ST_i16 : ST<Int16Regs>;
2032 defm ST_i32 : ST<Int32Regs>;
2033 defm ST_i64 : ST<Int64Regs>;
2034 defm ST_f32 : ST<Float32Regs>;
2035 defm ST_f64 : ST<Float64Regs>;
2038 // The following is used only in and after vector elementizations.
2039 // Vector elementization happens at the machine instruction level, so the
2040 // following instruction
2041 // never appears in the DAG.
2042 multiclass LD_VEC<NVPTXRegClass regclass> {
2043 def _v2_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2044 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2045 i32imm:$fromWidth, imem:$addr),
2046 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2047 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2048 def _v2_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2049 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2050 i32imm:$fromWidth, Int32Regs:$addr),
2051 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2052 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2053 def _v2_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2054 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2055 i32imm:$fromWidth, Int64Regs:$addr),
2056 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2057 "$fromWidth \t{{$dst1, $dst2}}, [$addr];"), []>;
2058 def _v2_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2059 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2060 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
2061 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2062 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2063 def _v2_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2064 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2065 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
2066 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2067 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2068 def _v2_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
2069 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2070 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
2071 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2072 "$fromWidth \t{{$dst1, $dst2}}, [$addr+$offset];"), []>;
2073 def _v4_avar : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2074 regclass:$dst3, regclass:$dst4),
2075 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2076 i32imm:$fromWidth, imem:$addr),
2077 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2078 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2079 def _v4_areg : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2081 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2082 i32imm:$fromWidth, Int32Regs:$addr),
2083 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2084 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2085 def _v4_areg_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2086 regclass:$dst3, regclass:$dst4),
2087 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2088 i32imm:$fromWidth, Int64Regs:$addr),
2089 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2090 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr];"), []>;
2091 def _v4_ari : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2093 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2094 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
2095 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2096 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
2098 def _v4_ari_64 : NVPTXInst<(outs regclass:$dst1, regclass:$dst2,
2099 regclass:$dst3, regclass:$dst4),
2100 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2101 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
2102 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2103 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
2105 def _v4_asi : NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
2107 (ins LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2108 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
2109 !strconcat("ld${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2110 "$fromWidth \t{{$dst1, $dst2, $dst3, $dst4}}, [$addr+$offset];"),
2113 let mayLoad=1, neverHasSideEffects=1 in {
2114 defm LDV_i8 : LD_VEC<Int16Regs>;
2115 defm LDV_i16 : LD_VEC<Int16Regs>;
2116 defm LDV_i32 : LD_VEC<Int32Regs>;
2117 defm LDV_i64 : LD_VEC<Int64Regs>;
2118 defm LDV_f32 : LD_VEC<Float32Regs>;
2119 defm LDV_f64 : LD_VEC<Float64Regs>;
2122 multiclass ST_VEC<NVPTXRegClass regclass> {
2123 def _v2_avar : NVPTXInst<(outs),
2124 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2125 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, imem:$addr),
2126 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2127 "$fromWidth \t[$addr], {{$src1, $src2}};"), []>;
2128 def _v2_areg : NVPTXInst<(outs),
2129 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2130 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int32Regs:$addr),
2131 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2132 "$fromWidth \t[$addr], {{$src1, $src2}};"), []>;
2133 def _v2_areg_64 : NVPTXInst<(outs),
2134 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2135 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int64Regs:$addr),
2136 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2137 "$fromWidth \t[$addr], {{$src1, $src2}};"), []>;
2138 def _v2_ari : NVPTXInst<(outs),
2139 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2140 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int32Regs:$addr,
2142 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2143 "$fromWidth \t[$addr+$offset], {{$src1, $src2}};"), []>;
2144 def _v2_ari_64 : NVPTXInst<(outs),
2145 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2146 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, Int64Regs:$addr,
2148 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2149 "$fromWidth \t[$addr+$offset], {{$src1, $src2}};"), []>;
2150 def _v2_asi : NVPTXInst<(outs),
2151 (ins regclass:$src1, regclass:$src2, LdStCode:$isVol, LdStCode:$addsp,
2152 LdStCode:$Vec, LdStCode:$Sign, i32imm:$fromWidth, imem:$addr,
2154 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2155 "$fromWidth \t[$addr+$offset], {{$src1, $src2}};"), []>;
2156 def _v4_avar : NVPTXInst<(outs),
2157 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2158 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2159 i32imm:$fromWidth, imem:$addr),
2160 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2161 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>;
2162 def _v4_areg : NVPTXInst<(outs),
2163 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2164 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2165 i32imm:$fromWidth, Int32Regs:$addr),
2166 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2167 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>;
2168 def _v4_areg_64 : NVPTXInst<(outs),
2169 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2170 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2171 i32imm:$fromWidth, Int64Regs:$addr),
2172 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2173 "$fromWidth \t[$addr], {{$src1, $src2, $src3, $src4}};"), []>;
2174 def _v4_ari : NVPTXInst<(outs),
2175 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2176 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2177 i32imm:$fromWidth, Int32Regs:$addr, i32imm:$offset),
2178 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2179 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
2181 def _v4_ari_64 : NVPTXInst<(outs),
2182 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2183 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2184 i32imm:$fromWidth, Int64Regs:$addr, i32imm:$offset),
2185 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2186 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
2188 def _v4_asi : NVPTXInst<(outs),
2189 (ins regclass:$src1, regclass:$src2, regclass:$src3, regclass:$src4,
2190 LdStCode:$isVol, LdStCode:$addsp, LdStCode:$Vec, LdStCode:$Sign,
2191 i32imm:$fromWidth, imem:$addr, i32imm:$offset),
2192 !strconcat("st${isVol:volatile}${addsp:addsp}${Vec:vec}.${Sign:sign}",
2193 "$fromWidth \t[$addr+$offset], {{$src1, $src2, $src3, $src4}};"),
2196 let mayStore=1, neverHasSideEffects=1 in {
2197 defm STV_i8 : ST_VEC<Int16Regs>;
2198 defm STV_i16 : ST_VEC<Int16Regs>;
2199 defm STV_i32 : ST_VEC<Int32Regs>;
2200 defm STV_i64 : ST_VEC<Int64Regs>;
2201 defm STV_f32 : ST_VEC<Float32Regs>;
2202 defm STV_f64 : ST_VEC<Float64Regs>;
2206 //---- Conversion ----
2208 // NOTE: pred->fp are currently sub-optimal due to an issue in TableGen where
2209 // we cannot specify floating-point literals in isel patterns. Therefore, we
2210 // use an integer selp to select either 1 or 0 and then cvt to floating-point.
2213 def : Pat<(f32 (sint_to_fp Int1Regs:$a)),
2214 (CVT_f32_s32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2215 def : Pat<(f32 (sint_to_fp Int16Regs:$a)),
2216 (CVT_f32_s16 Int16Regs:$a, CvtRN)>;
2217 def : Pat<(f32 (sint_to_fp Int32Regs:$a)),
2218 (CVT_f32_s32 Int32Regs:$a, CvtRN)>;
2219 def : Pat<(f32 (sint_to_fp Int64Regs:$a)),
2220 (CVT_f32_s64 Int64Regs:$a, CvtRN)>;
2223 def : Pat<(f32 (uint_to_fp Int1Regs:$a)),
2224 (CVT_f32_u32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2225 def : Pat<(f32 (uint_to_fp Int16Regs:$a)),
2226 (CVT_f32_u16 Int16Regs:$a, CvtRN)>;
2227 def : Pat<(f32 (uint_to_fp Int32Regs:$a)),
2228 (CVT_f32_u32 Int32Regs:$a, CvtRN)>;
2229 def : Pat<(f32 (uint_to_fp Int64Regs:$a)),
2230 (CVT_f32_u64 Int64Regs:$a, CvtRN)>;
2233 def : Pat<(f64 (sint_to_fp Int1Regs:$a)),
2234 (CVT_f64_s32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2235 def : Pat<(f64 (sint_to_fp Int16Regs:$a)),
2236 (CVT_f64_s16 Int16Regs:$a, CvtRN)>;
2237 def : Pat<(f64 (sint_to_fp Int32Regs:$a)),
2238 (CVT_f64_s32 Int32Regs:$a, CvtRN)>;
2239 def : Pat<(f64 (sint_to_fp Int64Regs:$a)),
2240 (CVT_f64_s64 Int64Regs:$a, CvtRN)>;
2243 def : Pat<(f64 (uint_to_fp Int1Regs:$a)),
2244 (CVT_f64_u32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;
2245 def : Pat<(f64 (uint_to_fp Int16Regs:$a)),
2246 (CVT_f64_u16 Int16Regs:$a, CvtRN)>;
2247 def : Pat<(f64 (uint_to_fp Int32Regs:$a)),
2248 (CVT_f64_u32 Int32Regs:$a, CvtRN)>;
2249 def : Pat<(f64 (uint_to_fp Int64Regs:$a)),
2250 (CVT_f64_u64 Int64Regs:$a, CvtRN)>;
2254 def : Pat<(i16 (fp_to_sint Float32Regs:$a)),
2255 (CVT_s16_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2256 def : Pat<(i16 (fp_to_sint Float32Regs:$a)),
2257 (CVT_s16_f32 Float32Regs:$a, CvtRZI)>;
2258 def : Pat<(i32 (fp_to_sint Float32Regs:$a)),
2259 (CVT_s32_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2260 def : Pat<(i32 (fp_to_sint Float32Regs:$a)),
2261 (CVT_s32_f32 Float32Regs:$a, CvtRZI)>;
2262 def : Pat<(i64 (fp_to_sint Float32Regs:$a)),
2263 (CVT_s64_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2264 def : Pat<(i64 (fp_to_sint Float32Regs:$a)),
2265 (CVT_s64_f32 Float32Regs:$a, CvtRZI)>;
2268 def : Pat<(i16 (fp_to_uint Float32Regs:$a)),
2269 (CVT_u16_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2270 def : Pat<(i16 (fp_to_uint Float32Regs:$a)),
2271 (CVT_u16_f32 Float32Regs:$a, CvtRZI)>;
2272 def : Pat<(i32 (fp_to_uint Float32Regs:$a)),
2273 (CVT_u32_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2274 def : Pat<(i32 (fp_to_uint Float32Regs:$a)),
2275 (CVT_u32_f32 Float32Regs:$a, CvtRZI)>;
2276 def : Pat<(i64 (fp_to_uint Float32Regs:$a)),
2277 (CVT_u64_f32 Float32Regs:$a, CvtRZI_FTZ)>, Requires<[doF32FTZ]>;
2278 def : Pat<(i64 (fp_to_uint Float32Regs:$a)),
2279 (CVT_u64_f32 Float32Regs:$a, CvtRZI)>;
2282 def : Pat<(i16 (fp_to_sint Float64Regs:$a)),
2283 (CVT_s16_f64 Float64Regs:$a, CvtRZI)>;
2284 def : Pat<(i32 (fp_to_sint Float64Regs:$a)),
2285 (CVT_s32_f64 Float64Regs:$a, CvtRZI)>;
2286 def : Pat<(i64 (fp_to_sint Float64Regs:$a)),
2287 (CVT_s64_f64 Float64Regs:$a, CvtRZI)>;
2290 def : Pat<(i16 (fp_to_uint Float64Regs:$a)),
2291 (CVT_u16_f64 Float64Regs:$a, CvtRZI)>;
2292 def : Pat<(i32 (fp_to_uint Float64Regs:$a)),
2293 (CVT_u32_f64 Float64Regs:$a, CvtRZI)>;
2294 def : Pat<(i64 (fp_to_uint Float64Regs:$a)),
2295 (CVT_u64_f64 Float64Regs:$a, CvtRZI)>;
2298 def : Pat<(i16 (sext Int1Regs:$a)),
2299 (SELP_s16ii -1, 0, Int1Regs:$a)>;
2300 def : Pat<(i32 (sext Int1Regs:$a)),
2301 (SELP_s32ii -1, 0, Int1Regs:$a)>;
2302 def : Pat<(i64 (sext Int1Regs:$a)),
2303 (SELP_s64ii -1, 0, Int1Regs:$a)>;
2306 def : Pat<(i16 (zext Int1Regs:$a)),
2307 (SELP_u16ii 1, 0, Int1Regs:$a)>;
2308 def : Pat<(i32 (zext Int1Regs:$a)),
2309 (SELP_u32ii 1, 0, Int1Regs:$a)>;
2310 def : Pat<(i64 (zext Int1Regs:$a)),
2311 (SELP_u64ii 1, 0, Int1Regs:$a)>;
2314 def : Pat<(i16 (anyext Int1Regs:$a)),
2315 (SELP_u16ii -1, 0, Int1Regs:$a)>;
2316 def : Pat<(i32 (anyext Int1Regs:$a)),
2317 (SELP_u32ii -1, 0, Int1Regs:$a)>;
2318 def : Pat<(i64 (anyext Int1Regs:$a)),
2319 (SELP_u64ii -1, 0, Int1Regs:$a)>;
2322 def : Pat<(i32 (sext Int16Regs:$a)),
2323 (CVT_s32_s16 Int16Regs:$a, CvtNONE)>;
2324 def : Pat<(i64 (sext Int16Regs:$a)),
2325 (CVT_s64_s16 Int16Regs:$a, CvtNONE)>;
2328 def : Pat<(i32 (zext Int16Regs:$a)),
2329 (CVT_u32_u16 Int16Regs:$a, CvtNONE)>;
2330 def : Pat<(i64 (zext Int16Regs:$a)),
2331 (CVT_u64_u16 Int16Regs:$a, CvtNONE)>;
2334 def : Pat<(i32 (anyext Int16Regs:$a)),
2335 (CVT_u32_u16 Int16Regs:$a, CvtNONE)>;
2336 def : Pat<(i64 (anyext Int16Regs:$a)),
2337 (CVT_u64_u16 Int16Regs:$a, CvtNONE)>;
2340 def : Pat<(i64 (sext Int32Regs:$a)),
2341 (CVT_s64_s32 Int32Regs:$a, CvtNONE)>;
2344 def : Pat<(i64 (zext Int32Regs:$a)),
2345 (CVT_u64_u32 Int32Regs:$a, CvtNONE)>;
2348 def : Pat<(i64 (anyext Int32Regs:$a)),
2349 (CVT_u64_u32 Int32Regs:$a, CvtNONE)>;
2353 def : Pat<(i32 (trunc Int64Regs:$a)),
2354 (CVT_u32_u64 Int64Regs:$a, CvtNONE)>;
2355 def : Pat<(i16 (trunc Int64Regs:$a)),
2356 (CVT_u16_u64 Int64Regs:$a, CvtNONE)>;
2357 def : Pat<(i1 (trunc Int64Regs:$a)),
2358 (SETP_b64ri (ANDb64ri Int64Regs:$a, 1), 1, CmpEQ)>;
2361 def : Pat<(i16 (trunc Int32Regs:$a)),
2362 (CVT_u16_u32 Int32Regs:$a, CvtNONE)>;
2363 def : Pat<(i1 (trunc Int32Regs:$a)),
2364 (SETP_b32ri (ANDb32ri Int32Regs:$a, 1), 1, CmpEQ)>;
2367 def : Pat<(i1 (trunc Int16Regs:$a)),
2368 (SETP_b16ri (ANDb16ri Int16Regs:$a, 1), 1, CmpEQ)>;
2371 def : Pat<(sext_inreg Int16Regs:$a, i8), (CVT_INREG_s16_s8 Int16Regs:$a)>;
2372 def : Pat<(sext_inreg Int32Regs:$a, i8), (CVT_INREG_s32_s8 Int32Regs:$a)>;
2373 def : Pat<(sext_inreg Int32Regs:$a, i16), (CVT_INREG_s32_s16 Int32Regs:$a)>;
2374 def : Pat<(sext_inreg Int64Regs:$a, i8), (CVT_INREG_s64_s8 Int64Regs:$a)>;
2375 def : Pat<(sext_inreg Int64Regs:$a, i16), (CVT_INREG_s64_s16 Int64Regs:$a)>;
2376 def : Pat<(sext_inreg Int64Regs:$a, i32), (CVT_INREG_s64_s32 Int64Regs:$a)>;
2379 // Select instructions with 32-bit predicates
2380 def : Pat<(select Int32Regs:$pred, Int16Regs:$a, Int16Regs:$b),
2381 (SELP_b16rr Int16Regs:$a, Int16Regs:$b,
2382 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2383 def : Pat<(select Int32Regs:$pred, Int32Regs:$a, Int32Regs:$b),
2384 (SELP_b32rr Int32Regs:$a, Int32Regs:$b,
2385 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2386 def : Pat<(select Int32Regs:$pred, Int64Regs:$a, Int64Regs:$b),
2387 (SELP_b64rr Int64Regs:$a, Int64Regs:$b,
2388 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2389 def : Pat<(select Int32Regs:$pred, Float32Regs:$a, Float32Regs:$b),
2390 (SELP_f32rr Float32Regs:$a, Float32Regs:$b,
2391 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2392 def : Pat<(select Int32Regs:$pred, Float64Regs:$a, Float64Regs:$b),
2393 (SELP_f64rr Float64Regs:$a, Float64Regs:$b,
2394 (SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
2397 class F_BITCONVERT<string SzStr, NVPTXRegClass regclassIn,
2398 NVPTXRegClass regclassOut> :
2399 NVPTXInst<(outs regclassOut:$d), (ins regclassIn:$a),
2400 !strconcat("mov.b", !strconcat(SzStr, " \t $d, $a;")),
2401 [(set regclassOut:$d, (bitconvert regclassIn:$a))]>;
2403 def BITCONVERT_32_I2F : F_BITCONVERT<"32", Int32Regs, Float32Regs>;
2404 def BITCONVERT_32_F2I : F_BITCONVERT<"32", Float32Regs, Int32Regs>;
2405 def BITCONVERT_64_I2F : F_BITCONVERT<"64", Int64Regs, Float64Regs>;
2406 def BITCONVERT_64_F2I : F_BITCONVERT<"64", Float64Regs, Int64Regs>;
2408 // pack a set of smaller int registers to a larger int register
2409 def V4I16toI64 : NVPTXInst<(outs Int64Regs:$d),
2410 (ins Int16Regs:$s1, Int16Regs:$s2,
2411 Int16Regs:$s3, Int16Regs:$s4),
2412 "mov.b64\t$d, {{$s1, $s2, $s3, $s4}};",
2414 def V2I16toI32 : NVPTXInst<(outs Int32Regs:$d),
2415 (ins Int16Regs:$s1, Int16Regs:$s2),
2416 "mov.b32\t$d, {{$s1, $s2}};",
2418 def V2I32toI64 : NVPTXInst<(outs Int64Regs:$d),
2419 (ins Int32Regs:$s1, Int32Regs:$s2),
2420 "mov.b64\t$d, {{$s1, $s2}};",
2422 def V2F32toF64 : NVPTXInst<(outs Float64Regs:$d),
2423 (ins Float32Regs:$s1, Float32Regs:$s2),
2424 "mov.b64\t$d, {{$s1, $s2}};",
2427 // unpack a larger int register to a set of smaller int registers
2428 def I64toV4I16 : NVPTXInst<(outs Int16Regs:$d1, Int16Regs:$d2,
2429 Int16Regs:$d3, Int16Regs:$d4),
2431 "mov.b64\t{{$d1, $d2, $d3, $d4}}, $s;",
2433 def I32toV2I16 : NVPTXInst<(outs Int16Regs:$d1, Int16Regs:$d2),
2435 "mov.b32\t{{$d1, $d2}}, $s;",
2437 def I64toV2I32 : NVPTXInst<(outs Int32Regs:$d1, Int32Regs:$d2),
2439 "mov.b64\t{{$d1, $d2}}, $s;",
2441 def F64toV2F32 : NVPTXInst<(outs Float32Regs:$d1, Float32Regs:$d2),
2442 (ins Float64Regs:$s),
2443 "mov.b64\t{{$d1, $d2}}, $s;",
2446 // Count leading zeros
2447 def CLZr32 : NVPTXInst<(outs Int32Regs:$d), (ins Int32Regs:$a),
2450 def CLZr64 : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2454 // 32-bit has a direct PTX instruction
2455 def : Pat<(ctlz Int32Regs:$a),
2456 (CLZr32 Int32Regs:$a)>;
2457 def : Pat<(ctlz_zero_undef Int32Regs:$a),
2458 (CLZr32 Int32Regs:$a)>;
2460 // For 64-bit, the result in PTX is actually 32-bit so we zero-extend
2461 // to 64-bit to match the LLVM semantics
2462 def : Pat<(ctlz Int64Regs:$a),
2463 (CVT_u64_u32 (CLZr64 Int64Regs:$a), CvtNONE)>;
2464 def : Pat<(ctlz_zero_undef Int64Regs:$a),
2465 (CVT_u64_u32 (CLZr64 Int64Regs:$a), CvtNONE)>;
2467 // For 16-bit, we zero-extend to 32-bit, then trunc the result back
2468 // to 16-bits (ctlz of a 16-bit value is guaranteed to require less
2469 // than 16 bits to store). We also need to subtract 16 because the
2470 // high-order 16 zeros were counted.
2471 def : Pat<(ctlz Int16Regs:$a),
2472 (SUBi16ri (CVT_u16_u32 (CLZr32
2473 (CVT_u32_u16 Int16Regs:$a, CvtNONE)),
2475 def : Pat<(ctlz_zero_undef Int16Regs:$a),
2476 (SUBi16ri (CVT_u16_u32 (CLZr32
2477 (CVT_u32_u16 Int16Regs:$a, CvtNONE)),
2481 def POPCr32 : NVPTXInst<(outs Int32Regs:$d), (ins Int32Regs:$a),
2482 "popc.b32\t$d, $a;",
2484 def POPCr64 : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2485 "popc.b64\t$d, $a;",
2488 // 32-bit has a direct PTX instruction
2489 def : Pat<(ctpop Int32Regs:$a),
2490 (POPCr32 Int32Regs:$a)>;
2492 // For 64-bit, the result in PTX is actually 32-bit so we zero-extend
2493 // to 64-bit to match the LLVM semantics
2494 def : Pat<(ctpop Int64Regs:$a),
2495 (CVT_u64_u32 (POPCr64 Int64Regs:$a), CvtNONE)>;
2497 // For 16-bit, we zero-extend to 32-bit, then trunc the result back
2498 // to 16-bits (ctpop of a 16-bit value is guaranteed to require less
2499 // than 16 bits to store)
2500 def : Pat<(ctpop Int16Regs:$a),
2501 (CVT_u16_u32 (POPCr32 (CVT_u32_u16 Int16Regs:$a, CvtNONE)),
2504 // fround f64 -> f32
2505 def : Pat<(f32 (fround Float64Regs:$a)),
2506 (CVT_f32_f64 Float64Regs:$a, CvtRN_FTZ)>, Requires<[doF32FTZ]>;
2507 def : Pat<(f32 (fround Float64Regs:$a)),
2508 (CVT_f32_f64 Float64Regs:$a, CvtRN)>;
2510 // fextend f32 -> f64
2511 def : Pat<(f64 (fextend Float32Regs:$a)),
2512 (CVT_f64_f32 Float32Regs:$a, CvtNONE_FTZ)>, Requires<[doF32FTZ]>;
2513 def : Pat<(f64 (fextend Float32Regs:$a)),
2514 (CVT_f64_f32 Float32Regs:$a, CvtNONE)>;
2516 def retflag : SDNode<"NVPTXISD::RET_FLAG", SDTNone,
2517 [SDNPHasChain, SDNPOptInGlue]>;
2519 //-----------------------------------
2521 //-----------------------------------
2523 let isTerminator=1 in {
2524 let isReturn=1, isBarrier=1 in
2525 def Return : NVPTXInst<(outs), (ins), "ret;", [(retflag)]>;
2528 def CBranch : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
2529 "@$a bra \t$target;",
2530 [(brcond Int1Regs:$a, bb:$target)]>;
2532 def CBranchOther : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
2533 "@!$a bra \t$target;",
2536 let isBranch=1, isBarrier=1 in
2537 def GOTO : NVPTXInst<(outs), (ins brtarget:$target),
2538 "bra.uni \t$target;",
2542 def : Pat<(brcond Int32Regs:$a, bb:$target),
2543 (CBranch (SETP_u32ri Int32Regs:$a, 0, CmpNE), bb:$target)>;
2545 // SelectionDAGBuilder::visitSWitchCase() will invert the condition of a
2546 // conditional branch if
2547 // the target block is the next block so that the code can fall through to the
2549 // The invertion is done by 'xor condition, 1', which will be translated to
2550 // (setne condition, -1).
2551 // Since ptx supports '@!pred bra target', we should use it.
2552 def : Pat<(brcond (i1 (setne Int1Regs:$a, -1)), bb:$target),
2553 (CBranchOther Int1Regs:$a, bb:$target)>;
2556 def SDT_NVPTXCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
2557 def SDT_NVPTXCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
2558 SDTCisVT<1, i32> ]>;
2560 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_NVPTXCallSeqStart,
2561 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
2562 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_NVPTXCallSeqEnd,
2563 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
2566 def SDT_NVPTXCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
2567 def call : SDNode<"NVPTXISD::CALL", SDT_NVPTXCall,
2568 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
2569 def calltarget : Operand<i32>;
2571 def CALL : NVPTXInst<(outs), (ins calltarget:$dst),
2572 "call \t$dst, (1);", []>;
2575 def : Pat<(call tglobaladdr:$dst),
2576 (CALL tglobaladdr:$dst)>;
2577 def : Pat<(call texternalsym:$dst),
2578 (CALL texternalsym:$dst)>;
2580 // Pseudo instructions.
2581 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
2582 : NVPTXInst<outs, ins, asmstr, pattern>;
2584 // @TODO: We use some tricks here to emit curly braces. Can we clean this up
2585 // a bit without TableGen modifications?
2586 def Callseq_Start : NVPTXInst<(outs), (ins i32imm:$amt),
2587 "// Callseq Start $amt\n\t{{\n\t.reg .b32 temp_param_reg;\n\t// <end>}}",
2588 [(callseq_start timm:$amt)]>;
2589 def Callseq_End : NVPTXInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
2590 "\n\t//{{\n\t}}// Callseq End $amt1",
2591 [(callseq_end timm:$amt1, timm:$amt2)]>;
2595 def trapinst : NVPTXInst<(outs), (ins),
2599 include "NVPTXIntrinsics.td"
2602 //-----------------------------------
2604 //-----------------------------------
2605 // BSWAP is currently expanded. The following is a more efficient
2606 // - for < sm_20, use vector scalar mov, as tesla support native 16-bit register
2607 // - for sm_20, use pmpt (use vector scalar mov to get the pack and
2608 // unpack). sm_20 supports native 32-bit register, but not native 16-bit