lib/Target/NVPTX/NVPTXIntrinsics.td

   1 //===- NVPTXIntrinsics.td - PTX Intrinsics Instructions -------*- tblgen -*-==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 def immFloat0 : PatLeaf<(fpimm), [{
  11     float f = (float)N->getValueAPF().convertToFloat();
  12     return (f==0.0f);
  13 }]>;
  14
  15 def immFloat1 : PatLeaf<(fpimm), [{
  16     float f = (float)N->getValueAPF().convertToFloat();
  17     return (f==1.0f);
  18 }]>;
  19
  20 def immDouble0 : PatLeaf<(fpimm), [{
  21     double d = (double)N->getValueAPF().convertToDouble();
  22     return (d==0.0);
  23 }]>;
  24
  25 def immDouble1 : PatLeaf<(fpimm), [{
  26     double d = (double)N->getValueAPF().convertToDouble();
  27     return (d==1.0);
  28 }]>;
  29
  30
  31
  32 //-----------------------------------
  33 // Synchronization Functions
  34 //-----------------------------------
  35 def INT_CUDA_SYNCTHREADS : NVPTXInst<(outs), (ins),
  36                   "bar.sync \t0;",
  37       [(int_cuda_syncthreads)]>;
  38 def INT_BARRIER0 : NVPTXInst<(outs), (ins),
  39                   "bar.sync \t0;",
  40       [(int_nvvm_barrier0)]>;
  41 def INT_BARRIER0_POPC : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$pred),
  42   !strconcat("{{ \n\t",
  43       !strconcat(".reg .pred \t%p1; \n\t",
  44       !strconcat("setp.ne.u32 \t%p1, $pred, 0; \n\t",
  45       !strconcat("bar.red.popc.u32 \t$dst, 0, %p1; \n\t",
  46         !strconcat("}}", ""))))),
  47       [(set Int32Regs:$dst, (int_nvvm_barrier0_popc Int32Regs:$pred))]>;
  48 def INT_BARRIER0_AND : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$pred),
  49   !strconcat("{{ \n\t",
  50       !strconcat(".reg .pred \t%p1; \n\t",
  51       !strconcat(".reg .pred \t%p2; \n\t",
  52       !strconcat("setp.ne.u32 \t%p1, $pred, 0; \n\t",
  53       !strconcat("bar.red.and.pred \t%p2, 0, %p1; \n\t",
  54       !strconcat("selp.u32 \t$dst, 1, 0, %p2; \n\t",
  55         !strconcat("}}", ""))))))),
  56       [(set Int32Regs:$dst, (int_nvvm_barrier0_and Int32Regs:$pred))]>;
  57 def INT_BARRIER0_OR : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$pred),
  58   !strconcat("{{ \n\t",
  59       !strconcat(".reg .pred \t%p1; \n\t",
  60       !strconcat(".reg .pred \t%p2; \n\t",
  61       !strconcat("setp.ne.u32 \t%p1, $pred, 0; \n\t",
  62       !strconcat("bar.red.or.pred \t%p2, 0, %p1; \n\t",
  63       !strconcat("selp.u32 \t$dst, 1, 0, %p2; \n\t",
  64         !strconcat("}}", ""))))))),
  65       [(set Int32Regs:$dst, (int_nvvm_barrier0_or Int32Regs:$pred))]>;
  66
  67
  68 //-----------------------------------
  69 // Explicit Memory Fence Functions
  70 //-----------------------------------
  71 class MEMBAR<string StrOp, Intrinsic IntOP> :
  72               NVPTXInst<(outs), (ins),
  73             StrOp, [(IntOP)]>;
  74
  75 def INT_MEMBAR_CTA : MEMBAR<"membar.cta;", int_nvvm_membar_cta>;
  76 def INT_MEMBAR_GL  : MEMBAR<"membar.gl;",  int_nvvm_membar_gl>;
  77 def INT_MEMBAR_SYS : MEMBAR<"membar.sys;", int_nvvm_membar_sys>;
  78
  79
  80 //-----------------------------------
  81 // Math Functions
  82 //-----------------------------------
  83
  84 // Map min(1.0, max(0.0, x)) to sat(x)
  85 // Note that max(0.0, min(x, 1.0)) cannot be mapped to sat(x) because when x is
  86 // NaN
  87 // max(0.0, min(x, 1.0)) is 1.0 while sat(x) is 0.
  88 // Same story for fmax, fmin.
  89
  90 def : Pat<(int_nvvm_fmin_f immFloat1,
  91             (int_nvvm_fmax_f immFloat0, Float32Regs:$a)),
  92           (CVT_f32_f32 Float32Regs:$a, CvtSAT)>;
  93 def : Pat<(int_nvvm_fmin_f immFloat1,
  94             (int_nvvm_fmax_f Float32Regs:$a, immFloat0)),
  95           (CVT_f32_f32 Float32Regs:$a, CvtSAT)>;
  96 def : Pat<(int_nvvm_fmin_f
  97             (int_nvvm_fmax_f immFloat0, Float32Regs:$a), immFloat1),
  98           (CVT_f32_f32 Float32Regs:$a, CvtSAT)>;
  99 def : Pat<(int_nvvm_fmin_f
 100             (int_nvvm_fmax_f Float32Regs:$a, immFloat0), immFloat1),
 101           (CVT_f32_f32 Float32Regs:$a, CvtSAT)>;
 102
 103 def : Pat<(int_nvvm_fmin_d immDouble1,
 104             (int_nvvm_fmax_d immDouble0, Float64Regs:$a)),
 105           (CVT_f64_f64 Float64Regs:$a, CvtSAT)>;
 106 def : Pat<(int_nvvm_fmin_d immDouble1,
 107             (int_nvvm_fmax_d Float64Regs:$a, immDouble0)),
 108           (CVT_f64_f64 Float64Regs:$a, CvtSAT)>;
 109 def : Pat<(int_nvvm_fmin_d
 110             (int_nvvm_fmax_d immDouble0, Float64Regs:$a), immDouble1),
 111           (CVT_f64_f64 Float64Regs:$a, CvtSAT)>;
 112 def : Pat<(int_nvvm_fmin_d
 113             (int_nvvm_fmax_d Float64Regs:$a, immDouble0), immDouble1),
 114           (CVT_f64_f64 Float64Regs:$a, CvtSAT)>;
 115
 116
 117 // We need a full string for OpcStr here because we need to deal with case like
 118 // INT_PTX_RECIP.
 119 class F_MATH_1<string OpcStr, NVPTXRegClass target_regclass,
 120   NVPTXRegClass src_regclass, Intrinsic IntOP>
 121             : NVPTXInst<(outs target_regclass:$dst), (ins src_regclass:$src0),
 122             OpcStr,
 123         [(set target_regclass:$dst, (IntOP src_regclass:$src0))]>;
 124
 125 // We need a full string for OpcStr here because we need to deal with the case
 126 // like INT_PTX_NATIVE_POWR_F.
 127 class F_MATH_2<string OpcStr, NVPTXRegClass t_regclass,
 128   NVPTXRegClass s0_regclass, NVPTXRegClass s1_regclass, Intrinsic IntOP>
 129             : NVPTXInst<(outs t_regclass:$dst),
 130               (ins s0_regclass:$src0, s1_regclass:$src1),
 131             OpcStr,
 132         [(set t_regclass:$dst, (IntOP s0_regclass:$src0, s1_regclass:$src1))]>;
 133
 134 class F_MATH_3<string OpcStr, NVPTXRegClass t_regclass,
 135   NVPTXRegClass s0_regclass, NVPTXRegClass s1_regclass,
 136   NVPTXRegClass s2_regclass, Intrinsic IntOP>
 137             : NVPTXInst<(outs t_regclass:$dst),
 138               (ins s0_regclass:$src0, s1_regclass:$src1, s2_regclass:$src2),
 139             OpcStr,
 140         [(set t_regclass:$dst,
 141           (IntOP s0_regclass:$src0, s1_regclass:$src1, s2_regclass:$src2))]>;
 142
 143 //
 144 // MISC
 145 //
 146
 147 def INT_NVVM_CLZ_I : F_MATH_1<"clz.b32 \t$dst, $src0;", Int32Regs, Int32Regs,
 148   int_nvvm_clz_i>;
 149 def INT_NVVM_CLZ_LL : F_MATH_1<"clz.b64 \t$dst, $src0;", Int32Regs, Int64Regs,
 150   int_nvvm_clz_ll>;
 151
 152 def INT_NVVM_POPC_I : F_MATH_1<"popc.b32 \t$dst, $src0;", Int32Regs, Int32Regs,
 153   int_nvvm_popc_i>;
 154 def INT_NVVM_POPC_LL : F_MATH_1<"popc.b64 \t$dst, $src0;", Int32Regs, Int64Regs,
 155   int_nvvm_popc_ll>;
 156
 157 def INT_NVVM_PRMT : F_MATH_3<"prmt.b32 \t$dst, $src0, $src1, $src2;", Int32Regs,
 158   Int32Regs, Int32Regs, Int32Regs, int_nvvm_prmt>;
 159
 160 //
 161 // Min Max
 162 //
 163
 164 def INT_NVVM_MIN_I : F_MATH_2<"min.s32 \t$dst, $src0, $src1;", Int32Regs,
 165   Int32Regs, Int32Regs, int_nvvm_min_i>;
 166 def INT_NVVM_MIN_UI : F_MATH_2<"min.u32 \t$dst, $src0, $src1;", Int32Regs,
 167   Int32Regs, Int32Regs, int_nvvm_min_ui>;
 168
 169 def INT_NVVM_MIN_LL : F_MATH_2<"min.s64 \t$dst, $src0, $src1;", Int64Regs,
 170   Int64Regs, Int64Regs, int_nvvm_min_ll>;
 171 def INT_NVVM_MIN_ULL : F_MATH_2<"min.u64 \t$dst, $src0, $src1;", Int64Regs,
 172   Int64Regs, Int64Regs, int_nvvm_min_ull>;
 173
 174 def INT_NVVM_MAX_I : F_MATH_2<"max.s32 \t$dst, $src0, $src1;", Int32Regs,
 175   Int32Regs, Int32Regs, int_nvvm_max_i>;
 176 def INT_NVVM_MAX_UI : F_MATH_2<"max.u32 \t$dst, $src0, $src1;", Int32Regs,
 177   Int32Regs, Int32Regs, int_nvvm_max_ui>;
 178
 179 def INT_NVVM_MAX_LL : F_MATH_2<"max.s64 \t$dst, $src0, $src1;", Int64Regs,
 180   Int64Regs, Int64Regs, int_nvvm_max_ll>;
 181 def INT_NVVM_MAX_ULL : F_MATH_2<"max.u64 \t$dst, $src0, $src1;", Int64Regs,
 182   Int64Regs, Int64Regs, int_nvvm_max_ull>;
 183
 184 def INT_NVVM_FMIN_F : F_MATH_2<"min.f32 \t$dst, $src0, $src1;", Float32Regs,
 185   Float32Regs, Float32Regs, int_nvvm_fmin_f>;
 186 def INT_NVVM_FMIN_FTZ_F : F_MATH_2<"min.ftz.f32 \t$dst, $src0, $src1;",
 187   Float32Regs, Float32Regs, Float32Regs, int_nvvm_fmin_ftz_f>;
 188
 189 def INT_NVVM_FMAX_F : F_MATH_2<"max.f32 \t$dst, $src0, $src1;", Float32Regs,
 190   Float32Regs, Float32Regs, int_nvvm_fmax_f>;
 191 def INT_NVVM_FMAX_FTZ_F : F_MATH_2<"max.ftz.f32 \t$dst, $src0, $src1;",
 192   Float32Regs, Float32Regs, Float32Regs, int_nvvm_fmax_ftz_f>;
 193
 194 def INT_NVVM_FMIN_D : F_MATH_2<"min.f64 \t$dst, $src0, $src1;", Float64Regs,
 195   Float64Regs, Float64Regs, int_nvvm_fmin_d>;
 196 def INT_NVVM_FMAX_D : F_MATH_2<"max.f64 \t$dst, $src0, $src1;", Float64Regs,
 197   Float64Regs, Float64Regs, int_nvvm_fmax_d>;
 198
 199 //
 200 // Multiplication
 201 //
 202
 203 def INT_NVVM_MULHI_I : F_MATH_2<"mul.hi.s32 \t$dst, $src0, $src1;", Int32Regs,
 204   Int32Regs, Int32Regs, int_nvvm_mulhi_i>;
 205 def INT_NVVM_MULHI_UI : F_MATH_2<"mul.hi.u32 \t$dst, $src0, $src1;", Int32Regs,
 206   Int32Regs, Int32Regs, int_nvvm_mulhi_ui>;
 207
 208 def INT_NVVM_MULHI_LL : F_MATH_2<"mul.hi.s64 \t$dst, $src0, $src1;", Int64Regs,
 209   Int64Regs, Int64Regs, int_nvvm_mulhi_ll>;
 210 def INT_NVVM_MULHI_ULL : F_MATH_2<"mul.hi.u64 \t$dst, $src0, $src1;", Int64Regs,
 211   Int64Regs, Int64Regs, int_nvvm_mulhi_ull>;
 212
 213 def INT_NVVM_MUL_RN_FTZ_F : F_MATH_2<"mul.rn.ftz.f32 \t$dst, $src0, $src1;",
 214   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rn_ftz_f>;
 215 def INT_NVVM_MUL_RN_F : F_MATH_2<"mul.rn.f32 \t$dst, $src0, $src1;",
 216   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rn_f>;
 217 def INT_NVVM_MUL_RZ_FTZ_F : F_MATH_2<"mul.rz.ftz.f32 \t$dst, $src0, $src1;",
 218   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rz_ftz_f>;
 219 def INT_NVVM_MUL_RZ_F : F_MATH_2<"mul.rz.f32 \t$dst, $src0, $src1;",
 220   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rz_f>;
 221 def INT_NVVM_MUL_RM_FTZ_F : F_MATH_2<"mul.rm.ftz.f32 \t$dst, $src0, $src1;",
 222   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rm_ftz_f>;
 223 def INT_NVVM_MUL_RM_F : F_MATH_2<"mul.rm.f32 \t$dst, $src0, $src1;",
 224   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rm_f>;
 225 def INT_NVVM_MUL_RP_FTZ_F : F_MATH_2<"mul.rp.ftz.f32 \t$dst, $src0, $src1;",
 226   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rp_ftz_f>;
 227 def INT_NVVM_MUL_RP_F : F_MATH_2<"mul.rp.f32 \t$dst, $src0, $src1;",
 228   Float32Regs, Float32Regs, Float32Regs, int_nvvm_mul_rp_f>;
 229
 230 def INT_NVVM_MUL_RN_D : F_MATH_2<"mul.rn.f64 \t$dst, $src0, $src1;",
 231   Float64Regs, Float64Regs, Float64Regs, int_nvvm_mul_rn_d>;
 232 def INT_NVVM_MUL_RZ_D : F_MATH_2<"mul.rz.f64 \t$dst, $src0, $src1;",
 233   Float64Regs, Float64Regs, Float64Regs, int_nvvm_mul_rz_d>;
 234 def INT_NVVM_MUL_RM_D : F_MATH_2<"mul.rm.f64 \t$dst, $src0, $src1;",
 235   Float64Regs, Float64Regs, Float64Regs, int_nvvm_mul_rm_d>;
 236 def INT_NVVM_MUL_RP_D : F_MATH_2<"mul.rp.f64 \t$dst, $src0, $src1;",
 237   Float64Regs, Float64Regs, Float64Regs, int_nvvm_mul_rp_d>;
 238
 239 def INT_NVVM_MUL24_I : F_MATH_2<"mul24.lo.s32 \t$dst, $src0, $src1;",
 240   Int32Regs, Int32Regs, Int32Regs, int_nvvm_mul24_i>;
 241 def INT_NVVM_MUL24_UI : F_MATH_2<"mul24.lo.u32 \t$dst, $src0, $src1;",
 242   Int32Regs, Int32Regs, Int32Regs, int_nvvm_mul24_ui>;
 243
 244 //
 245 // Div
 246 //
 247
 248 def INT_NVVM_DIV_APPROX_FTZ_F
 249   : F_MATH_2<"div.approx.ftz.f32 \t$dst, $src0, $src1;", Float32Regs,
 250     Float32Regs, Float32Regs, int_nvvm_div_approx_ftz_f>;
 251 def INT_NVVM_DIV_APPROX_F : F_MATH_2<"div.approx.f32 \t$dst, $src0, $src1;",
 252   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_approx_f>;
 253
 254 def INT_NVVM_DIV_RN_FTZ_F : F_MATH_2<"div.rn.ftz.f32 \t$dst, $src0, $src1;",
 255   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rn_ftz_f>;
 256 def INT_NVVM_DIV_RN_F     : F_MATH_2<"div.rn.f32 \t$dst, $src0, $src1;",
 257   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rn_f>;
 258 def INT_NVVM_DIV_RZ_FTZ_F : F_MATH_2<"div.rz.ftz.f32 \t$dst, $src0, $src1;",
 259   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rz_ftz_f>;
 260 def INT_NVVM_DIV_RZ_F     : F_MATH_2<"div.rz.f32 \t$dst, $src0, $src1;",
 261   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rz_f>;
 262 def INT_NVVM_DIV_RM_FTZ_F : F_MATH_2<"div.rm.ftz.f32 \t$dst, $src0, $src1;",
 263   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rm_ftz_f>;
 264 def INT_NVVM_DIV_RM_F     : F_MATH_2<"div.rm.f32 \t$dst, $src0, $src1;",
 265   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rm_f>;
 266 def INT_NVVM_DIV_RP_FTZ_F : F_MATH_2<"div.rp.ftz.f32 \t$dst, $src0, $src1;",
 267   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rp_ftz_f>;
 268 def INT_NVVM_DIV_RP_F     : F_MATH_2<"div.rp.f32 \t$dst, $src0, $src1;",
 269   Float32Regs, Float32Regs, Float32Regs, int_nvvm_div_rp_f>;
 270
 271 def INT_NVVM_DIV_RN_D : F_MATH_2<"div.rn.f64 \t$dst, $src0, $src1;",
 272   Float64Regs, Float64Regs, Float64Regs, int_nvvm_div_rn_d>;
 273 def INT_NVVM_DIV_RZ_D : F_MATH_2<"div.rz.f64 \t$dst, $src0, $src1;",
 274   Float64Regs, Float64Regs, Float64Regs, int_nvvm_div_rz_d>;
 275 def INT_NVVM_DIV_RM_D : F_MATH_2<"div.rm.f64 \t$dst, $src0, $src1;",
 276   Float64Regs, Float64Regs, Float64Regs, int_nvvm_div_rm_d>;
 277 def INT_NVVM_DIV_RP_D : F_MATH_2<"div.rp.f64 \t$dst, $src0, $src1;",
 278   Float64Regs, Float64Regs, Float64Regs, int_nvvm_div_rp_d>;
 279
 280 //
 281 // Brev
 282 //
 283
 284 def INT_NVVM_BREV32 : F_MATH_1<"brev.b32 \t$dst, $src0;", Int32Regs, Int32Regs,
 285   int_nvvm_brev32>;
 286 def INT_NVVM_BREV64 : F_MATH_1<"brev.b64 \t$dst, $src0;", Int64Regs, Int64Regs,
 287   int_nvvm_brev64>;
 288
 289 //
 290 // Sad
 291 //
 292
 293 def INT_NVVM_SAD_I : F_MATH_3<"sad.s32 \t$dst, $src0, $src1, $src2;",
 294   Int32Regs, Int32Regs, Int32Regs, Int32Regs, int_nvvm_sad_i>;
 295 def INT_NVVM_SAD_UI : F_MATH_3<"sad.u32 \t$dst, $src0, $src1, $src2;",
 296   Int32Regs, Int32Regs, Int32Regs, Int32Regs, int_nvvm_sad_ui>;
 297
 298 //
 299 // Floor  Ceil
 300 //
 301
 302 def : Pat<(int_nvvm_floor_ftz_f Float32Regs:$a),
 303           (CVT_f32_f32 Float32Regs:$a, CvtRMI_FTZ)>;
 304 def : Pat<(int_nvvm_floor_f Float32Regs:$a),
 305           (CVT_f32_f32 Float32Regs:$a, CvtRMI)>;
 306 def : Pat<(int_nvvm_floor_d Float64Regs:$a),
 307           (CVT_f64_f64 Float64Regs:$a, CvtRMI)>;
 308
 309 def : Pat<(int_nvvm_ceil_ftz_f Float32Regs:$a),
 310           (CVT_f32_f32 Float32Regs:$a, CvtRPI_FTZ)>;
 311 def : Pat<(int_nvvm_ceil_f Float32Regs:$a),
 312           (CVT_f32_f32 Float32Regs:$a, CvtRPI)>;
 313 def : Pat<(int_nvvm_ceil_d Float64Regs:$a),
 314           (CVT_f64_f64 Float64Regs:$a, CvtRPI)>;
 315
 316 //
 317 // Abs
 318 //
 319
 320 def INT_NVVM_ABS_I : F_MATH_1<"abs.s32 \t$dst, $src0;", Int32Regs, Int32Regs,
 321   int_nvvm_abs_i>;
 322 def INT_NVVM_ABS_LL : F_MATH_1<"abs.s64 \t$dst, $src0;", Int64Regs, Int64Regs,
 323   int_nvvm_abs_ll>;
 324
 325 def INT_NVVM_FABS_FTZ_F : F_MATH_1<"abs.ftz.f32 \t$dst, $src0;", Float32Regs,
 326   Float32Regs, int_nvvm_fabs_ftz_f>;
 327 def INT_NVVM_FABS_F : F_MATH_1<"abs.f32 \t$dst, $src0;", Float32Regs,
 328   Float32Regs, int_nvvm_fabs_f>;
 329
 330 def INT_NVVM_FABS_D : F_MATH_1<"abs.f64 \t$dst, $src0;", Float64Regs,
 331   Float64Regs, int_nvvm_fabs_d>;
 332
 333 //
 334 // Round
 335 //
 336
 337 def : Pat<(int_nvvm_round_ftz_f Float32Regs:$a),
 338           (CVT_f32_f32 Float32Regs:$a, CvtRNI_FTZ)>;
 339 def : Pat<(int_nvvm_round_f Float32Regs:$a),
 340           (CVT_f32_f32 Float32Regs:$a, CvtRNI)>;
 341 def : Pat<(int_nvvm_round_d Float64Regs:$a),
 342           (CVT_f64_f64 Float64Regs:$a, CvtRNI)>;
 343
 344 //
 345 // Trunc
 346 //
 347
 348 def : Pat<(int_nvvm_trunc_ftz_f Float32Regs:$a),
 349           (CVT_f32_f32 Float32Regs:$a, CvtRZI_FTZ)>;
 350 def : Pat<(int_nvvm_trunc_f Float32Regs:$a),
 351           (CVT_f32_f32 Float32Regs:$a, CvtRZI)>;
 352 def : Pat<(int_nvvm_trunc_d Float64Regs:$a),
 353           (CVT_f64_f64 Float64Regs:$a, CvtRZI)>;
 354
 355 //
 356 // Saturate
 357 //
 358
 359 def : Pat<(int_nvvm_saturate_ftz_f Float32Regs:$a),
 360           (CVT_f32_f32 Float32Regs:$a, CvtSAT_FTZ)>;
 361 def : Pat<(int_nvvm_saturate_f Float32Regs:$a),
 362           (CVT_f32_f32 Float32Regs:$a, CvtSAT)>;
 363 def : Pat<(int_nvvm_saturate_d Float64Regs:$a),
 364           (CVT_f64_f64 Float64Regs:$a, CvtSAT)>;
 365
 366 //
 367 // Exp2  Log2
 368 //
 369
 370 def INT_NVVM_EX2_APPROX_FTZ_F : F_MATH_1<"ex2.approx.ftz.f32 \t$dst, $src0;",
 371   Float32Regs, Float32Regs, int_nvvm_ex2_approx_ftz_f>;
 372 def INT_NVVM_EX2_APPROX_F : F_MATH_1<"ex2.approx.f32 \t$dst, $src0;",
 373   Float32Regs, Float32Regs, int_nvvm_ex2_approx_f>;
 374 def INT_NVVM_EX2_APPROX_D : F_MATH_1<"ex2.approx.f64 \t$dst, $src0;",
 375   Float64Regs, Float64Regs, int_nvvm_ex2_approx_d>;
 376
 377 def INT_NVVM_LG2_APPROX_FTZ_F : F_MATH_1<"lg2.approx.ftz.f32 \t$dst, $src0;",
 378   Float32Regs, Float32Regs, int_nvvm_lg2_approx_ftz_f>;
 379 def INT_NVVM_LG2_APPROX_F : F_MATH_1<"lg2.approx.f32 \t$dst, $src0;",
 380   Float32Regs, Float32Regs, int_nvvm_lg2_approx_f>;
 381 def INT_NVVM_LG2_APPROX_D : F_MATH_1<"lg2.approx.f64 \t$dst, $src0;",
 382   Float64Regs, Float64Regs, int_nvvm_lg2_approx_d>;
 383
 384 //
 385 // Sin  Cos
 386 //
 387
 388 def INT_NVVM_SIN_APPROX_FTZ_F : F_MATH_1<"sin.approx.ftz.f32 \t$dst, $src0;",
 389   Float32Regs, Float32Regs, int_nvvm_sin_approx_ftz_f>;
 390 def INT_NVVM_SIN_APPROX_F : F_MATH_1<"sin.approx.f32 \t$dst, $src0;",
 391   Float32Regs, Float32Regs, int_nvvm_sin_approx_f>;
 392
 393 def INT_NVVM_COS_APPROX_FTZ_F : F_MATH_1<"cos.approx.ftz.f32 \t$dst, $src0;",
 394   Float32Regs, Float32Regs, int_nvvm_cos_approx_ftz_f>;
 395 def INT_NVVM_COS_APPROX_F : F_MATH_1<"cos.approx.f32 \t$dst, $src0;",
 396   Float32Regs, Float32Regs, int_nvvm_cos_approx_f>;
 397
 398 //
 399 // Fma
 400 //
 401
 402 def INT_NVVM_FMA_RN_FTZ_F
 403   : F_MATH_3<"fma.rn.ftz.f32 \t$dst, $src0, $src1, $src2;", Float32Regs,
 404     Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rn_ftz_f>;
 405 def INT_NVVM_FMA_RN_F : F_MATH_3<"fma.rn.f32 \t$dst, $src0, $src1, $src2;",
 406   Float32Regs, Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rn_f>;
 407 def INT_NVVM_FMA_RZ_FTZ_F
 408   : F_MATH_3<"fma.rz.ftz.f32 \t$dst, $src0, $src1, $src2;", Float32Regs,
 409     Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rz_ftz_f>;
 410 def INT_NVVM_FMA_RZ_F : F_MATH_3<"fma.rz.f32 \t$dst, $src0, $src1, $src2;",
 411   Float32Regs, Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rz_f>;
 412 def INT_NVVM_FMA_RM_FTZ_F
 413   : F_MATH_3<"fma.rm.ftz.f32 \t$dst, $src0, $src1, $src2;", Float32Regs,
 414     Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rm_ftz_f>;
 415 def INT_NVVM_FMA_RM_F : F_MATH_3<"fma.rm.f32 \t$dst, $src0, $src1, $src2;",
 416   Float32Regs, Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rm_f>;
 417 def INT_NVVM_FMA_RP_FTZ_F
 418   : F_MATH_3<"fma.rp.ftz.f32 \t$dst, $src0, $src1, $src2;", Float32Regs,
 419     Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rp_ftz_f>;
 420 def INT_NVVM_FMA_RP_F : F_MATH_3<"fma.rp.f32 \t$dst, $src0, $src1, $src2;",
 421   Float32Regs, Float32Regs, Float32Regs, Float32Regs, int_nvvm_fma_rp_f>;
 422
 423 def INT_NVVM_FMA_RN_D : F_MATH_3<"fma.rn.f64 \t$dst, $src0, $src1, $src2;",
 424   Float64Regs, Float64Regs, Float64Regs, Float64Regs, int_nvvm_fma_rn_d>;
 425 def INT_NVVM_FMA_RZ_D : F_MATH_3<"fma.rz.f64 \t$dst, $src0, $src1, $src2;",
 426   Float64Regs, Float64Regs, Float64Regs, Float64Regs, int_nvvm_fma_rz_d>;
 427 def INT_NVVM_FMA_RM_D : F_MATH_3<"fma.rm.f64 \t$dst, $src0, $src1, $src2;",
 428   Float64Regs, Float64Regs, Float64Regs, Float64Regs, int_nvvm_fma_rm_d>;
 429 def INT_NVVM_FMA_RP_D : F_MATH_3<"fma.rp.f64 \t$dst, $src0, $src1, $src2;",
 430   Float64Regs, Float64Regs, Float64Regs, Float64Regs, int_nvvm_fma_rp_d>;
 431
 432 //
 433 // Rcp
 434 //
 435
 436 def INT_NVVM_RCP_RN_FTZ_F : F_MATH_1<"rcp.rn.ftz.f32 \t$dst, $src0;",
 437   Float32Regs, Float32Regs, int_nvvm_rcp_rn_ftz_f>;
 438 def INT_NVVM_RCP_RN_F : F_MATH_1<"rcp.rn.f32 \t$dst, $src0;",
 439   Float32Regs, Float32Regs, int_nvvm_rcp_rn_f>;
 440 def INT_NVVM_RCP_RZ_FTZ_F : F_MATH_1<"rcp.rz.ftz.f32 \t$dst, $src0;",
 441   Float32Regs, Float32Regs, int_nvvm_rcp_rz_ftz_f>;
 442 def INT_NVVM_RCP_RZ_F : F_MATH_1<"rcp.rz.f32 \t$dst, $src0;",
 443   Float32Regs, Float32Regs, int_nvvm_rcp_rz_f>;
 444 def INT_NVVM_RCP_RM_FTZ_F : F_MATH_1<"rcp.rm.ftz.f32 \t$dst, $src0;",
 445   Float32Regs, Float32Regs, int_nvvm_rcp_rm_ftz_f>;
 446 def INT_NVVM_RCP_RM_F : F_MATH_1<"rcp.rm.f32 \t$dst, $src0;",
 447   Float32Regs, Float32Regs, int_nvvm_rcp_rm_f>;
 448 def INT_NVVM_RCP_RP_FTZ_F : F_MATH_1<"rcp.rp.ftz.f32 \t$dst, $src0;",
 449   Float32Regs, Float32Regs, int_nvvm_rcp_rp_ftz_f>;
 450 def INT_NVVM_RCP_RP_F : F_MATH_1<"rcp.rp.f32 \t$dst, $src0;",
 451   Float32Regs, Float32Regs, int_nvvm_rcp_rp_f>;
 452
 453 def INT_NVVM_RCP_RN_D : F_MATH_1<"rcp.rn.f64 \t$dst, $src0;", Float64Regs,
 454   Float64Regs, int_nvvm_rcp_rn_d>;
 455 def INT_NVVM_RCP_RZ_D : F_MATH_1<"rcp.rz.f64 \t$dst, $src0;", Float64Regs,
 456   Float64Regs, int_nvvm_rcp_rz_d>;
 457 def INT_NVVM_RCP_RM_D : F_MATH_1<"rcp.rm.f64 \t$dst, $src0;", Float64Regs,
 458   Float64Regs, int_nvvm_rcp_rm_d>;
 459 def INT_NVVM_RCP_RP_D : F_MATH_1<"rcp.rp.f64 \t$dst, $src0;", Float64Regs,
 460   Float64Regs, int_nvvm_rcp_rp_d>;
 461
 462 def INT_NVVM_RCP_APPROX_FTZ_D : F_MATH_1<"rcp.approx.ftz.f64 \t$dst, $src0;",
 463   Float64Regs, Float64Regs, int_nvvm_rcp_approx_ftz_d>;
 464
 465 //
 466 // Sqrt
 467 //
 468
 469 def INT_NVVM_SQRT_RN_FTZ_F : F_MATH_1<"sqrt.rn.ftz.f32 \t$dst, $src0;",
 470   Float32Regs, Float32Regs, int_nvvm_sqrt_rn_ftz_f>;
 471 def INT_NVVM_SQRT_RN_F : F_MATH_1<"sqrt.rn.f32 \t$dst, $src0;", Float32Regs,
 472   Float32Regs, int_nvvm_sqrt_rn_f>;
 473 def INT_NVVM_SQRT_RZ_FTZ_F : F_MATH_1<"sqrt.rz.ftz.f32 \t$dst, $src0;",
 474   Float32Regs, Float32Regs, int_nvvm_sqrt_rz_ftz_f>;
 475 def INT_NVVM_SQRT_RZ_F : F_MATH_1<"sqrt.rz.f32 \t$dst, $src0;", Float32Regs,
 476   Float32Regs, int_nvvm_sqrt_rz_f>;
 477 def INT_NVVM_SQRT_RM_FTZ_F : F_MATH_1<"sqrt.rm.ftz.f32 \t$dst, $src0;",
 478   Float32Regs, Float32Regs, int_nvvm_sqrt_rm_ftz_f>;
 479 def INT_NVVM_SQRT_RM_F : F_MATH_1<"sqrt.rm.f32 \t$dst, $src0;", Float32Regs,
 480   Float32Regs, int_nvvm_sqrt_rm_f>;
 481 def INT_NVVM_SQRT_RP_FTZ_F : F_MATH_1<"sqrt.rp.ftz.f32 \t$dst, $src0;",
 482   Float32Regs, Float32Regs, int_nvvm_sqrt_rp_ftz_f>;
 483 def INT_NVVM_SQRT_RP_F : F_MATH_1<"sqrt.rp.f32 \t$dst, $src0;", Float32Regs,
 484   Float32Regs, int_nvvm_sqrt_rp_f>;
 485 def INT_NVVM_SQRT_APPROX_FTZ_F : F_MATH_1<"sqrt.approx.ftz.f32 \t$dst, $src0;",
 486   Float32Regs, Float32Regs, int_nvvm_sqrt_approx_ftz_f>;
 487 def INT_NVVM_SQRT_APPROX_F : F_MATH_1<"sqrt.approx.f32 \t$dst, $src0;",
 488   Float32Regs, Float32Regs, int_nvvm_sqrt_approx_f>;
 489
 490 def INT_NVVM_SQRT_RN_D : F_MATH_1<"sqrt.rn.f64 \t$dst, $src0;", Float64Regs,
 491   Float64Regs, int_nvvm_sqrt_rn_d>;
 492 def INT_NVVM_SQRT_RZ_D : F_MATH_1<"sqrt.rz.f64 \t$dst, $src0;", Float64Regs,
 493   Float64Regs, int_nvvm_sqrt_rz_d>;
 494 def INT_NVVM_SQRT_RM_D : F_MATH_1<"sqrt.rm.f64 \t$dst, $src0;", Float64Regs,
 495   Float64Regs, int_nvvm_sqrt_rm_d>;
 496 def INT_NVVM_SQRT_RP_D : F_MATH_1<"sqrt.rp.f64 \t$dst, $src0;", Float64Regs,
 497   Float64Regs, int_nvvm_sqrt_rp_d>;
 498
 499 // nvvm_sqrt intrinsic
 500 def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
 501           (INT_NVVM_SQRT_RN_FTZ_F Float32Regs:$a)>, Requires<[doF32FTZ, do_SQRTF32_RN]>;
 502 def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
 503           (INT_NVVM_SQRT_RN_F Float32Regs:$a)>, Requires<[do_SQRTF32_RN]>;
 504 def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
 505           (INT_NVVM_SQRT_APPROX_FTZ_F Float32Regs:$a)>, Requires<[doF32FTZ]>;
 506 def : Pat<(int_nvvm_sqrt_f Float32Regs:$a),
 507           (INT_NVVM_SQRT_APPROX_F Float32Regs:$a)>;
 508
 509 //
 510 // Rsqrt
 511 //
 512
 513 def INT_NVVM_RSQRT_APPROX_FTZ_F
 514   : F_MATH_1<"rsqrt.approx.ftz.f32 \t$dst, $src0;", Float32Regs, Float32Regs,
 515     int_nvvm_rsqrt_approx_ftz_f>;
 516 def INT_NVVM_RSQRT_APPROX_F : F_MATH_1<"rsqrt.approx.f32 \t$dst, $src0;",
 517   Float32Regs, Float32Regs, int_nvvm_rsqrt_approx_f>;
 518 def INT_NVVM_RSQRT_APPROX_D : F_MATH_1<"rsqrt.approx.f64 \t$dst, $src0;",
 519   Float64Regs, Float64Regs, int_nvvm_rsqrt_approx_d>;
 520
 521 //
 522 // Add
 523 //
 524
 525 def INT_NVVM_ADD_RN_FTZ_F : F_MATH_2<"add.rn.ftz.f32 \t$dst, $src0, $src1;",
 526   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rn_ftz_f>;
 527 def INT_NVVM_ADD_RN_F : F_MATH_2<"add.rn.f32 \t$dst, $src0, $src1;",
 528   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rn_f>;
 529 def INT_NVVM_ADD_RZ_FTZ_F : F_MATH_2<"add.rz.ftz.f32 \t$dst, $src0, $src1;",
 530   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rz_ftz_f>;
 531 def INT_NVVM_ADD_RZ_F : F_MATH_2<"add.rz.f32 \t$dst, $src0, $src1;",
 532   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rz_f>;
 533 def INT_NVVM_ADD_RM_FTZ_F : F_MATH_2<"add.rm.ftz.f32 \t$dst, $src0, $src1;",
 534   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rm_ftz_f>;
 535 def INT_NVVM_ADD_RM_F : F_MATH_2<"add.rm.f32 \t$dst, $src0, $src1;",
 536   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rm_f>;
 537 def INT_NVVM_ADD_RP_FTZ_F : F_MATH_2<"add.rp.ftz.f32 \t$dst, $src0, $src1;",
 538   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rp_ftz_f>;
 539 def INT_NVVM_ADD_RP_F : F_MATH_2<"add.rp.f32 \t$dst, $src0, $src1;",
 540   Float32Regs, Float32Regs, Float32Regs, int_nvvm_add_rp_f>;
 541
 542 def INT_NVVM_ADD_RN_D : F_MATH_2<"add.rn.f64 \t$dst, $src0, $src1;",
 543   Float64Regs, Float64Regs, Float64Regs, int_nvvm_add_rn_d>;
 544 def INT_NVVM_ADD_RZ_D : F_MATH_2<"add.rz.f64 \t$dst, $src0, $src1;",
 545   Float64Regs, Float64Regs, Float64Regs, int_nvvm_add_rz_d>;
 546 def INT_NVVM_ADD_RM_D : F_MATH_2<"add.rm.f64 \t$dst, $src0, $src1;",
 547   Float64Regs, Float64Regs, Float64Regs, int_nvvm_add_rm_d>;
 548 def INT_NVVM_ADD_RP_D : F_MATH_2<"add.rp.f64 \t$dst, $src0, $src1;",
 549   Float64Regs, Float64Regs, Float64Regs, int_nvvm_add_rp_d>;
 550
 551 //
 552 // Convert
 553 //
 554
 555 def : Pat<(int_nvvm_d2f_rn_ftz Float64Regs:$a),
 556           (CVT_f32_f64 Float64Regs:$a, CvtRN_FTZ)>;
 557 def : Pat<(int_nvvm_d2f_rn Float64Regs:$a),
 558           (CVT_f32_f64 Float64Regs:$a, CvtRN)>;
 559 def : Pat<(int_nvvm_d2f_rz_ftz Float64Regs:$a),
 560           (CVT_f32_f64 Float64Regs:$a, CvtRZ_FTZ)>;
 561 def : Pat<(int_nvvm_d2f_rz Float64Regs:$a),
 562           (CVT_f32_f64 Float64Regs:$a, CvtRZ)>;
 563 def : Pat<(int_nvvm_d2f_rm_ftz Float64Regs:$a),
 564           (CVT_f32_f64 Float64Regs:$a, CvtRM_FTZ)>;
 565 def : Pat<(int_nvvm_d2f_rm Float64Regs:$a),
 566           (CVT_f32_f64 Float64Regs:$a, CvtRM)>;
 567 def : Pat<(int_nvvm_d2f_rp_ftz Float64Regs:$a),
 568           (CVT_f32_f64 Float64Regs:$a, CvtRP_FTZ)>;
 569 def : Pat<(int_nvvm_d2f_rp Float64Regs:$a),
 570           (CVT_f32_f64 Float64Regs:$a, CvtRP)>;
 571
 572 def : Pat<(int_nvvm_d2i_rn Float64Regs:$a),
 573           (CVT_s32_f64 Float64Regs:$a, CvtRNI)>;
 574 def : Pat<(int_nvvm_d2i_rz Float64Regs:$a),
 575           (CVT_s32_f64 Float64Regs:$a, CvtRZI)>;
 576 def : Pat<(int_nvvm_d2i_rm Float64Regs:$a),
 577           (CVT_s32_f64 Float64Regs:$a, CvtRMI)>;
 578 def : Pat<(int_nvvm_d2i_rp Float64Regs:$a),
 579           (CVT_s32_f64 Float64Regs:$a, CvtRPI)>;
 580
 581 def : Pat<(int_nvvm_d2ui_rn Float64Regs:$a),
 582           (CVT_u32_f64 Float64Regs:$a, CvtRNI)>;
 583 def : Pat<(int_nvvm_d2ui_rz Float64Regs:$a),
 584           (CVT_u32_f64 Float64Regs:$a, CvtRZI)>;
 585 def : Pat<(int_nvvm_d2ui_rm Float64Regs:$a),
 586           (CVT_u32_f64 Float64Regs:$a, CvtRMI)>;
 587 def : Pat<(int_nvvm_d2ui_rp Float64Regs:$a),
 588           (CVT_u32_f64 Float64Regs:$a, CvtRPI)>;
 589
 590 def : Pat<(int_nvvm_i2d_rn Int32Regs:$a),
 591           (CVT_f64_s32 Int32Regs:$a, CvtRN)>;
 592 def : Pat<(int_nvvm_i2d_rz Int32Regs:$a),
 593           (CVT_f64_s32 Int32Regs:$a, CvtRZ)>;
 594 def : Pat<(int_nvvm_i2d_rm Int32Regs:$a),
 595           (CVT_f64_s32 Int32Regs:$a, CvtRM)>;
 596 def : Pat<(int_nvvm_i2d_rp Int32Regs:$a),
 597           (CVT_f64_s32 Int32Regs:$a, CvtRP)>;
 598
 599 def : Pat<(int_nvvm_ui2d_rn Int32Regs:$a),
 600           (CVT_f64_u32 Int32Regs:$a, CvtRN)>;
 601 def : Pat<(int_nvvm_ui2d_rz Int32Regs:$a),
 602           (CVT_f64_u32 Int32Regs:$a, CvtRZ)>;
 603 def : Pat<(int_nvvm_ui2d_rm Int32Regs:$a),
 604           (CVT_f64_u32 Int32Regs:$a, CvtRM)>;
 605 def : Pat<(int_nvvm_ui2d_rp Int32Regs:$a),
 606           (CVT_f64_u32 Int32Regs:$a, CvtRP)>;
 607
 608 def : Pat<(int_nvvm_f2i_rn_ftz Float32Regs:$a),
 609           (CVT_s32_f32 Float32Regs:$a, CvtRNI_FTZ)>;
 610 def : Pat<(int_nvvm_f2i_rn Float32Regs:$a),
 611           (CVT_s32_f32 Float32Regs:$a, CvtRNI)>;
 612 def : Pat<(int_nvvm_f2i_rz_ftz Float32Regs:$a),
 613           (CVT_s32_f32 Float32Regs:$a, CvtRZI_FTZ)>;
 614 def : Pat<(int_nvvm_f2i_rz Float32Regs:$a),
 615           (CVT_s32_f32 Float32Regs:$a, CvtRZI)>;
 616 def : Pat<(int_nvvm_f2i_rm_ftz Float32Regs:$a),
 617           (CVT_s32_f32 Float32Regs:$a, CvtRMI_FTZ)>;
 618 def : Pat<(int_nvvm_f2i_rm Float32Regs:$a),
 619           (CVT_s32_f32 Float32Regs:$a, CvtRMI)>;
 620 def : Pat<(int_nvvm_f2i_rp_ftz Float32Regs:$a),
 621           (CVT_s32_f32 Float32Regs:$a, CvtRPI_FTZ)>;
 622 def : Pat<(int_nvvm_f2i_rp Float32Regs:$a),
 623           (CVT_s32_f32 Float32Regs:$a, CvtRPI)>;
 624
 625 def : Pat<(int_nvvm_f2ui_rn_ftz Float32Regs:$a),
 626           (CVT_u32_f32 Float32Regs:$a, CvtRNI_FTZ)>;
 627 def : Pat<(int_nvvm_f2ui_rn Float32Regs:$a),
 628           (CVT_u32_f32 Float32Regs:$a, CvtRNI)>;
 629 def : Pat<(int_nvvm_f2ui_rz_ftz Float32Regs:$a),
 630           (CVT_u32_f32 Float32Regs:$a, CvtRZI_FTZ)>;
 631 def : Pat<(int_nvvm_f2ui_rz Float32Regs:$a),
 632           (CVT_u32_f32 Float32Regs:$a, CvtRZI)>;
 633 def : Pat<(int_nvvm_f2ui_rm_ftz Float32Regs:$a),
 634           (CVT_u32_f32 Float32Regs:$a, CvtRMI_FTZ)>;
 635 def : Pat<(int_nvvm_f2ui_rm Float32Regs:$a),
 636           (CVT_u32_f32 Float32Regs:$a, CvtRMI)>;
 637 def : Pat<(int_nvvm_f2ui_rp_ftz Float32Regs:$a),
 638           (CVT_u32_f32 Float32Regs:$a, CvtRPI_FTZ)>;
 639 def : Pat<(int_nvvm_f2ui_rp Float32Regs:$a),
 640           (CVT_u32_f32 Float32Regs:$a, CvtRPI)>;
 641
 642 def : Pat<(int_nvvm_i2f_rn Int32Regs:$a),
 643           (CVT_f32_s32 Int32Regs:$a, CvtRN)>;
 644 def : Pat<(int_nvvm_i2f_rz Int32Regs:$a),
 645           (CVT_f32_s32 Int32Regs:$a, CvtRZ)>;
 646 def : Pat<(int_nvvm_i2f_rm Int32Regs:$a),
 647           (CVT_f32_s32 Int32Regs:$a, CvtRM)>;
 648 def : Pat<(int_nvvm_i2f_rp Int32Regs:$a),
 649           (CVT_f32_s32 Int32Regs:$a, CvtRP)>;
 650
 651 def : Pat<(int_nvvm_ui2f_rn Int32Regs:$a),
 652           (CVT_f32_u32 Int32Regs:$a, CvtRN)>;
 653 def : Pat<(int_nvvm_ui2f_rz Int32Regs:$a),
 654           (CVT_f32_u32 Int32Regs:$a, CvtRZ)>;
 655 def : Pat<(int_nvvm_ui2f_rm Int32Regs:$a),
 656           (CVT_f32_u32 Int32Regs:$a, CvtRM)>;
 657 def : Pat<(int_nvvm_ui2f_rp Int32Regs:$a),
 658           (CVT_f32_u32 Int32Regs:$a, CvtRP)>;
 659
 660 def INT_NVVM_LOHI_I2D : F_MATH_2<"mov.b64 \t$dst, {{$src0, $src1}};",
 661   Float64Regs, Int32Regs, Int32Regs, int_nvvm_lohi_i2d>;
 662
 663 def INT_NVVM_D2I_LO : F_MATH_1<!strconcat("{{\n\t",
 664                        !strconcat(".reg .b32 %temp; \n\t",
 665              !strconcat("mov.b64 \t{$dst, %temp}, $src0;\n\t",
 666                "}}"))),
 667              Int32Regs, Float64Regs, int_nvvm_d2i_lo>;
 668 def INT_NVVM_D2I_HI : F_MATH_1<!strconcat("{{\n\t",
 669                        !strconcat(".reg .b32 %temp; \n\t",
 670                          !strconcat("mov.b64 \t{%temp, $dst}, $src0;\n\t",
 671                            "}}"))),
 672              Int32Regs, Float64Regs, int_nvvm_d2i_hi>;
 673
 674 def : Pat<(int_nvvm_f2ll_rn_ftz Float32Regs:$a),
 675           (CVT_s64_f32 Float32Regs:$a, CvtRNI_FTZ)>;
 676 def : Pat<(int_nvvm_f2ll_rn Float32Regs:$a),
 677           (CVT_s64_f32 Float32Regs:$a, CvtRNI)>;
 678 def : Pat<(int_nvvm_f2ll_rz_ftz Float32Regs:$a),
 679           (CVT_s64_f32 Float32Regs:$a, CvtRZI_FTZ)>;
 680 def : Pat<(int_nvvm_f2ll_rz Float32Regs:$a),
 681           (CVT_s64_f32 Float32Regs:$a, CvtRZI)>;
 682 def : Pat<(int_nvvm_f2ll_rm_ftz Float32Regs:$a),
 683           (CVT_s64_f32 Float32Regs:$a, CvtRMI_FTZ)>;
 684 def : Pat<(int_nvvm_f2ll_rm Float32Regs:$a),
 685           (CVT_s64_f32 Float32Regs:$a, CvtRMI)>;
 686 def : Pat<(int_nvvm_f2ll_rp_ftz Float32Regs:$a),
 687           (CVT_s64_f32 Float32Regs:$a, CvtRPI_FTZ)>;
 688 def : Pat<(int_nvvm_f2ll_rp Float32Regs:$a),
 689           (CVT_s64_f32 Float32Regs:$a, CvtRPI)>;
 690
 691 def : Pat<(int_nvvm_f2ull_rn_ftz Float32Regs:$a),
 692           (CVT_u64_f32 Float32Regs:$a, CvtRNI_FTZ)>;
 693 def : Pat<(int_nvvm_f2ull_rn Float32Regs:$a),
 694           (CVT_u64_f32 Float32Regs:$a, CvtRNI)>;
 695 def : Pat<(int_nvvm_f2ull_rz_ftz Float32Regs:$a),
 696           (CVT_u64_f32 Float32Regs:$a, CvtRZI_FTZ)>;
 697 def : Pat<(int_nvvm_f2ull_rz Float32Regs:$a),
 698           (CVT_u64_f32 Float32Regs:$a, CvtRZI)>;
 699 def : Pat<(int_nvvm_f2ull_rm_ftz Float32Regs:$a),
 700           (CVT_u64_f32 Float32Regs:$a, CvtRMI_FTZ)>;
 701 def : Pat<(int_nvvm_f2ull_rm Float32Regs:$a),
 702           (CVT_u64_f32 Float32Regs:$a, CvtRMI)>;
 703 def : Pat<(int_nvvm_f2ull_rp_ftz Float32Regs:$a),
 704           (CVT_u64_f32 Float32Regs:$a, CvtRPI_FTZ)>;
 705 def : Pat<(int_nvvm_f2ull_rp Float32Regs:$a),
 706           (CVT_u64_f32 Float32Regs:$a, CvtRPI)>;
 707
 708 def : Pat<(int_nvvm_d2ll_rn Float64Regs:$a),
 709           (CVT_s64_f64 Float64Regs:$a, CvtRNI)>;
 710 def : Pat<(int_nvvm_d2ll_rz Float64Regs:$a),
 711           (CVT_s64_f64 Float64Regs:$a, CvtRZI)>;
 712 def : Pat<(int_nvvm_d2ll_rm Float64Regs:$a),
 713           (CVT_s64_f64 Float64Regs:$a, CvtRMI)>;
 714 def : Pat<(int_nvvm_d2ll_rp Float64Regs:$a),
 715           (CVT_s64_f64 Float64Regs:$a, CvtRPI)>;
 716
 717 def : Pat<(int_nvvm_d2ull_rn Float64Regs:$a),
 718           (CVT_u64_f64 Float64Regs:$a, CvtRNI)>;
 719 def : Pat<(int_nvvm_d2ull_rz Float64Regs:$a),
 720           (CVT_u64_f64 Float64Regs:$a, CvtRZI)>;
 721 def : Pat<(int_nvvm_d2ull_rm Float64Regs:$a),
 722           (CVT_u64_f64 Float64Regs:$a, CvtRMI)>;
 723 def : Pat<(int_nvvm_d2ull_rp Float64Regs:$a),
 724           (CVT_u64_f64 Float64Regs:$a, CvtRPI)>;
 725
 726 def : Pat<(int_nvvm_ll2f_rn Int64Regs:$a),
 727           (CVT_f32_s64 Int64Regs:$a, CvtRN)>;
 728 def : Pat<(int_nvvm_ll2f_rz Int64Regs:$a),
 729           (CVT_f32_s64 Int64Regs:$a, CvtRZ)>;
 730 def : Pat<(int_nvvm_ll2f_rm Int64Regs:$a),
 731           (CVT_f32_s64 Int64Regs:$a, CvtRM)>;
 732 def : Pat<(int_nvvm_ll2f_rp Int64Regs:$a),
 733           (CVT_f32_s64 Int64Regs:$a, CvtRP)>;
 734
 735 def : Pat<(int_nvvm_ull2f_rn Int64Regs:$a),
 736           (CVT_f32_u64 Int64Regs:$a, CvtRN)>;
 737 def : Pat<(int_nvvm_ull2f_rz Int64Regs:$a),
 738           (CVT_f32_u64 Int64Regs:$a, CvtRZ)>;
 739 def : Pat<(int_nvvm_ull2f_rm Int64Regs:$a),
 740           (CVT_f32_u64 Int64Regs:$a, CvtRM)>;
 741 def : Pat<(int_nvvm_ull2f_rp Int64Regs:$a),
 742           (CVT_f32_u64 Int64Regs:$a, CvtRP)>;
 743
 744 def : Pat<(int_nvvm_ll2d_rn Int64Regs:$a),
 745           (CVT_f64_s64 Int64Regs:$a, CvtRN)>;
 746 def : Pat<(int_nvvm_ll2d_rz Int64Regs:$a),
 747           (CVT_f64_s64 Int64Regs:$a, CvtRZ)>;
 748 def : Pat<(int_nvvm_ll2d_rm Int64Regs:$a),
 749           (CVT_f64_s64 Int64Regs:$a, CvtRM)>;
 750 def : Pat<(int_nvvm_ll2d_rp Int64Regs:$a),
 751           (CVT_f64_s64 Int64Regs:$a, CvtRP)>;
 752
 753 def : Pat<(int_nvvm_ull2d_rn Int64Regs:$a),
 754           (CVT_f64_u64 Int64Regs:$a, CvtRN)>;
 755 def : Pat<(int_nvvm_ull2d_rz Int64Regs:$a),
 756           (CVT_f64_u64 Int64Regs:$a, CvtRZ)>;
 757 def : Pat<(int_nvvm_ull2d_rm Int64Regs:$a),
 758           (CVT_f64_u64 Int64Regs:$a, CvtRM)>;
 759 def : Pat<(int_nvvm_ull2d_rp Int64Regs:$a),
 760           (CVT_f64_u64 Int64Regs:$a, CvtRP)>;
 761
 762
 763 // FIXME: Ideally, we could use these patterns instead of the scope-creating
 764 // patterns, but ptxas does not like these since .s16 is not compatible with
 765 // .f16.  The solution is to use .bXX for all integer register types, but we
 766 // are not there yet.
 767 //def : Pat<(int_nvvm_f2h_rn_ftz Float32Regs:$a),
 768 //          (CVT_f16_f32 Float32Regs:$a, CvtRN_FTZ)>;
 769 //def : Pat<(int_nvvm_f2h_rn Float32Regs:$a),
 770 //          (CVT_f16_f32 Float32Regs:$a, CvtRN)>;
 771 //
 772 //def : Pat<(int_nvvm_h2f Int16Regs:$a),
 773 //          (CVT_f32_f16 Int16Regs:$a, CvtNONE)>;
 774
 775 def INT_NVVM_F2H_RN_FTZ : F_MATH_1<!strconcat("{{\n\t",
 776                                    !strconcat(".reg .b16 %temp;\n\t",
 777            !strconcat("cvt.rn.ftz.f16.f32 \t%temp, $src0;\n\t",
 778            !strconcat("mov.b16 \t$dst, %temp;\n",
 779              "}}")))),
 780                                    Int16Regs, Float32Regs, int_nvvm_f2h_rn_ftz>;
 781 def INT_NVVM_F2H_RN : F_MATH_1<!strconcat("{{\n\t",
 782                                    !strconcat(".reg .b16 %temp;\n\t",
 783            !strconcat("cvt.rn.f16.f32 \t%temp, $src0;\n\t",
 784            !strconcat("mov.b16 \t$dst, %temp;\n",
 785              "}}")))),
 786            Int16Regs, Float32Regs, int_nvvm_f2h_rn>;
 787
 788 def INT_NVVM_H2F : F_MATH_1<!strconcat("{{\n\t",
 789                             !strconcat(".reg .b16 %temp;\n\t",
 790           !strconcat("mov.b16 \t%temp, $src0;\n\t",
 791           !strconcat("cvt.f32.f16 \t$dst, %temp;\n\t",
 792             "}}")))),
 793           Float32Regs, Int16Regs, int_nvvm_h2f>;
 794
 795 def : Pat<(f32 (f16_to_f32 Int16Regs:$a)),
 796           (CVT_f32_f16 Int16Regs:$a, CvtNONE)>;
 797 def : Pat<(i16 (f32_to_f16 Float32Regs:$a)),
 798           (CVT_f16_f32 Float32Regs:$a, CvtRN_FTZ)>, Requires<[doF32FTZ]>;
 799 def : Pat<(i16 (f32_to_f16 Float32Regs:$a)),
 800           (CVT_f16_f32 Float32Regs:$a, CvtRN)>;
 801
 802 //
 803 // Bitcast
 804 //
 805
 806 def INT_NVVM_BITCAST_F2I : F_MATH_1<"mov.b32 \t$dst, $src0;", Int32Regs,
 807   Float32Regs, int_nvvm_bitcast_f2i>;
 808 def INT_NVVM_BITCAST_I2F : F_MATH_1<"mov.b32 \t$dst, $src0;", Float32Regs,
 809   Int32Regs, int_nvvm_bitcast_i2f>;
 810
 811 def INT_NVVM_BITCAST_LL2D : F_MATH_1<"mov.b64 \t$dst, $src0;", Float64Regs,
 812   Int64Regs, int_nvvm_bitcast_ll2d>;
 813 def INT_NVVM_BITCAST_D2LL : F_MATH_1<"mov.b64 \t$dst, $src0;", Int64Regs,
 814   Float64Regs, int_nvvm_bitcast_d2ll>;
 815
 816 //-----------------------------------
 817 // Atomic Functions
 818 //-----------------------------------
 819
 820 class ATOMIC_GLOBAL_CHK <dag ops, dag frag>
 821  : PatFrag<ops, frag, [{
 822    return ChkMemSDNodeAddressSpace(N, llvm::ADDRESS_SPACE_GLOBAL);
 823 }]>;
 824 class ATOMIC_SHARED_CHK <dag ops, dag frag>
 825  : PatFrag<ops, frag, [{
 826    return ChkMemSDNodeAddressSpace(N, llvm::ADDRESS_SPACE_SHARED);
 827 }]>;
 828 class ATOMIC_GENERIC_CHK <dag ops, dag frag>
 829  : PatFrag<ops, frag, [{
 830    return ChkMemSDNodeAddressSpace(N, llvm::ADDRESS_SPACE_GENERIC);
 831 }]>;
 832
 833 multiclass F_ATOMIC_2_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
 834   string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp,
 835   Operand IMMType, SDNode IMM, Predicate Pred> {
 836   def reg : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, regclass:$b),
 837                !strconcat("atom",
 838          !strconcat(SpaceStr,
 839          !strconcat(OpcStr,
 840          !strconcat(TypeStr,
 841          !strconcat(" \t$dst, [$addr], $b;", ""))))),
 842          [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b))]>,
 843   Requires<[Pred]>;
 844   def imm : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, IMMType:$b),
 845                !strconcat("atom",
 846          !strconcat(SpaceStr,
 847          !strconcat(OpcStr,
 848          !strconcat(TypeStr,
 849          !strconcat(" \t$dst, [$addr], $b;", ""))))),
 850          [(set regclass:$dst, (IntOp ptrclass:$addr, IMM:$b))]>,
 851   Requires<[Pred]>;
 852 }
 853 multiclass F_ATOMIC_2<NVPTXRegClass regclass, string SpaceStr, string TypeStr,
 854   string OpcStr, PatFrag IntOp, Operand IMMType, SDNode IMM, Predicate Pred> {
 855   defm p32 : F_ATOMIC_2_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
 856     IntOp, IMMType, IMM, Pred>;
 857   defm p64 : F_ATOMIC_2_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
 858     IntOp, IMMType, IMM, Pred>;
 859 }
 860
 861 // has 2 operands, neg the second one
 862 multiclass F_ATOMIC_2_NEG_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
 863   string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp,
 864   Operand IMMType, Predicate Pred> {
 865   def reg : NVPTXInst<(outs regclass:$dst), (ins ptrclass:$addr, regclass:$b),
 866     !strconcat("{{ \n\t",
 867          !strconcat(".reg \t.s",
 868          !strconcat(TypeStr,
 869          !strconcat(" temp; \n\t",
 870          !strconcat("neg.s",
 871          !strconcat(TypeStr,
 872          !strconcat(" \ttemp, $b; \n\t",
 873                !strconcat("atom",
 874          !strconcat(SpaceStr,
 875          !strconcat(OpcStr,
 876          !strconcat(".u",
 877          !strconcat(TypeStr,
 878          !strconcat(" \t$dst, [$addr], temp; \n\t",
 879            !strconcat("}}", "")))))))))))))),
 880          [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b))]>,
 881   Requires<[Pred]>;
 882 }
 883 multiclass F_ATOMIC_2_NEG<NVPTXRegClass regclass, string SpaceStr,
 884   string TypeStr, string OpcStr, PatFrag IntOp, Operand IMMType,
 885   Predicate Pred> {
 886  defm p32: F_ATOMIC_2_NEG_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
 887    IntOp, IMMType, Pred> ;
 888  defm p64: F_ATOMIC_2_NEG_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
 889    IntOp, IMMType, Pred> ;
 890 }
 891
 892 // has 3 operands
 893 multiclass F_ATOMIC_3_imp<NVPTXRegClass ptrclass, NVPTXRegClass regclass,
 894   string SpaceStr, string TypeStr, string OpcStr, PatFrag IntOp,
 895   Operand IMMType, Predicate Pred> {
 896   def reg : NVPTXInst<(outs regclass:$dst),
 897     (ins ptrclass:$addr, regclass:$b, regclass:$c),
 898                !strconcat("atom",
 899          !strconcat(SpaceStr,
 900          !strconcat(OpcStr,
 901          !strconcat(TypeStr,
 902          !strconcat(" \t$dst, [$addr], $b, $c;", ""))))),
 903          [(set regclass:$dst,
 904            (IntOp ptrclass:$addr, regclass:$b, regclass:$c))]>,
 905          Requires<[Pred]>;
 906   def imm1 : NVPTXInst<(outs regclass:$dst),
 907     (ins ptrclass:$addr, IMMType:$b, regclass:$c),
 908                !strconcat("atom",
 909          !strconcat(SpaceStr,
 910          !strconcat(OpcStr,
 911          !strconcat(TypeStr,
 912          !strconcat(" \t$dst, [$addr], $b, $c;", ""))))),
 913          [(set regclass:$dst, (IntOp ptrclass:$addr, imm:$b, regclass:$c))]>,
 914   Requires<[Pred]>;
 915   def imm2 : NVPTXInst<(outs regclass:$dst),
 916     (ins ptrclass:$addr, regclass:$b, IMMType:$c),
 917                !strconcat("atom",
 918          !strconcat(SpaceStr,
 919          !strconcat(OpcStr,
 920          !strconcat(TypeStr,
 921          !strconcat(" \t$dst, [$addr], $b, $c;", ""))))),
 922          [(set regclass:$dst, (IntOp ptrclass:$addr, regclass:$b, imm:$c))]>,
 923   Requires<[Pred]>;
 924   def imm3 : NVPTXInst<(outs regclass:$dst),
 925     (ins ptrclass:$addr, IMMType:$b, IMMType:$c),
 926                !strconcat("atom",
 927          !strconcat(SpaceStr,
 928          !strconcat(OpcStr,
 929          !strconcat(TypeStr,
 930          !strconcat(" \t$dst, [$addr], $b, $c;", ""))))),
 931          [(set regclass:$dst, (IntOp ptrclass:$addr, imm:$b, imm:$c))]>,
 932   Requires<[Pred]>;
 933 }
 934 multiclass F_ATOMIC_3<NVPTXRegClass regclass, string SpaceStr, string TypeStr,
 935   string OpcStr, PatFrag IntOp, Operand IMMType, Predicate Pred> {
 936   defm p32 : F_ATOMIC_3_imp<Int32Regs, regclass, SpaceStr, TypeStr, OpcStr,
 937     IntOp, IMMType, Pred>;
 938   defm p64 : F_ATOMIC_3_imp<Int64Regs, regclass, SpaceStr, TypeStr, OpcStr,
 939     IntOp, IMMType, Pred>;
 940 }
 941
 942 // atom_add
 943
 944 def atomic_load_add_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
 945   (atomic_load_add_32 node:$a, node:$b)>;
 946 def atomic_load_add_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
 947   (atomic_load_add_32 node:$a, node:$b)>;
 948 def atomic_load_add_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
 949   (atomic_load_add_32 node:$a, node:$b)>;
 950 def atomic_load_add_64_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
 951   (atomic_load_add_64 node:$a, node:$b)>;
 952 def atomic_load_add_64_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
 953   (atomic_load_add_64 node:$a, node:$b)>;
 954 def atomic_load_add_64_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
 955   (atomic_load_add_64 node:$a, node:$b)>;
 956 def atomic_load_add_f32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
 957   (int_nvvm_atomic_load_add_f32 node:$a, node:$b)>;
 958 def atomic_load_add_f32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
 959   (int_nvvm_atomic_load_add_f32 node:$a, node:$b)>;
 960 def atomic_load_add_f32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
 961   (int_nvvm_atomic_load_add_f32 node:$a, node:$b)>;
 962
 963 defm INT_PTX_ATOM_ADD_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".u32", ".add",
 964   atomic_load_add_32_g, i32imm, imm, hasAtomRedG32>;
 965 defm INT_PTX_ATOM_ADD_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".u32", ".add",
 966   atomic_load_add_32_s, i32imm, imm, hasAtomRedS32>;
 967 defm INT_PTX_ATOM_ADD_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".u32", ".add",
 968   atomic_load_add_32_gen, i32imm, imm, hasAtomRedGen32>;
 969 defm INT_PTX_ATOM_ADD_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global", ".u32",
 970   ".add", atomic_load_add_32_gen, i32imm, imm, useAtomRedG32forGen32>;
 971
 972 defm INT_PTX_ATOM_ADD_G_64 : F_ATOMIC_2<Int64Regs, ".global", ".u64", ".add",
 973   atomic_load_add_64_g, i64imm, imm, hasAtomRedG64>;
 974 defm INT_PTX_ATOM_ADD_S_64 : F_ATOMIC_2<Int64Regs, ".shared", ".u64", ".add",
 975   atomic_load_add_64_s, i64imm, imm, hasAtomRedS64>;
 976 defm INT_PTX_ATOM_ADD_GEN_64 : F_ATOMIC_2<Int64Regs, "", ".u64", ".add",
 977   atomic_load_add_64_gen, i64imm, imm, hasAtomRedGen64>;
 978 defm INT_PTX_ATOM_ADD_GEN_64_USE_G : F_ATOMIC_2<Int64Regs, ".global", ".u64",
 979   ".add", atomic_load_add_64_gen, i64imm, imm, useAtomRedG64forGen64>;
 980
 981 defm INT_PTX_ATOM_ADD_G_F32 : F_ATOMIC_2<Float32Regs, ".global", ".f32", ".add",
 982   atomic_load_add_f32_g, f32imm, fpimm, hasAtomAddF32>;
 983 defm INT_PTX_ATOM_ADD_S_F32 : F_ATOMIC_2<Float32Regs, ".shared", ".f32", ".add",
 984   atomic_load_add_f32_s, f32imm, fpimm, hasAtomAddF32>;
 985 defm INT_PTX_ATOM_ADD_GEN_F32 : F_ATOMIC_2<Float32Regs, "", ".f32", ".add",
 986   atomic_load_add_f32_gen, f32imm, fpimm, hasAtomAddF32>;
 987
 988 // atom_sub
 989
 990 def atomic_load_sub_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
 991   (atomic_load_sub_32 node:$a, node:$b)>;
 992 def atomic_load_sub_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
 993   (atomic_load_sub_32 node:$a, node:$b)>;
 994 def atomic_load_sub_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
 995   (atomic_load_sub_32 node:$a, node:$b)>;
 996 def atomic_load_sub_64_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
 997   (atomic_load_sub_64 node:$a, node:$b)>;
 998 def atomic_load_sub_64_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
 999   (atomic_load_sub_64 node:$a, node:$b)>;
1000 def atomic_load_sub_64_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1001   (atomic_load_sub_64 node:$a, node:$b)>;
1002
1003 defm INT_PTX_ATOM_SUB_G_32 : F_ATOMIC_2_NEG<Int32Regs, ".global", "32", ".add",
1004   atomic_load_sub_32_g, i32imm, hasAtomRedG32>;
1005 defm INT_PTX_ATOM_SUB_G_64 : F_ATOMIC_2_NEG<Int64Regs, ".global", "64", ".add",
1006   atomic_load_sub_64_g, i64imm, hasAtomRedG64>;
1007 defm INT_PTX_ATOM_SUB_GEN_32 : F_ATOMIC_2_NEG<Int32Regs, "", "32", ".add",
1008   atomic_load_sub_32_gen, i32imm, hasAtomRedGen32>;
1009 defm INT_PTX_ATOM_SUB_GEN_32_USE_G : F_ATOMIC_2_NEG<Int32Regs, ".global", "32",
1010   ".add", atomic_load_sub_32_gen, i32imm, useAtomRedG32forGen32>;
1011 defm INT_PTX_ATOM_SUB_S_32 : F_ATOMIC_2_NEG<Int32Regs, ".shared", "32", ".add",
1012   atomic_load_sub_32_s, i32imm, hasAtomRedS32>;
1013 defm INT_PTX_ATOM_SUB_S_64 : F_ATOMIC_2_NEG<Int64Regs, ".shared", "64", ".add",
1014   atomic_load_sub_64_s, i64imm, hasAtomRedS64>;
1015 defm INT_PTX_ATOM_SUB_GEN_64 : F_ATOMIC_2_NEG<Int64Regs, "", "64", ".add",
1016   atomic_load_sub_64_gen, i64imm, hasAtomRedGen64>;
1017 defm INT_PTX_ATOM_SUB_GEN_64_USE_G : F_ATOMIC_2_NEG<Int64Regs, ".global", "64",
1018   ".add", atomic_load_sub_64_gen, i64imm, useAtomRedG64forGen64>;
1019
1020 // atom_swap
1021
1022 def atomic_swap_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1023   (atomic_swap_32 node:$a, node:$b)>;
1024 def atomic_swap_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1025   (atomic_swap_32 node:$a, node:$b)>;
1026 def atomic_swap_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1027   (atomic_swap_32 node:$a, node:$b)>;
1028 def atomic_swap_64_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1029   (atomic_swap_64 node:$a, node:$b)>;
1030 def atomic_swap_64_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1031   (atomic_swap_64 node:$a, node:$b)>;
1032 def atomic_swap_64_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1033   (atomic_swap_64 node:$a, node:$b)>;
1034
1035 defm INT_PTX_ATOM_SWAP_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".b32", ".exch",
1036   atomic_swap_32_g, i32imm, imm, hasAtomRedG32>;
1037 defm INT_PTX_ATOM_SWAP_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".b32", ".exch",
1038   atomic_swap_32_s, i32imm, imm, hasAtomRedS32>;
1039 defm INT_PTX_ATOM_SWAP_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".b32", ".exch",
1040   atomic_swap_32_gen, i32imm, imm, hasAtomRedGen32>;
1041 defm INT_PTX_ATOM_SWAP_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global", ".b32",
1042   ".exch", atomic_swap_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1043 defm INT_PTX_ATOM_SWAP_G_64 : F_ATOMIC_2<Int64Regs, ".global", ".b64", ".exch",
1044   atomic_swap_64_g, i64imm, imm, hasAtomRedG64>;
1045 defm INT_PTX_ATOM_SWAP_S_64 : F_ATOMIC_2<Int64Regs, ".shared", ".b64", ".exch",
1046   atomic_swap_64_s, i64imm, imm, hasAtomRedS64>;
1047 defm INT_PTX_ATOM_SWAP_GEN_64 : F_ATOMIC_2<Int64Regs, "", ".b64", ".exch",
1048   atomic_swap_64_gen, i64imm, imm, hasAtomRedGen64>;
1049 defm INT_PTX_ATOM_SWAP_GEN_64_USE_G : F_ATOMIC_2<Int64Regs, ".global", ".b64",
1050   ".exch", atomic_swap_64_gen, i64imm, imm, useAtomRedG64forGen64>;
1051
1052 // atom_max
1053
1054 def atomic_load_max_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b)
1055   , (atomic_load_max_32 node:$a, node:$b)>;
1056 def atomic_load_max_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1057   (atomic_load_max_32 node:$a, node:$b)>;
1058 def atomic_load_max_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1059   (atomic_load_max_32 node:$a, node:$b)>;
1060 def atomic_load_umax_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1061   (atomic_load_umax_32 node:$a, node:$b)>;
1062 def atomic_load_umax_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1063   (atomic_load_umax_32 node:$a, node:$b)>;
1064 def atomic_load_umax_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1065   (atomic_load_umax_32 node:$a, node:$b)>;
1066
1067 defm INT_PTX_ATOM_LOAD_MAX_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".s32",
1068   ".max", atomic_load_max_32_g, i32imm, imm, hasAtomRedG32>;
1069 defm INT_PTX_ATOM_LOAD_MAX_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".s32",
1070   ".max", atomic_load_max_32_s, i32imm, imm, hasAtomRedS32>;
1071 defm INT_PTX_ATOM_LOAD_MAX_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".s32", ".max",
1072   atomic_load_max_32_gen, i32imm, imm, hasAtomRedGen32>;
1073 defm INT_PTX_ATOM_LOAD_MAX_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global",
1074   ".s32", ".max", atomic_load_max_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1075 defm INT_PTX_ATOM_LOAD_UMAX_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".u32",
1076   ".max", atomic_load_umax_32_g, i32imm, imm, hasAtomRedG32>;
1077 defm INT_PTX_ATOM_LOAD_UMAX_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".u32",
1078   ".max", atomic_load_umax_32_s, i32imm, imm, hasAtomRedS32>;
1079 defm INT_PTX_ATOM_LOAD_UMAX_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".u32", ".max",
1080   atomic_load_umax_32_gen, i32imm, imm, hasAtomRedGen32>;
1081 defm INT_PTX_ATOM_LOAD_UMAX_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global",
1082   ".u32", ".max", atomic_load_umax_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1083
1084 // atom_min
1085
1086 def atomic_load_min_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1087   (atomic_load_min_32 node:$a, node:$b)>;
1088 def atomic_load_min_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1089   (atomic_load_min_32 node:$a, node:$b)>;
1090 def atomic_load_min_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1091   (atomic_load_min_32 node:$a, node:$b)>;
1092 def atomic_load_umin_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1093   (atomic_load_umin_32 node:$a, node:$b)>;
1094 def atomic_load_umin_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1095   (atomic_load_umin_32 node:$a, node:$b)>;
1096 def atomic_load_umin_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1097   (atomic_load_umin_32 node:$a, node:$b)>;
1098
1099 defm INT_PTX_ATOM_LOAD_MIN_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".s32",
1100   ".min", atomic_load_min_32_g, i32imm, imm, hasAtomRedG32>;
1101 defm INT_PTX_ATOM_LOAD_MIN_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".s32",
1102   ".min", atomic_load_min_32_s, i32imm, imm, hasAtomRedS32>;
1103 defm INT_PTX_ATOM_LOAD_MIN_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".s32", ".min",
1104   atomic_load_min_32_gen, i32imm, imm, hasAtomRedGen32>;
1105 defm INT_PTX_ATOM_LOAD_MIN_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global",
1106   ".s32", ".min", atomic_load_min_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1107 defm INT_PTX_ATOM_LOAD_UMIN_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".u32",
1108   ".min", atomic_load_umin_32_g, i32imm, imm, hasAtomRedG32>;
1109 defm INT_PTX_ATOM_LOAD_UMIN_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".u32",
1110   ".min", atomic_load_umin_32_s, i32imm, imm, hasAtomRedS32>;
1111 defm INT_PTX_ATOM_LOAD_UMIN_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".u32", ".min",
1112   atomic_load_umin_32_gen, i32imm, imm, hasAtomRedGen32>;
1113 defm INT_PTX_ATOM_LOAD_UMIN_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global",
1114   ".u32", ".min", atomic_load_umin_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1115
1116 // atom_inc  atom_dec
1117
1118 def atomic_load_inc_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1119   (int_nvvm_atomic_load_inc_32 node:$a, node:$b)>;
1120 def atomic_load_inc_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1121   (int_nvvm_atomic_load_inc_32 node:$a, node:$b)>;
1122 def atomic_load_inc_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1123   (int_nvvm_atomic_load_inc_32 node:$a, node:$b)>;
1124 def atomic_load_dec_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1125   (int_nvvm_atomic_load_dec_32 node:$a, node:$b)>;
1126 def atomic_load_dec_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1127   (int_nvvm_atomic_load_dec_32 node:$a, node:$b)>;
1128 def atomic_load_dec_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1129   (int_nvvm_atomic_load_dec_32 node:$a, node:$b)>;
1130
1131 defm INT_PTX_ATOM_INC_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".u32", ".inc",
1132   atomic_load_inc_32_g, i32imm, imm, hasAtomRedG32>;
1133 defm INT_PTX_ATOM_INC_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".u32", ".inc",
1134   atomic_load_inc_32_s, i32imm, imm, hasAtomRedS32>;
1135 defm INT_PTX_ATOM_INC_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".u32", ".inc",
1136   atomic_load_inc_32_gen, i32imm, imm, hasAtomRedGen32>;
1137 defm INT_PTX_ATOM_INC_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global", ".u32",
1138   ".inc", atomic_load_inc_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1139 defm INT_PTX_ATOM_DEC_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".u32", ".dec",
1140   atomic_load_dec_32_g, i32imm, imm, hasAtomRedG32>;
1141 defm INT_PTX_ATOM_DEC_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".u32", ".dec",
1142   atomic_load_dec_32_s, i32imm, imm, hasAtomRedS32>;
1143 defm INT_PTX_ATOM_DEC_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".u32", ".dec",
1144   atomic_load_dec_32_gen, i32imm, imm, hasAtomRedGen32>;
1145 defm INT_PTX_ATOM_DEC_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global", ".u32",
1146   ".dec", atomic_load_dec_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1147
1148 // atom_and
1149
1150 def atomic_load_and_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1151   (atomic_load_and_32 node:$a, node:$b)>;
1152 def atomic_load_and_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1153   (atomic_load_and_32 node:$a, node:$b)>;
1154 def atomic_load_and_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1155   (atomic_load_and_32 node:$a, node:$b)>;
1156
1157 defm INT_PTX_ATOM_AND_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".b32", ".and",
1158   atomic_load_and_32_g, i32imm, imm, hasAtomRedG32>;
1159 defm INT_PTX_ATOM_AND_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".b32", ".and",
1160   atomic_load_and_32_s, i32imm, imm, hasAtomRedS32>;
1161 defm INT_PTX_ATOM_AND_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".b32", ".and",
1162   atomic_load_and_32_gen, i32imm, imm, hasAtomRedGen32>;
1163 defm INT_PTX_ATOM_AND_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global", ".b32",
1164   ".and", atomic_load_and_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1165
1166 // atom_or
1167
1168 def atomic_load_or_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1169   (atomic_load_or_32 node:$a, node:$b)>;
1170 def atomic_load_or_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1171   (atomic_load_or_32 node:$a, node:$b)>;
1172 def atomic_load_or_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1173   (atomic_load_or_32 node:$a, node:$b)>;
1174
1175 defm INT_PTX_ATOM_OR_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".b32", ".or",
1176   atomic_load_or_32_g, i32imm, imm, hasAtomRedG32>;
1177 defm INT_PTX_ATOM_OR_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".b32", ".or",
1178   atomic_load_or_32_gen, i32imm, imm, hasAtomRedGen32>;
1179 defm INT_PTX_ATOM_OR_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global", ".b32",
1180   ".or", atomic_load_or_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1181 defm INT_PTX_ATOM_OR_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".b32", ".or",
1182   atomic_load_or_32_s, i32imm, imm, hasAtomRedS32>;
1183
1184 // atom_xor
1185
1186 def atomic_load_xor_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b),
1187   (atomic_load_xor_32 node:$a, node:$b)>;
1188 def atomic_load_xor_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b),
1189   (atomic_load_xor_32 node:$a, node:$b)>;
1190 def atomic_load_xor_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b),
1191   (atomic_load_xor_32 node:$a, node:$b)>;
1192
1193 defm INT_PTX_ATOM_XOR_G_32 : F_ATOMIC_2<Int32Regs, ".global", ".b32", ".xor",
1194   atomic_load_xor_32_g, i32imm, imm, hasAtomRedG32>;
1195 defm INT_PTX_ATOM_XOR_S_32 : F_ATOMIC_2<Int32Regs, ".shared", ".b32", ".xor",
1196   atomic_load_xor_32_s, i32imm, imm, hasAtomRedS32>;
1197 defm INT_PTX_ATOM_XOR_GEN_32 : F_ATOMIC_2<Int32Regs, "", ".b32", ".xor",
1198   atomic_load_xor_32_gen, i32imm, imm, hasAtomRedGen32>;
1199 defm INT_PTX_ATOM_XOR_GEN_32_USE_G : F_ATOMIC_2<Int32Regs, ".global", ".b32",
1200   ".xor", atomic_load_xor_32_gen, i32imm, imm, useAtomRedG32forGen32>;
1201
1202 // atom_cas
1203
1204 def atomic_cmp_swap_32_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b, node:$c),
1205   (atomic_cmp_swap_32 node:$a, node:$b, node:$c)>;
1206 def atomic_cmp_swap_32_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b, node:$c),
1207   (atomic_cmp_swap_32 node:$a, node:$b, node:$c)>;
1208 def atomic_cmp_swap_32_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b, node:$c),
1209   (atomic_cmp_swap_32 node:$a, node:$b, node:$c)>;
1210 def atomic_cmp_swap_64_g: ATOMIC_GLOBAL_CHK<(ops node:$a, node:$b, node:$c),
1211   (atomic_cmp_swap_64 node:$a, node:$b, node:$c)>;
1212 def atomic_cmp_swap_64_s: ATOMIC_SHARED_CHK<(ops node:$a, node:$b, node:$c),
1213   (atomic_cmp_swap_64 node:$a, node:$b, node:$c)>;
1214 def atomic_cmp_swap_64_gen: ATOMIC_GENERIC_CHK<(ops node:$a, node:$b, node:$c),
1215   (atomic_cmp_swap_64 node:$a, node:$b, node:$c)>;
1216
1217 defm INT_PTX_ATOM_CAS_G_32 : F_ATOMIC_3<Int32Regs, ".global", ".b32", ".cas",
1218   atomic_cmp_swap_32_g, i32imm, hasAtomRedG32>;
1219 defm INT_PTX_ATOM_CAS_S_32 : F_ATOMIC_3<Int32Regs, ".shared", ".b32", ".cas",
1220   atomic_cmp_swap_32_s, i32imm, hasAtomRedS32>;
1221 defm INT_PTX_ATOM_CAS_GEN_32 : F_ATOMIC_3<Int32Regs, "", ".b32", ".cas",
1222   atomic_cmp_swap_32_gen, i32imm, hasAtomRedGen32>;
1223 defm INT_PTX_ATOM_CAS_GEN_32_USE_G : F_ATOMIC_3<Int32Regs, ".global", ".b32",
1224   ".cas", atomic_cmp_swap_32_gen, i32imm, useAtomRedG32forGen32>;
1225 defm INT_PTX_ATOM_CAS_G_64 : F_ATOMIC_3<Int64Regs, ".global", ".b64", ".cas",
1226   atomic_cmp_swap_64_g, i64imm, hasAtomRedG64>;
1227 defm INT_PTX_ATOM_CAS_S_64 : F_ATOMIC_3<Int64Regs, ".shared", ".b64", ".cas",
1228   atomic_cmp_swap_64_s, i64imm, hasAtomRedS64>;
1229 defm INT_PTX_ATOM_CAS_GEN_64 : F_ATOMIC_3<Int64Regs, "", ".b64", ".cas",
1230   atomic_cmp_swap_64_gen, i64imm, hasAtomRedGen64>;
1231 defm INT_PTX_ATOM_CAS_GEN_64_USE_G : F_ATOMIC_3<Int64Regs, ".global", ".b64",
1232   ".cas", atomic_cmp_swap_64_gen, i64imm, useAtomRedG64forGen64>;
1233
1234
1235 //-----------------------------------
1236 // Read Special Registers
1237 //-----------------------------------
1238 class F_SREG<string OpStr, NVPTXRegClass regclassOut, Intrinsic IntOp> :
1239       NVPTXInst<(outs regclassOut:$dst), (ins),
1240                OpStr,
1241          [(set regclassOut:$dst, (IntOp))]>;
1242
1243 def INT_PTX_SREG_TID_X : F_SREG<"mov.u32 \t$dst, %tid.x;", Int32Regs,
1244   int_nvvm_read_ptx_sreg_tid_x>;
1245 def INT_PTX_SREG_TID_Y : F_SREG<"mov.u32 \t$dst, %tid.y;", Int32Regs,
1246   int_nvvm_read_ptx_sreg_tid_y>;
1247 def INT_PTX_SREG_TID_Z : F_SREG<"mov.u32 \t$dst, %tid.z;", Int32Regs,
1248   int_nvvm_read_ptx_sreg_tid_z>;
1249
1250 def INT_PTX_SREG_NTID_X : F_SREG<"mov.u32 \t$dst, %ntid.x;", Int32Regs,
1251   int_nvvm_read_ptx_sreg_ntid_x>;
1252 def INT_PTX_SREG_NTID_Y : F_SREG<"mov.u32 \t$dst, %ntid.y;", Int32Regs,
1253   int_nvvm_read_ptx_sreg_ntid_y>;
1254 def INT_PTX_SREG_NTID_Z : F_SREG<"mov.u32 \t$dst, %ntid.z;", Int32Regs,
1255   int_nvvm_read_ptx_sreg_ntid_z>;
1256
1257 def INT_PTX_SREG_CTAID_X : F_SREG<"mov.u32 \t$dst, %ctaid.x;", Int32Regs,
1258   int_nvvm_read_ptx_sreg_ctaid_x>;
1259 def INT_PTX_SREG_CTAID_Y : F_SREG<"mov.u32 \t$dst, %ctaid.y;", Int32Regs,
1260   int_nvvm_read_ptx_sreg_ctaid_y>;
1261 def INT_PTX_SREG_CTAID_Z : F_SREG<"mov.u32 \t$dst, %ctaid.z;", Int32Regs,
1262   int_nvvm_read_ptx_sreg_ctaid_z>;
1263
1264 def INT_PTX_SREG_NCTAID_X : F_SREG<"mov.u32 \t$dst, %nctaid.x;", Int32Regs,
1265   int_nvvm_read_ptx_sreg_nctaid_x>;
1266 def INT_PTX_SREG_NCTAID_Y : F_SREG<"mov.u32 \t$dst, %nctaid.y;", Int32Regs,
1267   int_nvvm_read_ptx_sreg_nctaid_y>;
1268 def INT_PTX_SREG_NCTAID_Z : F_SREG<"mov.u32 \t$dst, %nctaid.z;", Int32Regs,
1269   int_nvvm_read_ptx_sreg_nctaid_z>;
1270
1271 def INT_PTX_SREG_WARPSIZE : F_SREG<"mov.u32 \t$dst, WARP_SZ;", Int32Regs,
1272   int_nvvm_read_ptx_sreg_warpsize>;
1273
1274
1275 //-----------------------------------
1276 // Support for ldu on sm_20 or later
1277 //-----------------------------------
1278
1279 def ldu_i8 : PatFrag<(ops node:$ptr), (int_nvvm_ldu_global_i node:$ptr), [{
1280   MemIntrinsicSDNode *M = cast<MemIntrinsicSDNode>(N);
1281   return M->getMemoryVT() == MVT::i8;
1282 }]>;
1283
1284 // Scalar
1285 // @TODO: Revisit this, Changed imemAny to imem
1286 multiclass LDU_G<string TyStr, NVPTXRegClass regclass, Intrinsic IntOp> {
1287   def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1288                !strconcat("ldu.global.", TyStr),
1289          [(set regclass:$result, (IntOp Int32Regs:$src))]>, Requires<[hasLDU]>;
1290   def areg64: NVPTXInst<(outs regclass:$result), (ins Int64Regs:$src),
1291                !strconcat("ldu.global.", TyStr),
1292          [(set regclass:$result, (IntOp Int64Regs:$src))]>, Requires<[hasLDU]>;
1293  def avar:  NVPTXInst<(outs regclass:$result), (ins imem:$src),
1294                !strconcat("ldu.global.", TyStr),
1295                 [(set regclass:$result, (IntOp (Wrapper tglobaladdr:$src)))]>,
1296                 Requires<[hasLDU]>;
1297  def ari :  NVPTXInst<(outs regclass:$result), (ins MEMri:$src),
1298                !strconcat("ldu.global.", TyStr),
1299          [(set regclass:$result, (IntOp ADDRri:$src))]>, Requires<[hasLDU]>;
1300  def ari64 :  NVPTXInst<(outs regclass:$result), (ins MEMri64:$src),
1301                !strconcat("ldu.global.", TyStr),
1302          [(set regclass:$result, (IntOp ADDRri64:$src))]>, Requires<[hasLDU]>;
1303 }
1304
1305 multiclass LDU_G_NOINTRIN<string TyStr, NVPTXRegClass regclass, PatFrag IntOp> {
1306   def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1307                !strconcat("ldu.global.", TyStr),
1308          [(set regclass:$result, (IntOp Int32Regs:$src))]>, Requires<[hasLDU]>;
1309   def areg64: NVPTXInst<(outs regclass:$result), (ins Int64Regs:$src),
1310                !strconcat("ldu.global.", TyStr),
1311          [(set regclass:$result, (IntOp Int64Regs:$src))]>, Requires<[hasLDU]>;
1312  def avar:  NVPTXInst<(outs regclass:$result), (ins imem:$src),
1313                !strconcat("ldu.global.", TyStr),
1314          [(set regclass:$result, (IntOp (Wrapper tglobaladdr:$src)))]>,
1315          Requires<[hasLDU]>;
1316  def ari :  NVPTXInst<(outs regclass:$result), (ins MEMri:$src),
1317                !strconcat("ldu.global.", TyStr),
1318          [(set regclass:$result, (IntOp ADDRri:$src))]>, Requires<[hasLDU]>;
1319  def ari64 :  NVPTXInst<(outs regclass:$result), (ins MEMri64:$src),
1320                !strconcat("ldu.global.", TyStr),
1321          [(set regclass:$result, (IntOp ADDRri64:$src))]>, Requires<[hasLDU]>;
1322 }
1323
1324 defm INT_PTX_LDU_GLOBAL_i8  : LDU_G_NOINTRIN<"u8 \t$result, [$src];", Int16Regs,
1325                                              ldu_i8>;
1326 defm INT_PTX_LDU_GLOBAL_i16 : LDU_G<"u16 \t$result, [$src];", Int16Regs,
1327 int_nvvm_ldu_global_i>;
1328 defm INT_PTX_LDU_GLOBAL_i32 : LDU_G<"u32 \t$result, [$src];", Int32Regs,
1329 int_nvvm_ldu_global_i>;
1330 defm INT_PTX_LDU_GLOBAL_i64 : LDU_G<"u64 \t$result, [$src];", Int64Regs,
1331 int_nvvm_ldu_global_i>;
1332 defm INT_PTX_LDU_GLOBAL_f32 : LDU_G<"f32 \t$result, [$src];", Float32Regs,
1333 int_nvvm_ldu_global_f>;
1334 defm INT_PTX_LDU_GLOBAL_f64 : LDU_G<"f64 \t$result, [$src];", Float64Regs,
1335 int_nvvm_ldu_global_f>;
1336 defm INT_PTX_LDU_GLOBAL_p32 : LDU_G<"u32 \t$result, [$src];", Int32Regs,
1337 int_nvvm_ldu_global_p>;
1338 defm INT_PTX_LDU_GLOBAL_p64 : LDU_G<"u64 \t$result, [$src];", Int64Regs,
1339 int_nvvm_ldu_global_p>;
1340
1341 // vector
1342
1343 // Elementized vector ldu
1344 multiclass VLDU_G_ELE_V2<string TyStr, NVPTXRegClass regclass> {
1345  def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1346                      (ins Int32Regs:$src),
1347                      !strconcat("ldu.global.", TyStr), []>;
1348  def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1349                      (ins Int64Regs:$src),
1350                      !strconcat("ldu.global.", TyStr), []>;
1351  def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1352                      (ins MEMri:$src),
1353                      !strconcat("ldu.global.", TyStr), []>;
1354  def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1355                      (ins MEMri64:$src),
1356                      !strconcat("ldu.global.", TyStr), []>;
1357  def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1358                      (ins imemAny:$src),
1359                      !strconcat("ldu.global.", TyStr), []>;
1360 }
1361
1362 multiclass VLDU_G_ELE_V4<string TyStr, NVPTXRegClass regclass> {
1363  def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1364                             regclass:$dst4), (ins Int32Regs:$src),
1365                !strconcat("ldu.global.", TyStr), []>;
1366  def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1367                             regclass:$dst4), (ins Int64Regs:$src),
1368                !strconcat("ldu.global.", TyStr), []>;
1369  def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1370                             regclass:$dst4), (ins MEMri:$src),
1371                !strconcat("ldu.global.", TyStr), []>;
1372  def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1373                             regclass:$dst4), (ins MEMri64:$src),
1374                !strconcat("ldu.global.", TyStr), []>;
1375  def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1376                             regclass:$dst4), (ins imemAny:$src),
1377                !strconcat("ldu.global.", TyStr), []>;
1378 }
1379
1380 defm INT_PTX_LDU_G_v2i8_ELE
1381   : VLDU_G_ELE_V2<"v2.u8 \t{{$dst1, $dst2}}, [$src];",  Int16Regs>;
1382 defm INT_PTX_LDU_G_v2i16_ELE
1383   : VLDU_G_ELE_V2<"v2.u16 \t{{$dst1, $dst2}}, [$src];", Int16Regs>;
1384 defm INT_PTX_LDU_G_v2i32_ELE
1385   : VLDU_G_ELE_V2<"v2.u32 \t{{$dst1, $dst2}}, [$src];", Int32Regs>;
1386 defm INT_PTX_LDU_G_v2f32_ELE
1387   : VLDU_G_ELE_V2<"v2.f32 \t{{$dst1, $dst2}}, [$src];", Float32Regs>;
1388 defm INT_PTX_LDU_G_v2i64_ELE
1389   : VLDU_G_ELE_V2<"v2.u64 \t{{$dst1, $dst2}}, [$src];", Int64Regs>;
1390 defm INT_PTX_LDU_G_v2f64_ELE
1391   : VLDU_G_ELE_V2<"v2.f64 \t{{$dst1, $dst2}}, [$src];", Float64Regs>;
1392 defm INT_PTX_LDU_G_v4i8_ELE
1393   : VLDU_G_ELE_V4<"v4.u8 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Int16Regs>;
1394 defm INT_PTX_LDU_G_v4i16_ELE
1395   : VLDU_G_ELE_V4<"v4.u16 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
1396     Int16Regs>;
1397 defm INT_PTX_LDU_G_v4i32_ELE
1398   : VLDU_G_ELE_V4<"v4.u32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
1399     Int32Regs>;
1400 defm INT_PTX_LDU_G_v4f32_ELE
1401   : VLDU_G_ELE_V4<"v4.f32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];",
1402     Float32Regs>;
1403
1404
1405 //-----------------------------------
1406 // Support for ldg on sm_35 or later
1407 //-----------------------------------
1408
1409 def ldg_i8 : PatFrag<(ops node:$ptr), (int_nvvm_ldg_global_i node:$ptr), [{
1410   MemIntrinsicSDNode *M = cast<MemIntrinsicSDNode>(N);
1411   return M->getMemoryVT() == MVT::i8;
1412 }]>;
1413
1414 multiclass LDG_G<string TyStr, NVPTXRegClass regclass, Intrinsic IntOp> {
1415   def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1416                !strconcat("ld.global.nc.", TyStr),
1417          [(set regclass:$result, (IntOp Int32Regs:$src))]>, Requires<[hasLDG]>;
1418   def areg64: NVPTXInst<(outs regclass:$result), (ins Int64Regs:$src),
1419                !strconcat("ld.global.nc.", TyStr),
1420          [(set regclass:$result, (IntOp Int64Regs:$src))]>, Requires<[hasLDG]>;
1421  def avar:  NVPTXInst<(outs regclass:$result), (ins imem:$src),
1422                !strconcat("ld.global.nc.", TyStr),
1423          [(set regclass:$result, (IntOp (Wrapper tglobaladdr:$src)))]>,
1424          Requires<[hasLDG]>;
1425  def ari :  NVPTXInst<(outs regclass:$result), (ins MEMri:$src),
1426                !strconcat("ld.global.nc.", TyStr),
1427          [(set regclass:$result, (IntOp ADDRri:$src))]>, Requires<[hasLDG]>;
1428  def ari64 :  NVPTXInst<(outs regclass:$result), (ins MEMri64:$src),
1429                !strconcat("ld.global.nc.", TyStr),
1430          [(set regclass:$result, (IntOp ADDRri64:$src))]>, Requires<[hasLDG]>;
1431 }
1432
1433 multiclass LDG_G_NOINTRIN<string TyStr, NVPTXRegClass regclass, PatFrag IntOp> {
1434   def areg: NVPTXInst<(outs regclass:$result), (ins Int32Regs:$src),
1435                !strconcat("ld.global.nc.", TyStr),
1436          [(set regclass:$result, (IntOp Int32Regs:$src))]>, Requires<[hasLDG]>;
1437   def areg64: NVPTXInst<(outs regclass:$result), (ins Int64Regs:$src),
1438                !strconcat("ld.global.nc.", TyStr),
1439          [(set regclass:$result, (IntOp Int64Regs:$src))]>, Requires<[hasLDG]>;
1440  def avar:  NVPTXInst<(outs regclass:$result), (ins imem:$src),
1441                !strconcat("ld.global.nc.", TyStr),
1442          [(set regclass:$result, (IntOp (Wrapper tglobaladdr:$src)))]>,
1443         Requires<[hasLDG]>;
1444  def ari :  NVPTXInst<(outs regclass:$result), (ins MEMri:$src),
1445                !strconcat("ld.global.nc.", TyStr),
1446          [(set regclass:$result, (IntOp ADDRri:$src))]>, Requires<[hasLDG]>;
1447  def ari64 :  NVPTXInst<(outs regclass:$result), (ins MEMri64:$src),
1448                !strconcat("ld.global.nc.", TyStr),
1449          [(set regclass:$result, (IntOp ADDRri64:$src))]>, Requires<[hasLDG]>;
1450 }
1451
1452 defm INT_PTX_LDG_GLOBAL_i8
1453   : LDG_G_NOINTRIN<"u8 \t$result, [$src];",  Int16Regs, ldg_i8>;
1454 defm INT_PTX_LDG_GLOBAL_i16
1455   : LDG_G<"u16 \t$result, [$src];", Int16Regs,   int_nvvm_ldg_global_i>;
1456 defm INT_PTX_LDG_GLOBAL_i32
1457   : LDG_G<"u32 \t$result, [$src];", Int32Regs,   int_nvvm_ldg_global_i>;
1458 defm INT_PTX_LDG_GLOBAL_i64
1459   : LDG_G<"u64 \t$result, [$src];", Int64Regs,   int_nvvm_ldg_global_i>;
1460 defm INT_PTX_LDG_GLOBAL_f32
1461   : LDG_G<"f32 \t$result, [$src];", Float32Regs, int_nvvm_ldg_global_f>;
1462 defm INT_PTX_LDG_GLOBAL_f64
1463   : LDG_G<"f64 \t$result, [$src];", Float64Regs, int_nvvm_ldg_global_f>;
1464 defm INT_PTX_LDG_GLOBAL_p32
1465   : LDG_G<"u32 \t$result, [$src];", Int32Regs,   int_nvvm_ldg_global_p>;
1466 defm INT_PTX_LDG_GLOBAL_p64
1467   : LDG_G<"u64 \t$result, [$src];", Int64Regs,   int_nvvm_ldg_global_p>;
1468
1469 // vector
1470
1471 // Elementized vector ldg
1472 multiclass VLDG_G_ELE_V2<string TyStr, NVPTXRegClass regclass> {
1473  def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1474                      (ins Int32Regs:$src),
1475                      !strconcat("ld.global.nc.", TyStr), []>;
1476  def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1477                      (ins Int64Regs:$src),
1478                      !strconcat("ld.global.nc.", TyStr), []>;
1479  def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1480                      (ins MEMri:$src),
1481                      !strconcat("ld.global.nc.", TyStr), []>;
1482  def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1483                      (ins MEMri64:$src),
1484                      !strconcat("ld.global.nc.", TyStr), []>;
1485  def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2),
1486                      (ins imemAny:$src),
1487                      !strconcat("ld.global.nc.", TyStr), []>;
1488 }
1489
1490 multiclass VLDG_G_ELE_V4<string TyStr, NVPTXRegClass regclass> {
1491   def _areg32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1492                               regclass:$dst4), (ins Int32Regs:$src),
1493                !strconcat("ld.global.nc.", TyStr), []>;
1494   def _areg64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1495                                regclass:$dst4), (ins Int64Regs:$src),
1496                !strconcat("ld.global.nc.", TyStr), []>;
1497   def _ari32: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1498                               regclass:$dst4), (ins MEMri:$src),
1499                !strconcat("ld.global.nc.", TyStr), []>;
1500   def _ari64: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1501                               regclass:$dst4), (ins MEMri64:$src),
1502                !strconcat("ld.global.nc.", TyStr), []>;
1503   def _avar: NVPTXInst<(outs regclass:$dst1, regclass:$dst2, regclass:$dst3,
1504                              regclass:$dst4), (ins imemAny:$src),
1505                !strconcat("ld.global.nc.", TyStr), []>;
1506 }
1507
1508 // FIXME: 8-bit LDG should be fixed once LDG/LDU nodes are made into proper loads.
1509 defm INT_PTX_LDG_G_v2i8_ELE
1510   : VLDG_G_ELE_V2<"v2.u8 \t{{$dst1, $dst2}}, [$src];",  Int16Regs>;
1511 defm INT_PTX_LDG_G_v2i16_ELE
1512   : VLDG_G_ELE_V2<"v2.u16 \t{{$dst1, $dst2}}, [$src];", Int16Regs>;
1513 defm INT_PTX_LDG_G_v2i32_ELE
1514   : VLDG_G_ELE_V2<"v2.u32 \t{{$dst1, $dst2}}, [$src];", Int32Regs>;
1515 defm INT_PTX_LDG_G_v2f32_ELE
1516   : VLDG_G_ELE_V2<"v2.f32 \t{{$dst1, $dst2}}, [$src];", Float32Regs>;
1517 defm INT_PTX_LDG_G_v2i64_ELE
1518   : VLDG_G_ELE_V2<"v2.u64 \t{{$dst1, $dst2}}, [$src];", Int64Regs>;
1519 defm INT_PTX_LDG_G_v2f64_ELE
1520   : VLDG_G_ELE_V2<"v2.f64 \t{{$dst1, $dst2}}, [$src];", Float64Regs>;
1521 defm INT_PTX_LDG_G_v4i8_ELE
1522   : VLDG_G_ELE_V4<"v4.u8 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Int16Regs>;
1523 defm INT_PTX_LDG_G_v4i16_ELE
1524   : VLDG_G_ELE_V4<"v4.u16 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Int16Regs>;
1525 defm INT_PTX_LDG_G_v4i32_ELE
1526   : VLDG_G_ELE_V4<"v4.u32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Int32Regs>;
1527 defm INT_PTX_LDG_G_v4f32_ELE
1528   : VLDG_G_ELE_V4<"v4.f32 \t{{$dst1, $dst2, $dst3, $dst4}}, [$src];", Float32Regs>;
1529
1530
1531 multiclass NG_TO_G<string Str, Intrinsic Intrin> {
1532    def _yes : NVPTXInst<(outs Int32Regs:$result), (ins Int32Regs:$src),
1533           !strconcat("cvta.", !strconcat(Str, ".u32 \t$result, $src;")),
1534       [(set Int32Regs:$result, (Intrin Int32Regs:$src))]>,
1535    Requires<[hasGenericLdSt]>;
1536    def _yes_64 : NVPTXInst<(outs Int64Regs:$result), (ins Int64Regs:$src),
1537           !strconcat("cvta.", !strconcat(Str, ".u64 \t$result, $src;")),
1538       [(set Int64Regs:$result, (Intrin Int64Regs:$src))]>,
1539    Requires<[hasGenericLdSt]>;
1540
1541 // @TODO: Are these actually needed?  I believe global addresses will be copied
1542 // to register values anyway.
1543    /*def __addr_yes : NVPTXInst<(outs Int32Regs:$result), (ins imemAny:$src),
1544           !strconcat("cvta.", !strconcat(Str, ".u32 \t$result, $src;")),
1545       [(set Int32Regs:$result, (Intrin (Wrapper tglobaladdr:$src)))]>,
1546       Requires<[hasGenericLdSt]>;
1547    def __addr_yes_64 : NVPTXInst<(outs Int64Regs:$result), (ins imemAny:$src),
1548           !strconcat("cvta.", !strconcat(Str, ".u64 \t$result, $src;")),
1549       [(set Int64Regs:$result, (Intrin (Wrapper tglobaladdr:$src)))]>,
1550       Requires<[hasGenericLdSt]>;*/
1551
1552    def _no : NVPTXInst<(outs Int32Regs:$result), (ins Int32Regs:$src),
1553           "mov.u32 \t$result, $src;",
1554       [(set Int32Regs:$result, (Intrin Int32Regs:$src))]>;
1555    def _no_64 : NVPTXInst<(outs Int64Regs:$result), (ins Int64Regs:$src),
1556           "mov.u64 \t$result, $src;",
1557       [(set Int64Regs:$result, (Intrin Int64Regs:$src))]>;
1558
1559 // @TODO: Are these actually needed?  I believe global addresses will be copied
1560 // to register values anyway.
1561    /*def _addr_no : NVPTXInst<(outs Int32Regs:$result), (ins imem:$src),
1562           "mov.u32 \t$result, $src;",
1563       [(set Int32Regs:$result, (Intrin (Wrapper tglobaladdr:$src)))]>;
1564    def _addr_no_64 : NVPTXInst<(outs Int64Regs:$result), (ins imem:$src),
1565           "mov.u64 \t$result, $src;",
1566       [(set Int64Regs:$result, (Intrin (Wrapper tglobaladdr:$src)))]>;*/
1567 }
1568
1569 multiclass G_TO_NG<string Str, Intrinsic Intrin> {
1570    def _yes : NVPTXInst<(outs Int32Regs:$result), (ins Int32Regs:$src),
1571           !strconcat("cvta.to.", !strconcat(Str, ".u32 \t$result, $src;")),
1572       [(set Int32Regs:$result, (Intrin Int32Regs:$src))]>,
1573    Requires<[hasGenericLdSt]>;
1574    def _yes_64 : NVPTXInst<(outs Int64Regs:$result), (ins Int64Regs:$src),
1575           !strconcat("cvta.to.", !strconcat(Str, ".u64 \t$result, $src;")),
1576       [(set Int64Regs:$result, (Intrin Int64Regs:$src))]>,
1577    Requires<[hasGenericLdSt]>;
1578    def _no : NVPTXInst<(outs Int32Regs:$result), (ins Int32Regs:$src),
1579           "mov.u32 \t$result, $src;",
1580       [(set Int32Regs:$result, (Intrin Int32Regs:$src))]>;
1581    def _no_64 : NVPTXInst<(outs Int64Regs:$result), (ins Int64Regs:$src),
1582           "mov.u64 \t$result, $src;",
1583       [(set Int64Regs:$result, (Intrin Int64Regs:$src))]>;
1584 }
1585
1586 defm cvta_local  : NG_TO_G<"local", int_nvvm_ptr_local_to_gen>;
1587 defm cvta_shared : NG_TO_G<"shared", int_nvvm_ptr_shared_to_gen>;
1588 defm cvta_global : NG_TO_G<"global", int_nvvm_ptr_global_to_gen>;
1589 defm cvta_const  : NG_TO_G<"const", int_nvvm_ptr_constant_to_gen>;
1590
1591 defm cvta_to_local   : G_TO_NG<"local", int_nvvm_ptr_gen_to_local>;
1592 defm cvta_to_shared : G_TO_NG<"shared", int_nvvm_ptr_gen_to_shared>;
1593 defm cvta_to_global : G_TO_NG<"global", int_nvvm_ptr_gen_to_global>;
1594 defm cvta_to_const  : G_TO_NG<"const", int_nvvm_ptr_gen_to_constant>;
1595
1596
1597 // nvvm.ptr.gen.to.param
1598 def nvvm_ptr_gen_to_param : NVPTXInst<(outs Int32Regs:$result),
1599   (ins Int32Regs:$src),
1600                         "mov.u32 \t$result, $src;",
1601                               [(set Int32Regs:$result,
1602                                 (int_nvvm_ptr_gen_to_param Int32Regs:$src))]>;
1603 def nvvm_ptr_gen_to_param_64 : NVPTXInst<(outs Int64Regs:$result),
1604   (ins Int64Regs:$src),
1605                         "mov.u64 \t$result, $src;",
1606                               [(set Int64Regs:$result,
1607                                 (int_nvvm_ptr_gen_to_param Int64Regs:$src))]>;
1608
1609
1610 // nvvm.move intrinsicc
1611 def nvvm_move_i16 : NVPTXInst<(outs Int16Regs:$r), (ins Int16Regs:$s),
1612                              "mov.b16 \t$r, $s;",
1613                              [(set Int16Regs:$r,
1614                                (int_nvvm_move_i16 Int16Regs:$s))]>;
1615 def nvvm_move_i32 : NVPTXInst<(outs Int32Regs:$r), (ins Int32Regs:$s),
1616                              "mov.b32 \t$r, $s;",
1617                              [(set Int32Regs:$r,
1618                                (int_nvvm_move_i32 Int32Regs:$s))]>;
1619 def nvvm_move_i64 : NVPTXInst<(outs Int64Regs:$r), (ins Int64Regs:$s),
1620                              "mov.b64 \t$r, $s;",
1621                              [(set Int64Regs:$r,
1622                                (int_nvvm_move_i64 Int64Regs:$s))]>;
1623 def nvvm_move_float : NVPTXInst<(outs Float32Regs:$r), (ins Float32Regs:$s),
1624                              "mov.f32 \t$r, $s;",
1625                              [(set Float32Regs:$r,
1626                                (int_nvvm_move_float Float32Regs:$s))]>;
1627 def nvvm_move_double : NVPTXInst<(outs Float64Regs:$r), (ins Float64Regs:$s),
1628                              "mov.f64 \t$r, $s;",
1629                              [(set Float64Regs:$r,
1630                                (int_nvvm_move_double Float64Regs:$s))]>;
1631 def nvvm_move_ptr32 : NVPTXInst<(outs Int32Regs:$r), (ins Int32Regs:$s),
1632                              "mov.u32 \t$r, $s;",
1633                              [(set Int32Regs:$r,
1634                                (int_nvvm_move_ptr Int32Regs:$s))]>;
1635 def nvvm_move_ptr64 : NVPTXInst<(outs Int64Regs:$r), (ins Int64Regs:$s),
1636                              "mov.u64 \t$r, $s;",
1637                              [(set Int64Regs:$r,
1638                                (int_nvvm_move_ptr Int64Regs:$s))]>;
1639
1640 // @TODO: Are these actually needed, or will we always just see symbols
1641 // copied to registers first?
1642 /*def nvvm_move_sym32 : NVPTXInst<(outs Int32Regs:$r), (ins imem:$s),
1643                              "mov.u32 \t$r, $s;",
1644                              [(set Int32Regs:$r,
1645                              (int_nvvm_move_ptr texternalsym:$s))]>;
1646 def nvvm_move_sym64 : NVPTXInst<(outs Int64Regs:$r), (ins imem:$s),
1647                              "mov.u64 \t$r, $s;",
1648                              [(set Int64Regs:$r,
1649                              (int_nvvm_move_ptr texternalsym:$s))]>;*/
1650
1651
1652 // MoveParam        %r1, param
1653 // ptr_local_to_gen %r2, %r1
1654 // ptr_gen_to_local %r3, %r2
1655 // ->
1656 // mov %r1, param
1657
1658 // @TODO: Revisit this.  There is a type
1659 // contradiction between iPTRAny and iPTR for the addr defs, so the move_sym
1660 // instructions are not currently defined. However, we can use the ptr
1661 // variants and the asm printer will do the right thing.
1662 def : Pat<(i64 (int_nvvm_ptr_gen_to_local (int_nvvm_ptr_local_to_gen
1663                 (MoveParam texternalsym:$src)))),
1664                (nvvm_move_ptr64  texternalsym:$src)>;
1665 def : Pat<(i32 (int_nvvm_ptr_gen_to_local (int_nvvm_ptr_local_to_gen
1666                 (MoveParam texternalsym:$src)))),
1667                (nvvm_move_ptr32  texternalsym:$src)>;
1668
1669 def texsurf_handles
1670   : NVPTXInst<(outs Int64Regs:$result), (ins imem:$src),
1671               "mov.u64 \t$result, $src;", []>;
1672
1673 //-----------------------------------
1674 // Compiler Error Warn
1675 // - Just ignore them in codegen
1676 //-----------------------------------
1677
1678 def INT_NVVM_COMPILER_WARN_32 : NVPTXInst<(outs), (ins Int32Regs:$a),
1679                 "// llvm.nvvm.compiler.warn()",
1680                 [(int_nvvm_compiler_warn Int32Regs:$a)]>;
1681 def INT_NVVM_COMPILER_WARN_64 : NVPTXInst<(outs), (ins Int64Regs:$a),
1682                 "// llvm.nvvm.compiler.warn()",
1683                 [(int_nvvm_compiler_warn Int64Regs:$a)]>;
1684 def INT_NVVM_COMPILER_ERROR_32 : NVPTXInst<(outs), (ins Int32Regs:$a),
1685                 "// llvm.nvvm.compiler.error()",
1686                 [(int_nvvm_compiler_error Int32Regs:$a)]>;
1687 def INT_NVVM_COMPILER_ERROR_64 : NVPTXInst<(outs), (ins Int64Regs:$a),
1688                 "// llvm.nvvm.compiler.error()",
1689                 [(int_nvvm_compiler_error Int64Regs:$a)]>;
1690
1691
1692 //-----------------------------------
1693 // Texture Intrinsics
1694 //-----------------------------------
1695
1696 // NOTE: For Fermi support, any new texture/surface/sampler intrinsics must be
1697 // also defined in NVPTXReplaceImageHandles.cpp
1698
1699
1700 // Texture fetch instructions using handles
1701 def TEX_1D_F32_I32
1702   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1703                     Float32Regs:$b, Float32Regs:$a),
1704               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$x),
1705               "tex.1d.v4.f32.s32\t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$x\\}];",
1706               []>;
1707 def TEX_1D_F32_F32
1708   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1709                     Float32Regs:$b, Float32Regs:$a),
1710               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x),
1711               "tex.1d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$x\\}];",
1712               []>;
1713 def TEX_1D_F32_F32_LEVEL
1714   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1715                     Float32Regs:$b, Float32Regs:$a),
1716               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$lod),
1717               "tex.level.1d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1718               "[$t, $s, \\{$x\\}], $lod;",
1719               []>;
1720 def TEX_1D_F32_F32_GRAD
1721   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1722                     Float32Regs:$b, Float32Regs:$a),
1723               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x,
1724                    Float32Regs:$gradx, Float32Regs:$grady),
1725               "tex.grad.1d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1726               "[$t, $s, \\{$x\\}], \\{$gradx\\}, \\{$grady\\};",
1727               []>;
1728 def TEX_1D_I32_I32
1729   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1730                     Int32Regs:$b, Int32Regs:$a),
1731               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$x),
1732               "tex.1d.v4.s32.s32\t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$x\\}];",
1733               []>;
1734 def TEX_1D_I32_F32
1735   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1736                     Int32Regs:$b, Int32Regs:$a),
1737               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x),
1738               "tex.1d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$x\\}];",
1739               []>;
1740 def TEX_1D_I32_F32_LEVEL
1741   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1742                     Int32Regs:$b, Int32Regs:$a),
1743               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x,
1744                    Float32Regs:$lod),
1745               "tex.level.1d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1746               "[$t, $s, \\{$x\\}], $lod;",
1747               []>;
1748 def TEX_1D_I32_F32_GRAD
1749   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1750                     Int32Regs:$b, Int32Regs:$a),
1751               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x,
1752                    Float32Regs:$gradx, Float32Regs:$grady),
1753               "tex.grad.1d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1754               "[$t, $s, \\{$x\\}], \\{$gradx\\}, \\{$grady\\};",
1755               []>;
1756
1757 def TEX_1D_ARRAY_F32_I32
1758   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1759                     Float32Regs:$b, Float32Regs:$a),
1760               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
1761               "tex.a1d.v4.f32.s32\t\\{$r, $g, $b, $a\\}, "
1762               "[$t, $s, \\{$l, $x\\}];",
1763               []>;
1764 def TEX_1D_ARRAY_F32_F32
1765   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1766                     Float32Regs:$b, Float32Regs:$a),
1767               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x),
1768               "tex.a1d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1769               "[$t, $s, \\{$l, $x\\}];",
1770               []>;
1771 def TEX_1D_ARRAY_F32_F32_LEVEL
1772   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1773                     Float32Regs:$b, Float32Regs:$a),
1774               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1775                    Float32Regs:$lod),
1776               "tex.level.a1d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1777               "[$t, $s, \\{$l, $x\\}], $lod;",
1778               []>;
1779 def TEX_1D_ARRAY_F32_F32_GRAD
1780   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1781                     Float32Regs:$b, Float32Regs:$a),
1782               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1783                    Float32Regs:$gradx, Float32Regs:$grady),
1784               "tex.grad.a1d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1785               "[$t, $s, \\{$l, $x\\}], \\{$gradx\\}, \\{$grady\\};",
1786               []>;
1787 def TEX_1D_ARRAY_I32_I32
1788   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1789                     Int32Regs:$b, Int32Regs:$a),
1790               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
1791               "tex.a1d.v4.s32.s32\t\\{$r, $g, $b, $a\\}, "
1792               "[$t, $s, \\{$l, $x\\}];",
1793               []>;
1794 def TEX_1D_ARRAY_I32_F32
1795   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1796                     Int32Regs:$b, Int32Regs:$a),
1797               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x),
1798               "tex.a1d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1799               "[$t, $s, \\{$l, $x\\}];",
1800               []>;
1801 def TEX_1D_ARRAY_I32_F32_LEVEL
1802   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1803                     Int32Regs:$b, Int32Regs:$a),
1804               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1805                    Float32Regs:$lod),
1806               "tex.level.a1d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1807               "[$t, $s, \\{$l, $x\\}], $lod;",
1808               []>;
1809 def TEX_1D_ARRAY_I32_F32_GRAD
1810   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1811                     Int32Regs:$b, Int32Regs:$a),
1812               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1813                    Float32Regs:$gradx, Float32Regs:$grady),
1814               "tex.grad.a1d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1815               "[$t, $s, \\{$l, $x\\}], \\{$gradx\\}, \\{$grady\\};",
1816               []>;
1817
1818 def TEX_2D_F32_I32
1819   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1820                     Float32Regs:$b, Float32Regs:$a),
1821               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
1822               "tex.2d.v4.f32.s32\t\\{$r, $g, $b, $a\\}, "
1823               "[$t, $s, \\{$x, $y\\}];",
1824               []>;
1825 def TEX_2D_F32_F32
1826   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1827                     Float32Regs:$b, Float32Regs:$a),
1828               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y),
1829               "tex.2d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1830               "[$t, $s, \\{$x, $y\\}];",
1831               []>;
1832 def TEX_2D_F32_F32_LEVEL
1833   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1834                     Float32Regs:$b, Float32Regs:$a),
1835               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
1836                    Float32Regs:$lod),
1837               "tex.level.2d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1838               "[$t, $s, \\{$x, $y\\}], $lod;",
1839               []>;
1840 def TEX_2D_F32_F32_GRAD
1841   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1842                     Float32Regs:$b, Float32Regs:$a),
1843               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
1844                    Float32Regs:$gradx0, Float32Regs:$gradx1,
1845                    Float32Regs:$grady0, Float32Regs:$grady1),
1846               "tex.grad.2d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1847               "[$t, $s, \\{$x, $y\\}], \\{$gradx0, $gradx1\\}, "
1848               "\\{$grady0, $grady1\\};",
1849               []>;
1850 def TEX_2D_I32_I32
1851   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1852                     Int32Regs:$b, Int32Regs:$a),
1853               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
1854               "tex.2d.v4.s32.s32\t\\{$r, $g, $b, $a\\}, "
1855               "[$t, $s, \\{$x, $y\\}];",
1856               []>;
1857 def TEX_2D_I32_F32
1858   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1859                     Int32Regs:$b, Int32Regs:$a),
1860               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y),
1861               "tex.2d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1862               "[$t, $s, \\{$x, $y\\}];",
1863               []>;
1864 def TEX_2D_I32_F32_LEVEL
1865   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1866                     Int32Regs:$b, Int32Regs:$a),
1867               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
1868                    Float32Regs:$lod),
1869               "tex.level.2d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1870               "[$t, $s, \\{$x, $y\\}], $lod;",
1871               []>;
1872 def TEX_2D_I32_F32_GRAD
1873   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1874                     Int32Regs:$b, Int32Regs:$a),
1875               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
1876                    Float32Regs:$gradx0, Float32Regs:$gradx1,
1877                    Float32Regs:$grady0, Float32Regs:$grady1),
1878               "tex.grad.2d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1879               "[$t, $s, \\{$x, $y\\}], \\{$gradx0, $gradx1\\}, "
1880               "\\{$grady0, $grady1\\};",
1881               []>;
1882
1883 def TEX_2D_ARRAY_F32_I32
1884   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1885                     Float32Regs:$b, Float32Regs:$a),
1886               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
1887                    Int32Regs:$y),
1888               "tex.a2d.v4.f32.s32\t\\{$r, $g, $b, $a\\}, "
1889               "[$t, $s, \\{$l, $x, $y, $y\\}];",
1890               []>;
1891 def TEX_2D_ARRAY_F32_F32
1892   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1893                     Float32Regs:$b, Float32Regs:$a),
1894               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1895                    Float32Regs:$y),
1896               "tex.a2d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1897               "[$t, $s, \\{$l, $x, $y, $y\\}];",
1898               []>;
1899 def TEX_2D_ARRAY_F32_F32_LEVEL
1900   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1901                     Float32Regs:$b, Float32Regs:$a),
1902               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1903                    Float32Regs:$y, Float32Regs:$lod),
1904               "tex.level.a2d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1905               "[$t, $s, \\{$l, $x, $y, $y\\}], $lod;",
1906               []>;
1907 def TEX_2D_ARRAY_F32_F32_GRAD
1908   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1909                     Float32Regs:$b, Float32Regs:$a),
1910               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1911                    Float32Regs:$y, Float32Regs:$gradx0, Float32Regs:$gradx1,
1912                    Float32Regs:$grady0, Float32Regs:$grady1),
1913               "tex.grad.a2d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1914               "[$t, $s, \\{$l, $x, $y, $y\\}], \\{$gradx0, $gradx1\\}, "
1915               "\\{$grady0, $grady1\\};",
1916               []>;
1917 def TEX_2D_ARRAY_I32_I32
1918   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1919                     Int32Regs:$b, Int32Regs:$a),
1920               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
1921                    Int32Regs:$y),
1922               "tex.a2d.v4.s32.s32\t\\{$r, $g, $b, $a\\}, "
1923               "[$t, $s, \\{$l, $x, $y, $y\\}];",
1924               []>;
1925 def TEX_2D_ARRAY_I32_F32
1926   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1927                     Int32Regs:$b, Int32Regs:$a),
1928               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1929                    Float32Regs:$y),
1930               "tex.a2d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1931               "[$t, $s, \\{$l, $x, $y, $y\\}];",
1932               []>;
1933 def TEX_2D_ARRAY_I32_F32_LEVEL
1934   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1935                     Int32Regs:$b, Int32Regs:$a),
1936               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1937                    Float32Regs:$y, Float32Regs:$lod),
1938               "tex.level.a2d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1939               "[$t, $s, \\{$l, $x, $y, $y\\}], $lod;",
1940               []>;
1941 def TEX_2D_ARRAY_I32_F32_GRAD
1942   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1943                     Int32Regs:$b, Int32Regs:$a),
1944               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$l, Float32Regs:$x,
1945                    Float32Regs:$y,
1946                    Float32Regs:$gradx0, Float32Regs:$gradx1,
1947                    Float32Regs:$grady0, Float32Regs:$grady1),
1948               "tex.grad.a2d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
1949               "[$t, $s, \\{$l, $x, $y, $y\\}], \\{$gradx0, $gradx1\\}, "
1950               "\\{$grady0, $grady1\\};",
1951               []>;
1952
1953 def TEX_3D_F32_I32
1954   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1955                     Float32Regs:$b, Float32Regs:$a),
1956               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
1957                    Int32Regs:$z),
1958               "tex.3d.v4.f32.s32\t\\{$r, $g, $b, $a\\}, "
1959               "[$t, $s, \\{$x, $y, $z, $z\\}];",
1960               []>;
1961 def TEX_3D_F32_F32
1962   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1963                     Float32Regs:$b, Float32Regs:$a),
1964               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
1965                    Float32Regs:$z),
1966               "tex.3d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1967               "[$t, $s, \\{$x, $y, $z, $z\\}];",
1968               []>;
1969 def TEX_3D_F32_F32_LEVEL
1970   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1971                     Float32Regs:$b, Float32Regs:$a),
1972               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
1973                    Float32Regs:$z, Float32Regs:$lod),
1974               "tex.level.3d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1975               "[$t, $s, \\{$x, $y, $z, $z\\}], $lod;",
1976               []>;
1977 def TEX_3D_F32_F32_GRAD
1978   : NVPTXInst<(outs Float32Regs:$r, Float32Regs:$g,
1979                     Float32Regs:$b, Float32Regs:$a),
1980               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
1981                    Float32Regs:$z,
1982                    Float32Regs:$gradx0, Float32Regs:$gradx1,
1983                    Float32Regs:$gradx2, Float32Regs:$grady0,
1984                    Float32Regs:$grady1, Float32Regs:$grady2),
1985               "tex.grad.3d.v4.f32.f32\t\\{$r, $g, $b, $a\\}, "
1986               "[$t, $s, \\{$x, $y, $z, $z\\}], "
1987               "\\{$gradx0, $gradx1, $gradx2, $gradx2\\}, "
1988               "\\{$grady0, $grady1, $grady2, $grady2\\};",
1989               []>;
1990 def TEX_3D_I32_I32
1991   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
1992                     Int32Regs:$b, Int32Regs:$a),
1993               (ins Int64Regs:$t, Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
1994                    Int32Regs:$z),
1995               "tex.3d.v4.s32.s32\t\\{$r, $g, $b, $a\\}, "
1996               "[$t, $s, \\{$x, $y, $z, $z\\}];",
1997               []>;
1998 def TEX_3D_I32_F32
1999   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
2000                     Int32Regs:$b, Int32Regs:$a),
2001               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
2002                    Float32Regs:$z),
2003               "tex.3d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
2004               "[$t, $s, \\{$x, $y, $z, $z\\}];",
2005               []>;
2006 def TEX_3D_I32_F32_LEVEL
2007   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
2008                     Int32Regs:$b, Int32Regs:$a),
2009               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
2010                    Float32Regs:$z, Float32Regs:$lod),
2011               "tex.level.3d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
2012               "[$t, $s, \\{$x, $y, $z, $z\\}], $lod;",
2013               []>;
2014 def TEX_3D_I32_F32_GRAD
2015   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g,
2016                     Int32Regs:$b, Int32Regs:$a),
2017               (ins Int64Regs:$t, Int64Regs:$s, Float32Regs:$x, Float32Regs:$y,
2018                    Float32Regs:$z,
2019                    Float32Regs:$gradx0, Float32Regs:$gradx1,
2020                    Float32Regs:$gradx2, Float32Regs:$grady0,
2021                    Float32Regs:$grady1, Float32Regs:$grady2),
2022               "tex.grad.3d.v4.s32.f32\t\\{$r, $g, $b, $a\\}, "
2023               "[$t, $s, \\{$x, $y, $z, $z\\}], "
2024               "\\{$gradx0, $gradx1, $gradx2, $gradx2\\}, "
2025               "\\{$grady0, $grady1, $grady2, $grady2\\};",
2026               []>;
2027
2028
2029 // Surface load instructions
2030 def SULD_1D_I8_TRAP
2031   : NVPTXInst<(outs Int16Regs:$r),
2032               (ins Int64Regs:$s, Int32Regs:$x),
2033               "suld.b.1d.b8.trap \\{$r\\}, [$s, \\{$x\\}];",
2034               []>;
2035 def SULD_1D_I16_TRAP
2036   : NVPTXInst<(outs Int16Regs:$r),
2037               (ins Int64Regs:$s, Int32Regs:$x),
2038               "suld.b.1d.b16.trap \\{$r\\}, [$s, \\{$x\\}];",
2039               []>;
2040 def SULD_1D_I32_TRAP
2041   : NVPTXInst<(outs Int32Regs:$r),
2042               (ins Int64Regs:$s, Int32Regs:$x),
2043               "suld.b.1d.b32.trap \\{$r\\}, [$s, \\{$x\\}];",
2044               []>;
2045 def SULD_1D_V2I8_TRAP
2046   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2047               (ins Int64Regs:$s, Int32Regs:$x),
2048               "suld.b.1d.v2.b8.trap \\{$r, $g\\}, [$s, \\{$x\\}];",
2049               []>;
2050 def SULD_1D_V2I16_TRAP
2051   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2052               (ins Int64Regs:$s, Int32Regs:$x),
2053               "suld.b.1d.v2.b16.trap \\{$r, $g\\}, [$s, \\{$x\\}];",
2054               []>;
2055 def SULD_1D_V2I32_TRAP
2056   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g),
2057               (ins Int64Regs:$s, Int32Regs:$x),
2058               "suld.b.1d.v2.b32.trap \\{$r, $g\\}, [$s, \\{$x\\}];",
2059               []>;
2060 def SULD_1D_V4I8_TRAP
2061   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2062               (ins Int64Regs:$s, Int32Regs:$x),
2063               "suld.b.1d.v4.b8.trap \\{$r, $g, $b, $a\\}, [$s, \\{$x\\}];",
2064               []>;
2065 def SULD_1D_V4I16_TRAP
2066   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2067               (ins Int64Regs:$s, Int32Regs:$x),
2068               "suld.b.1d.v4.b16.trap \\{$r, $g, $b, $a\\}, [$s, \\{$x\\}];",
2069               []>;
2070 def SULD_1D_V4I32_TRAP
2071   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2072               (ins Int64Regs:$s, Int32Regs:$x),
2073               "suld.b.1d.v4.b32.trap \\{$r, $g, $b, $a\\}, [$s, \\{$x\\}];",
2074               []>;
2075
2076 def SULD_1D_ARRAY_I8_TRAP
2077   : NVPTXInst<(outs Int16Regs:$r),
2078               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2079               "suld.b.a1d.b8.trap \\{$r\\}, [$s, \\{$l, $x\\}];",
2080               []>;
2081 def SULD_1D_ARRAY_I16_TRAP
2082   : NVPTXInst<(outs Int16Regs:$r),
2083               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2084               "suld.b.a1d.b16.trap \\{$r\\}, [$s, \\{$l, $x\\}];",
2085               []>;
2086 def SULD_1D_ARRAY_I32_TRAP
2087   : NVPTXInst<(outs Int32Regs:$r),
2088               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2089               "suld.b.a1d.b32.trap \\{$r\\}, [$s, \\{$l, $x\\}];",
2090               []>;
2091 def SULD_1D_ARRAY_V2I8_TRAP
2092   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2093               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2094               "suld.b.a1d.v2.b8.trap \\{$r, $g\\}, [$s, \\{$l, $x\\}];",
2095               []>;
2096 def SULD_1D_ARRAY_V2I16_TRAP
2097   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2098               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2099               "suld.b.a1d.v2.b16.trap \\{$r, $g\\}, [$s, \\{$l, $x\\}];",
2100               []>;
2101 def SULD_1D_ARRAY_V2I32_TRAP
2102   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g),
2103               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2104               "suld.b.a1d.v2.b32.trap \\{$r, $g\\}, [$s, \\{$l, $x\\}];",
2105               []>;
2106 def SULD_1D_ARRAY_V4I8_TRAP
2107   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2108               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2109               "suld.b.a1d.v4.b8.trap \\{$r, $g, $b, $a\\}, "
2110               "[$s, \\{$l, $x\\}];",
2111               []>;
2112 def SULD_1D_ARRAY_V4I16_TRAP
2113   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2114               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2115               "suld.b.a1d.v4.b16.trap \\{$r, $g, $b, $a\\}, "
2116               "[$s, \\{$l, $x\\}];",
2117               []>;
2118 def SULD_1D_ARRAY_V4I32_TRAP
2119   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2120               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x),
2121               "suld.b.a1d.v4.b32.trap \\{$r, $g, $b, $a\\}, "
2122               "[$s, \\{$l, $x\\}];",
2123               []>;
2124
2125 def SULD_2D_I8_TRAP
2126   : NVPTXInst<(outs Int16Regs:$r),
2127               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2128               "suld.b.2d.b8.trap \\{$r\\}, [$s, \\{$x, $y\\}];",
2129               []>;
2130 def SULD_2D_I16_TRAP
2131   : NVPTXInst<(outs Int16Regs:$r),
2132               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2133               "suld.b.2d.b16.trap \\{$r\\}, [$s, \\{$x, $y\\}];",
2134               []>;
2135 def SULD_2D_I32_TRAP
2136   : NVPTXInst<(outs Int32Regs:$r),
2137               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2138               "suld.b.2d.b32.trap \\{$r\\}, [$s, \\{$x, $y\\}];",
2139               []>;
2140 def SULD_2D_V2I8_TRAP
2141   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2142               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2143               "suld.b.2d.v2.b8.trap \\{$r, $g\\}, [$s, \\{$x, $y\\}];",
2144               []>;
2145 def SULD_2D_V2I16_TRAP
2146   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2147               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2148               "suld.b.2d.v2.b16.trap \\{$r, $g\\}, [$s, \\{$x, $y\\}];",
2149               []>;
2150 def SULD_2D_V2I32_TRAP
2151   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g),
2152               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2153               "suld.b.2d.v2.b32.trap \\{$r, $g\\}, [$s, \\{$x, $y\\}];",
2154               []>;
2155 def SULD_2D_V4I8_TRAP
2156   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2157               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2158               "suld.b.2d.v4.b8.trap \\{$r, $g, $b, $a\\}, [$s, \\{$x, $y\\}];",
2159               []>;
2160 def SULD_2D_V4I16_TRAP
2161   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2162               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2163               "suld.b.2d.v4.b16.trap \\{$r, $g, $b, $a\\}, [$s, \\{$x, $y\\}];",
2164               []>;
2165 def SULD_2D_V4I32_TRAP
2166   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2167               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y),
2168               "suld.b.2d.v4.b32.trap \\{$r, $g, $b, $a\\}, [$s, \\{$x, $y\\}];",
2169               []>;
2170
2171 def SULD_2D_ARRAY_I8_TRAP
2172   : NVPTXInst<(outs Int16Regs:$r),
2173               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2174               "suld.b.a2d.b8.trap \\{$r\\}, [$s, \\{$l, $x, $y, $y\\}];",
2175               []>;
2176 def SULD_2D_ARRAY_I16_TRAP
2177   : NVPTXInst<(outs Int16Regs:$r),
2178               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2179               "suld.b.a2d.b16.trap \\{$r\\}, [$s, \\{$l, $x, $y, $y\\}];",
2180               []>;
2181 def SULD_2D_ARRAY_I32_TRAP
2182   : NVPTXInst<(outs Int32Regs:$r),
2183               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2184               "suld.b.a2d.b32.trap \\{$r\\}, [$s, \\{$l, $x, $y, $y\\}];",
2185               []>;
2186 def SULD_2D_ARRAY_V2I8_TRAP
2187   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2188               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2189               "suld.b.a2d.v2.b8.trap \\{$r, $g\\}, "
2190               "[$s, \\{$l, $x, $y, $y\\}];",
2191               []>;
2192 def SULD_2D_ARRAY_V2I16_TRAP
2193   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2194               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2195               "suld.b.a2d.v2.b16.trap \\{$r, $g\\}, "
2196               "[$s, \\{$l, $x, $y, $y\\}];",
2197               []>;
2198 def SULD_2D_ARRAY_V2I32_TRAP
2199   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g),
2200               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2201               "suld.b.a2d.v2.b32.trap \\{$r, $g\\}, "
2202               "[$s, \\{$l, $x, $y, $y\\}];",
2203               []>;
2204 def SULD_2D_ARRAY_V4I8_TRAP
2205   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2206               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2207               "suld.b.a2d.v4.b8.trap \\{$r, $g, $b, $a\\}, "
2208               "[$s, \\{$l, $x, $y, $y\\}];",
2209               []>;
2210 def SULD_2D_ARRAY_V4I16_TRAP
2211   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2212               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2213               "suld.b.a2d.v4.b16.trap \\{$r, $g, $b, $a\\}, "
2214               "[$s, \\{$l, $x, $y, $y\\}];",
2215               []>;
2216 def SULD_2D_ARRAY_V4I32_TRAP
2217   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2218               (ins Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y),
2219               "suld.b.a2d.v4.b32.trap \\{$r, $g, $b, $a\\}, "
2220               "[$s, \\{$l, $x, $y, $y\\}];",
2221               []>;
2222
2223 def SULD_3D_I8_TRAP
2224   : NVPTXInst<(outs Int16Regs:$r),
2225               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2226               "suld.b.3d.b8.trap \\{$r\\}, [$s, \\{$x, $y, $z, $z\\}];",
2227               []>;
2228 def SULD_3D_I16_TRAP
2229   : NVPTXInst<(outs Int16Regs:$r),
2230               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2231               "suld.b.3d.b16.trap \\{$r\\}, [$s, \\{$x, $y, $z, $z\\}];",
2232               []>;
2233 def SULD_3D_I32_TRAP
2234   : NVPTXInst<(outs Int32Regs:$r),
2235               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2236               "suld.b.3d.b32.trap \\{$r\\}, [$s, \\{$x, $y, $z, $z\\}];",
2237               []>;
2238 def SULD_3D_V2I8_TRAP
2239   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2240               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2241               "suld.b.3d.v2.b8.trap \\{$r, $g\\}, [$s, \\{$x, $y, $z, $z\\}];",
2242               []>;
2243 def SULD_3D_V2I16_TRAP
2244   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g),
2245               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2246               "suld.b.3d.v2.b16.trap \\{$r, $g\\}, [$s, \\{$x, $y, $z, $z\\}];",
2247               []>;
2248 def SULD_3D_V2I32_TRAP
2249   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g),
2250               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2251               "suld.b.3d.v2.b32.trap \\{$r, $g\\}, [$s, \\{$x, $y, $z, $z\\}];",
2252               []>;
2253 def SULD_3D_V4I8_TRAP
2254   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2255               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2256               "suld.b.3d.v4.b8.trap \\{$r, $g, $b, $a\\}, "
2257               "[$s, \\{$x, $y, $z, $z\\}];",
2258               []>;
2259 def SULD_3D_V4I16_TRAP
2260   : NVPTXInst<(outs Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2261               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2262               "suld.b.3d.v4.b16.trap \\{$r, $g, $b, $a\\}, "
2263               "[$s, \\{$x, $y, $z, $z\\}];",
2264               []>;
2265 def SULD_3D_V4I32_TRAP
2266   : NVPTXInst<(outs Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2267               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z),
2268               "suld.b.3d.v4.b32.trap \\{$r, $g, $b, $a\\}, "
2269               "[$s, \\{$x, $y, $z, $z\\}];",
2270               []>;
2271
2272
2273 //-----------------------------------
2274 // Texture Query Intrinsics
2275 //-----------------------------------
2276 def TXQ_CHANNEL_ORDER
2277   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2278               "txq.channel_order.b32 \t$d, [$a];",
2279               []>;
2280 def TXQ_CHANNEL_DATA_TYPE
2281   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2282               "txq.channel_data_type.b32 \t$d, [$a];",
2283               []>;
2284 def TXQ_WIDTH
2285   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2286               "txq.width.b32 \t$d, [$a];",
2287               []>;
2288 def TXQ_HEIGHT
2289   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2290               "txq.height.b32 \t$d, [$a];",
2291               []>;
2292 def TXQ_DEPTH
2293   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2294               "txq.depth.b32 \t$d, [$a];",
2295               []>;
2296 def TXQ_ARRAY_SIZE
2297   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2298               "txq.array_size.b32 \t$d, [$a];",
2299               []>;
2300 def TXQ_NUM_SAMPLES
2301   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2302               "txq.num_samples.b32 \t$d, [$a];",
2303               []>;
2304 def TXQ_NUM_MIPMAP_LEVELS
2305   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2306               "txq.num_mipmap_levels.b32 \t$d, [$a];",
2307               []>;
2308
2309 def : Pat<(int_nvvm_txq_channel_order Int64Regs:$a),
2310           (TXQ_CHANNEL_ORDER Int64Regs:$a)>;
2311 def : Pat<(int_nvvm_txq_channel_data_type Int64Regs:$a),
2312           (TXQ_CHANNEL_DATA_TYPE Int64Regs:$a)>;
2313 def : Pat<(int_nvvm_txq_width Int64Regs:$a),
2314           (TXQ_WIDTH Int64Regs:$a)>;
2315 def : Pat<(int_nvvm_txq_height Int64Regs:$a),
2316           (TXQ_HEIGHT Int64Regs:$a)>;
2317 def : Pat<(int_nvvm_txq_depth Int64Regs:$a),
2318           (TXQ_DEPTH Int64Regs:$a)>;
2319 def : Pat<(int_nvvm_txq_array_size Int64Regs:$a),
2320           (TXQ_ARRAY_SIZE Int64Regs:$a)>;
2321 def : Pat<(int_nvvm_txq_num_samples Int64Regs:$a),
2322           (TXQ_NUM_SAMPLES Int64Regs:$a)>;
2323 def : Pat<(int_nvvm_txq_num_mipmap_levels Int64Regs:$a),
2324           (TXQ_NUM_MIPMAP_LEVELS Int64Regs:$a)>;
2325
2326
2327 //-----------------------------------
2328 // Surface Query Intrinsics
2329 //-----------------------------------
2330 def SUQ_CHANNEL_ORDER
2331   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2332               "suq.channel_order.b32 \t$d, [$a];",
2333               []>;
2334 def SUQ_CHANNEL_DATA_TYPE
2335   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2336               "suq.channel_data_type.b32 \t$d, [$a];",
2337               []>;
2338 def SUQ_WIDTH
2339   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2340               "suq.width.b32 \t$d, [$a];",
2341               []>;
2342 def SUQ_HEIGHT
2343   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2344               "suq.height.b32 \t$d, [$a];",
2345               []>;
2346 def SUQ_DEPTH
2347   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2348               "suq.depth.b32 \t$d, [$a];",
2349               []>;
2350 def SUQ_ARRAY_SIZE
2351   : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
2352               "suq.array_size.b32 \t$d, [$a];",
2353               []>;
2354
2355 def : Pat<(int_nvvm_suq_channel_order Int64Regs:$a),
2356           (SUQ_CHANNEL_ORDER Int64Regs:$a)>;
2357 def : Pat<(int_nvvm_suq_channel_data_type Int64Regs:$a),
2358           (SUQ_CHANNEL_DATA_TYPE Int64Regs:$a)>;
2359 def : Pat<(int_nvvm_suq_width Int64Regs:$a),
2360           (SUQ_WIDTH Int64Regs:$a)>;
2361 def : Pat<(int_nvvm_suq_height Int64Regs:$a),
2362           (SUQ_HEIGHT Int64Regs:$a)>;
2363 def : Pat<(int_nvvm_suq_depth Int64Regs:$a),
2364           (SUQ_DEPTH Int64Regs:$a)>;
2365 def : Pat<(int_nvvm_suq_array_size Int64Regs:$a),
2366           (SUQ_ARRAY_SIZE Int64Regs:$a)>;
2367
2368
2369 //===- Handle Query -------------------------------------------------------===//
2370
2371 // TODO: These intrinsics are not yet finalized, pending PTX ISA design work
2372 def ISTYPEP_SAMPLER
2373   : NVPTXInst<(outs Int1Regs:$d), (ins Int64Regs:$a),
2374               "istypep.samplerref \t$d, $a;",
2375               [(set Int1Regs:$d, (int_nvvm_istypep_sampler Int64Regs:$a))]>;
2376 def ISTYPEP_SURFACE
2377   : NVPTXInst<(outs Int1Regs:$d), (ins Int64Regs:$a),
2378               "istypep.surfref \t$d, $a;",
2379               [(set Int1Regs:$d, (int_nvvm_istypep_surface Int64Regs:$a))]>;
2380 def ISTYPEP_TEXTURE
2381   : NVPTXInst<(outs Int1Regs:$d), (ins Int64Regs:$a),
2382               "istypep.texref \t$d, $a;",
2383               [(set Int1Regs:$d, (int_nvvm_istypep_texture Int64Regs:$a))]>;
2384
2385 //===- Surface Stores -----------------------------------------------------===//
2386
2387 // Unformatted
2388
2389 def SUST_B_1D_B8_TRAP
2390   : NVPTXInst<(outs),
2391               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
2392               "sust.b.1d.b8.trap \t[$s, \\{$x\\}], \\{$r\\};",
2393               []>;
2394 def SUST_B_1D_B16_TRAP
2395   : NVPTXInst<(outs),
2396               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
2397               "sust.b.1d.b16.trap \t[$s, \\{$x\\}], \\{$r\\};",
2398               []>;
2399 def SUST_B_1D_B32_TRAP
2400   : NVPTXInst<(outs),
2401               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$r),
2402               "sust.b.1d.b32.trap \t[$s, \\{$x\\}], \\{$r\\};",
2403               []>;
2404 def SUST_B_1D_V2B8_TRAP
2405   : NVPTXInst<(outs),
2406               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
2407               "sust.b.1d.v2.b8.trap \t[$s, \\{$x\\}], \\{$r, $g\\};",
2408               []>;
2409 def SUST_B_1D_V2B16_TRAP
2410   : NVPTXInst<(outs),
2411               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
2412               "sust.b.1d.v2.b16.trap \t[$s, \\{$x\\}], \\{$r, $g\\};",
2413               []>;
2414 def SUST_B_1D_V2B32_TRAP
2415   : NVPTXInst<(outs),
2416               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g),
2417               "sust.b.1d.v2.b32.trap \t[$s, \\{$x\\}], \\{$r, $g\\};",
2418               []>;
2419 def SUST_B_1D_V4B8_TRAP
2420   : NVPTXInst<(outs),
2421               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g,
2422                    Int16Regs:$b, Int16Regs:$a),
2423               "sust.b.1d.v4.b8.trap \t[$s, \\{$x\\}], \\{$r, $g, $b, $a\\};",
2424               []>;
2425 def SUST_B_1D_V4B16_TRAP
2426   : NVPTXInst<(outs),
2427               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g,
2428                    Int16Regs:$b, Int16Regs:$a),
2429               "sust.b.1d.v4.b16.trap \t[$s, \\{$x\\}], \\{$r, $g, $b, $a\\};",
2430               []>;
2431 def SUST_B_1D_V4B32_TRAP
2432   : NVPTXInst<(outs),
2433               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g,
2434                    Int32Regs:$b, Int32Regs:$a),
2435               "sust.b.1d.v4.b32.trap \t[$s, \\{$x\\}], \\{$r, $g, $b, $a\\};",
2436               []>;
2437
2438
2439 def SUST_B_1D_ARRAY_B8_TRAP
2440   : NVPTXInst<(outs),
2441               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r),
2442               "sust.b.a1d.b8.trap \t[$s, \\{$idx, $x\\}], \\{$r\\};",
2443               []>;
2444 def SUST_B_1D_ARRAY_B16_TRAP
2445   : NVPTXInst<(outs),
2446               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r),
2447               "sust.b.a1d.b16.trap \t[$s, \\{$idx, $x\\}], \\{$r\\};",
2448               []>;
2449 def SUST_B_1D_ARRAY_B32_TRAP
2450   : NVPTXInst<(outs),
2451               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$r),
2452               "sust.b.a1d.b32.trap \t[$s, \\{$idx, $x\\}], \\{$r\\};",
2453               []>;
2454 def SUST_B_1D_ARRAY_V2B8_TRAP
2455   : NVPTXInst<(outs),
2456               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2457                    Int16Regs:$g),
2458               "sust.b.a1d.v2.b8.trap \t[$s, \\{$idx, $x\\}], \\{$r, $g\\};",
2459               []>;
2460 def SUST_B_1D_ARRAY_V2B16_TRAP
2461   : NVPTXInst<(outs),
2462               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2463                    Int16Regs:$g),
2464               "sust.b.a1d.v2.b16.trap \t[$s, \\{$idx, $x\\}], \\{$r, $g\\};",
2465               []>;
2466 def SUST_B_1D_ARRAY_V2B32_TRAP
2467   : NVPTXInst<(outs),
2468               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$r,
2469                    Int32Regs:$g),
2470               "sust.b.a1d.v2.b32.trap \t[$s, \\{$idx, $x\\}], \\{$r, $g\\};",
2471               []>;
2472 def SUST_B_1D_ARRAY_V4B8_TRAP
2473   : NVPTXInst<(outs),
2474               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2475                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2476               "sust.b.a1d.v4.b8.trap \t[$s, \\{$idx, $x\\}], "
2477               "\\{$r, $g, $b, $a\\};",
2478               []>;
2479 def SUST_B_1D_ARRAY_V4B16_TRAP
2480   : NVPTXInst<(outs),
2481               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2482                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2483              "sust.b.a1d.v4.b16.trap \t[$s, \\{$idx, $x\\}], "
2484              "\\{$r, $g, $b, $a\\};",
2485               []>;
2486 def SUST_B_1D_ARRAY_V4B32_TRAP
2487   : NVPTXInst<(outs),
2488               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$r,
2489                    Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2490              "sust.b.a1d.v4.b32.trap \t[$s, \\{$idx, $x\\}], "
2491              "\\{$r, $g, $b, $a\\};",
2492               []>;
2493
2494
2495 def SUST_B_2D_B8_TRAP
2496   : NVPTXInst<(outs),
2497               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
2498               "sust.b.2d.b8.trap \t[$s, \\{$x, $y\\}], \\{$r\\};",
2499               []>;
2500 def SUST_B_2D_B16_TRAP
2501   : NVPTXInst<(outs),
2502               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
2503               "sust.b.2d.b16.trap \t[$s, \\{$x, $y\\}], \\{$r\\};",
2504               []>;
2505 def SUST_B_2D_B32_TRAP
2506   : NVPTXInst<(outs),
2507               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r),
2508               "sust.b.2d.b32.trap \t[$s, \\{$x, $y\\}], \\{$r\\};",
2509               []>;
2510 def SUST_B_2D_V2B8_TRAP
2511   : NVPTXInst<(outs),
2512               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2513                    Int16Regs:$g),
2514               "sust.b.2d.v2.b8.trap \t[$s, \\{$x, $y\\}], \\{$r, $g\\};",
2515               []>;
2516 def SUST_B_2D_V2B16_TRAP
2517   : NVPTXInst<(outs),
2518               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2519                    Int16Regs:$g),
2520               "sust.b.2d.v2.b16.trap \t[$s, \\{$x, $y\\}], \\{$r, $g\\};",
2521               []>;
2522 def SUST_B_2D_V2B32_TRAP
2523   : NVPTXInst<(outs),
2524               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r,
2525                    Int32Regs:$g),
2526               "sust.b.2d.v2.b32.trap \t[$s, \\{$x, $y\\}], \\{$r, $g\\};",
2527               []>;
2528 def SUST_B_2D_V4B8_TRAP
2529   : NVPTXInst<(outs),
2530               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2531                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2532               "sust.b.2d.v4.b8.trap \t[$s, \\{$x, $y\\}], "
2533               "\\{$r, $g, $b, $a\\};",
2534               []>;
2535 def SUST_B_2D_V4B16_TRAP
2536   : NVPTXInst<(outs),
2537               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2538                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2539              "sust.b.2d.v4.b16.trap \t[$s, \\{$x, $y\\}], "
2540              "\\{$r, $g, $b, $a\\};",
2541               []>;
2542 def SUST_B_2D_V4B32_TRAP
2543   : NVPTXInst<(outs),
2544               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r,
2545                    Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2546              "sust.b.2d.v4.b32.trap \t[$s, \\{$x, $y\\}], "
2547              "\\{$r, $g, $b, $a\\};",
2548               []>;
2549
2550
2551 def SUST_B_2D_ARRAY_B8_TRAP
2552   : NVPTXInst<(outs),
2553               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2554                    Int16Regs:$r),
2555               "sust.b.a2d.b8.trap \t[$s, \\{$idx, $x, $y, $y\\}], \\{$r\\};",
2556               []>;
2557 def SUST_B_2D_ARRAY_B16_TRAP
2558   : NVPTXInst<(outs),
2559               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2560                    Int16Regs:$r),
2561               "sust.b.a2d.b16.trap \t[$s, \\{$idx, $x, $y, $y\\}], \\{$r\\};",
2562               []>;
2563 def SUST_B_2D_ARRAY_B32_TRAP
2564   : NVPTXInst<(outs),
2565               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2566                    Int32Regs:$r),
2567               "sust.b.a2d.b32.trap \t[$s, \\{$idx, $x, $y, $y\\}], \\{$r\\};",
2568               []>;
2569 def SUST_B_2D_ARRAY_V2B8_TRAP
2570   : NVPTXInst<(outs),
2571               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2572                    Int16Regs:$r, Int16Regs:$g),
2573               "sust.b.a2d.v2.b8.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2574               "\\{$r, $g\\};",
2575               []>;
2576 def SUST_B_2D_ARRAY_V2B16_TRAP
2577   : NVPTXInst<(outs),
2578               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2579                    Int16Regs:$r, Int16Regs:$g),
2580              "sust.b.a2d.v2.b16.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2581              "\\{$r, $g\\};",
2582               []>;
2583 def SUST_B_2D_ARRAY_V2B32_TRAP
2584   : NVPTXInst<(outs),
2585               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2586                    Int32Regs:$r, Int32Regs:$g),
2587              "sust.b.a2d.v2.b32.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2588              "\\{$r, $g\\};",
2589               []>;
2590 def SUST_B_2D_ARRAY_V4B8_TRAP
2591   : NVPTXInst<(outs),
2592               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2593                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2594       "sust.b.a2d.v4.b8.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2595       "\\{$r, $g, $b, $a\\};",
2596               []>;
2597 def SUST_B_2D_ARRAY_V4B16_TRAP
2598   : NVPTXInst<(outs),
2599               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2600                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2601      "sust.b.a2d.v4.b16.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2602      "\\{$r, $g, $b, $a\\};",
2603               []>;
2604 def SUST_B_2D_ARRAY_V4B32_TRAP
2605   : NVPTXInst<(outs),
2606               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2607                    Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2608      "sust.b.a2d.v4.b32.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2609      "\\{$r, $g, $b, $a\\};",
2610               []>;
2611
2612
2613 def SUST_B_3D_B8_TRAP
2614   : NVPTXInst<(outs),
2615               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2616                    Int16Regs:$r),
2617               "sust.b.3d.b8.trap \t[$s, \\{$x, $y, $z, $z\\}], \\{$r\\};",
2618               []>;
2619 def SUST_B_3D_B16_TRAP
2620   : NVPTXInst<(outs),
2621               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2622                    Int16Regs:$r),
2623               "sust.b.3d.b16.trap \t[$s, \\{$x, $y, $z, $z\\}], \\{$r\\};",
2624               []>;
2625 def SUST_B_3D_B32_TRAP
2626   : NVPTXInst<(outs),
2627               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2628                    Int32Regs:$r),
2629               "sust.b.3d.b32.trap \t[$s, \\{$x, $y, $z, $z\\}], \\{$r\\};",
2630               []>;
2631 def SUST_B_3D_V2B8_TRAP
2632   : NVPTXInst<(outs),
2633               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2634                    Int16Regs:$r, Int16Regs:$g),
2635               "sust.b.3d.v2.b8.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2636               "\\{$r, $g\\};",
2637               []>;
2638 def SUST_B_3D_V2B16_TRAP
2639   : NVPTXInst<(outs),
2640               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2641                    Int16Regs:$r, Int16Regs:$g),
2642               "sust.b.3d.v2.b16.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2643               "\\{$r, $g\\};",
2644               []>;
2645 def SUST_B_3D_V2B32_TRAP
2646   : NVPTXInst<(outs),
2647               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2648                    Int32Regs:$r, Int32Regs:$g),
2649               "sust.b.3d.v2.b32.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2650               "\\{$r, $g\\};",
2651               []>;
2652 def SUST_B_3D_V4B8_TRAP
2653   : NVPTXInst<(outs),
2654               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2655                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2656          "sust.b.3d.v4.b8.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2657          "\\{$r, $g, $b, $a\\};",
2658               []>;
2659 def SUST_B_3D_V4B16_TRAP
2660   : NVPTXInst<(outs),
2661               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2662                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2663         "sust.b.3d.v4.b16.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2664         "\\{$r, $g, $b, $a\\};",
2665               []>;
2666 def SUST_B_3D_V4B32_TRAP
2667   : NVPTXInst<(outs),
2668               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2669                    Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2670         "sust.b.3d.v4.b32.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2671         "\\{$r, $g, $b, $a\\};",
2672               []>;
2673
2674 // Formatted
2675
2676 def SUST_P_1D_B8_TRAP
2677   : NVPTXInst<(outs),
2678               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
2679               "sust.p.1d.b8.trap \t[$s, \\{$x\\}], \\{$r\\};",
2680               []>;
2681 def SUST_P_1D_B16_TRAP
2682   : NVPTXInst<(outs),
2683               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
2684               "sust.p.1d.b16.trap \t[$s, \\{$x\\}], \\{$r\\};",
2685               []>;
2686 def SUST_P_1D_B32_TRAP
2687   : NVPTXInst<(outs),
2688               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$r),
2689               "sust.p.1d.b32.trap \t[$s, \\{$x\\}], \\{$r\\};",
2690               []>;
2691 def SUST_P_1D_V2B8_TRAP
2692   : NVPTXInst<(outs),
2693               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
2694               "sust.p.1d.v2.b8.trap \t[$s, \\{$x\\}], \\{$r, $g\\};",
2695               []>;
2696 def SUST_P_1D_V2B16_TRAP
2697   : NVPTXInst<(outs),
2698               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
2699               "sust.p.1d.v2.b16.trap \t[$s, \\{$x\\}], \\{$r, $g\\};",
2700               []>;
2701 def SUST_P_1D_V2B32_TRAP
2702   : NVPTXInst<(outs),
2703               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g),
2704               "sust.p.1d.v2.b32.trap \t[$s, \\{$x\\}], \\{$r, $g\\};",
2705               []>;
2706 def SUST_P_1D_V4B8_TRAP
2707   : NVPTXInst<(outs),
2708               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g,
2709                    Int16Regs:$b, Int16Regs:$a),
2710               "sust.p.1d.v4.b8.trap \t[$s, \\{$x\\}], \\{$r, $g, $b, $a\\};",
2711               []>;
2712 def SUST_P_1D_V4B16_TRAP
2713   : NVPTXInst<(outs),
2714               (ins Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g,
2715                    Int16Regs:$b, Int16Regs:$a),
2716               "sust.p.1d.v4.b16.trap \t[$s, \\{$x\\}], \\{$r, $g, $b, $a\\};",
2717               []>;
2718 def SUST_P_1D_V4B32_TRAP
2719   : NVPTXInst<(outs),
2720               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g,
2721                    Int32Regs:$b, Int32Regs:$a),
2722               "sust.p.1d.v4.b32.trap \t[$s, \\{$x\\}], \\{$r, $g, $b, $a\\};",
2723               []>;
2724
2725
2726 def SUST_P_1D_ARRAY_B8_TRAP
2727   : NVPTXInst<(outs),
2728               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r),
2729               "sust.p.a1d.b8.trap \t[$s, \\{$idx, $x\\}], \\{$r\\};",
2730               []>;
2731 def SUST_P_1D_ARRAY_B16_TRAP
2732   : NVPTXInst<(outs),
2733               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r),
2734               "sust.p.a1d.b16.trap \t[$s, \\{$idx, $x\\}], \\{$r\\};",
2735               []>;
2736 def SUST_P_1D_ARRAY_B32_TRAP
2737   : NVPTXInst<(outs),
2738               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$r),
2739               "sust.p.a1d.b32.trap \t[$s, \\{$idx, $x\\}], \\{$r\\};",
2740               []>;
2741 def SUST_P_1D_ARRAY_V2B8_TRAP
2742   : NVPTXInst<(outs),
2743               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2744                    Int16Regs:$g),
2745               "sust.p.a1d.v2.b8.trap \t[$s, \\{$idx, $x\\}], \\{$r, $g\\};",
2746               []>;
2747 def SUST_P_1D_ARRAY_V2B16_TRAP
2748   : NVPTXInst<(outs),
2749               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2750                    Int16Regs:$g),
2751               "sust.p.a1d.v2.b16.trap \t[$s, \\{$idx, $x\\}], \\{$r, $g\\};",
2752               []>;
2753 def SUST_P_1D_ARRAY_V2B32_TRAP
2754   : NVPTXInst<(outs),
2755               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$r,
2756                    Int32Regs:$g),
2757               "sust.p.a1d.v2.b32.trap \t[$s, \\{$idx, $x\\}], \\{$r, $g\\};",
2758               []>;
2759 def SUST_P_1D_ARRAY_V4B8_TRAP
2760   : NVPTXInst<(outs),
2761               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2762                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2763               "sust.p.a1d.v4.b8.trap \t[$s, \\{$idx, $x\\}], "
2764               "\\{$r, $g, $b, $a\\};",
2765               []>;
2766 def SUST_P_1D_ARRAY_V4B16_TRAP
2767   : NVPTXInst<(outs),
2768               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int16Regs:$r,
2769                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2770              "sust.p.a1d.v4.b16.trap \t[$s, \\{$idx, $x\\}], "
2771              "\\{$r, $g, $b, $a\\};",
2772               []>;
2773 def SUST_P_1D_ARRAY_V4B32_TRAP
2774   : NVPTXInst<(outs),
2775               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$r,
2776                    Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2777              "sust.p.a1d.v4.b32.trap \t[$s, \\{$idx, $x\\}], "
2778              "\\{$r, $g, $b, $a\\};",
2779               []>;
2780
2781
2782 def SUST_P_2D_B8_TRAP
2783   : NVPTXInst<(outs),
2784               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
2785               "sust.p.2d.b8.trap \t[$s, \\{$x, $y\\}], \\{$r\\};",
2786               []>;
2787 def SUST_P_2D_B16_TRAP
2788   : NVPTXInst<(outs),
2789               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
2790               "sust.p.2d.b16.trap \t[$s, \\{$x, $y\\}], \\{$r\\};",
2791               []>;
2792 def SUST_P_2D_B32_TRAP
2793   : NVPTXInst<(outs),
2794               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r),
2795               "sust.p.2d.b32.trap \t[$s, \\{$x, $y\\}], \\{$r\\};",
2796               []>;
2797 def SUST_P_2D_V2B8_TRAP
2798   : NVPTXInst<(outs),
2799               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2800                    Int16Regs:$g),
2801               "sust.p.2d.v2.b8.trap \t[$s, \\{$x, $y\\}], \\{$r, $g\\};",
2802               []>;
2803 def SUST_P_2D_V2B16_TRAP
2804   : NVPTXInst<(outs),
2805               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2806                    Int16Regs:$g),
2807               "sust.p.2d.v2.b16.trap \t[$s, \\{$x, $y\\}], \\{$r, $g\\};",
2808               []>;
2809 def SUST_P_2D_V2B32_TRAP
2810   : NVPTXInst<(outs),
2811               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r,
2812                    Int32Regs:$g),
2813               "sust.p.2d.v2.b32.trap \t[$s, \\{$x, $y\\}], \\{$r, $g\\};",
2814               []>;
2815 def SUST_P_2D_V4B8_TRAP
2816   : NVPTXInst<(outs),
2817               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2818                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2819               "sust.p.2d.v4.b8.trap \t[$s, \\{$x, $y\\}], "
2820               "\\{$r, $g, $b, $a\\};",
2821               []>;
2822 def SUST_P_2D_V4B16_TRAP
2823   : NVPTXInst<(outs),
2824               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r,
2825                    Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2826              "sust.p.2d.v4.b16.trap \t[$s, \\{$x, $y\\}], "
2827              "\\{$r, $g, $b, $a\\};",
2828               []>;
2829 def SUST_P_2D_V4B32_TRAP
2830   : NVPTXInst<(outs),
2831               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r,
2832                    Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2833              "sust.p.2d.v4.b32.trap \t[$s, \\{$x, $y\\}], "
2834              "\\{$r, $g, $b, $a\\};",
2835               []>;
2836
2837
2838 def SUST_P_2D_ARRAY_B8_TRAP
2839   : NVPTXInst<(outs),
2840               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2841                    Int16Regs:$r),
2842               "sust.p.a2d.b8.trap \t[$s, \\{$idx, $x, $y, $y\\}], \\{$r\\};",
2843               []>;
2844 def SUST_P_2D_ARRAY_B16_TRAP
2845   : NVPTXInst<(outs),
2846               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2847                    Int16Regs:$r),
2848               "sust.p.a2d.b16.trap \t[$s, \\{$idx, $x, $y, $y\\}], \\{$r\\};",
2849               []>;
2850 def SUST_P_2D_ARRAY_B32_TRAP
2851   : NVPTXInst<(outs),
2852               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2853                    Int32Regs:$r),
2854               "sust.p.a2d.b32.trap \t[$s, \\{$idx, $x, $y, $y\\}], \\{$r\\};",
2855               []>;
2856 def SUST_P_2D_ARRAY_V2B8_TRAP
2857   : NVPTXInst<(outs),
2858               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2859                    Int16Regs:$r, Int16Regs:$g),
2860               "sust.p.a2d.v2.b8.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2861               "\\{$r, $g\\};",
2862               []>;
2863 def SUST_P_2D_ARRAY_V2B16_TRAP
2864   : NVPTXInst<(outs),
2865               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2866                    Int16Regs:$r, Int16Regs:$g),
2867              "sust.p.a2d.v2.b16.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2868              "\\{$r, $g\\};",
2869               []>;
2870 def SUST_P_2D_ARRAY_V2B32_TRAP
2871   : NVPTXInst<(outs),
2872               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2873                    Int32Regs:$r, Int32Regs:$g),
2874              "sust.p.a2d.v2.b32.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2875              "\\{$r, $g\\};",
2876               []>;
2877 def SUST_P_2D_ARRAY_V4B8_TRAP
2878   : NVPTXInst<(outs),
2879               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2880                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2881       "sust.p.a2d.v4.b8.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2882       "\\{$r, $g, $b, $a\\};",
2883               []>;
2884 def SUST_P_2D_ARRAY_V4B16_TRAP
2885   : NVPTXInst<(outs),
2886               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2887                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2888      "sust.p.a2d.v4.b16.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2889      "\\{$r, $g, $b, $a\\};",
2890               []>;
2891 def SUST_P_2D_ARRAY_V4B32_TRAP
2892   : NVPTXInst<(outs),
2893               (ins Int64Regs:$s, Int32Regs:$idx, Int32Regs:$x, Int32Regs:$y,
2894                    Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2895      "sust.p.a2d.v4.b32.trap \t[$s, \\{$idx, $x, $y, $y\\}], "
2896      "\\{$r, $g, $b, $a\\};",
2897               []>;
2898
2899
2900 def SUST_P_3D_B8_TRAP
2901   : NVPTXInst<(outs),
2902               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2903                    Int16Regs:$r),
2904               "sust.p.3d.b8.trap \t[$s, \\{$x, $y, $z, $z\\}], \\{$r\\};",
2905               []>;
2906 def SUST_P_3D_B16_TRAP
2907   : NVPTXInst<(outs),
2908               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2909                    Int16Regs:$r),
2910               "sust.p.3d.b16.trap \t[$s, \\{$x, $y, $z, $z\\}], \\{$r\\};",
2911               []>;
2912 def SUST_P_3D_B32_TRAP
2913   : NVPTXInst<(outs),
2914               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2915                    Int32Regs:$r),
2916               "sust.p.3d.b32.trap \t[$s, \\{$x, $y, $z, $z\\}], \\{$r\\};",
2917               []>;
2918 def SUST_P_3D_V2B8_TRAP
2919   : NVPTXInst<(outs),
2920               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2921                    Int16Regs:$r, Int16Regs:$g),
2922               "sust.p.3d.v2.b8.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2923               "\\{$r, $g\\};",
2924               []>;
2925 def SUST_P_3D_V2B16_TRAP
2926   : NVPTXInst<(outs),
2927               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2928                    Int16Regs:$r, Int16Regs:$g),
2929               "sust.p.3d.v2.b16.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2930               "\\{$r, $g\\};",
2931               []>;
2932 def SUST_P_3D_V2B32_TRAP
2933   : NVPTXInst<(outs),
2934               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2935                    Int32Regs:$r, Int32Regs:$g),
2936               "sust.p.3d.v2.b32.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2937               "\\{$r, $g\\};",
2938               []>;
2939 def SUST_P_3D_V4B8_TRAP
2940   : NVPTXInst<(outs),
2941               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2942                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2943          "sust.p.3d.v4.b8.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2944          "\\{$r, $g, $b, $a\\};",
2945               []>;
2946 def SUST_P_3D_V4B16_TRAP
2947   : NVPTXInst<(outs),
2948               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2949                    Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2950         "sust.p.3d.v4.b16.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2951         "\\{$r, $g, $b, $a\\};",
2952               []>;
2953 def SUST_P_3D_V4B32_TRAP
2954   : NVPTXInst<(outs),
2955               (ins Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
2956                    Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
2957         "sust.p.3d.v4.b32.trap \t[$s, \\{$x, $y, $z, $z\\}], "
2958         "\\{$r, $g, $b, $a\\};",
2959               []>;
2960
2961
2962 // Surface store instruction patterns
2963 // I'm not sure why we can't just include these in the instruction definitions,
2964 // but TableGen complains of type errors :(
2965
2966 def : Pat<(int_nvvm_sust_b_1d_i8_trap
2967            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
2968           (SUST_B_1D_B8_TRAP Int64Regs:$s, Int32Regs:$x, Int16Regs:$r)>;
2969
2970 def : Pat<(int_nvvm_sust_b_1d_i16_trap
2971            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
2972           (SUST_B_1D_B16_TRAP Int64Regs:$s, Int32Regs:$x, Int16Regs:$r)>;
2973
2974 def : Pat<(int_nvvm_sust_b_1d_i32_trap
2975            Int64Regs:$s, Int32Regs:$x, Int32Regs:$r),
2976           (SUST_B_1D_B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$r)>;
2977
2978 def : Pat<(int_nvvm_sust_b_1d_v2i8_trap
2979            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
2980           (SUST_B_1D_V2B8_TRAP Int64Regs:$s, Int32Regs:$x,
2981            Int16Regs:$r, Int16Regs:$g)>;
2982
2983 def : Pat<(int_nvvm_sust_b_1d_v2i16_trap
2984            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
2985           (SUST_B_1D_V2B16_TRAP Int64Regs:$s, Int32Regs:$x,
2986            Int16Regs:$r, Int16Regs:$g)>;
2987
2988 def : Pat<(int_nvvm_sust_b_1d_v2i32_trap
2989            Int64Regs:$s, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g),
2990           (SUST_B_1D_V2B32_TRAP Int64Regs:$s, Int32Regs:$x,
2991            Int32Regs:$r, Int32Regs:$g)>;
2992
2993 def : Pat<(int_nvvm_sust_b_1d_v4i8_trap
2994            Int64Regs:$s, Int32Regs:$x,
2995            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
2996           (SUST_B_1D_V4B8_TRAP Int64Regs:$s, Int32Regs:$x,
2997            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
2998
2999 def : Pat<(int_nvvm_sust_b_1d_v4i16_trap
3000            Int64Regs:$s, Int32Regs:$x,
3001            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3002           (SUST_B_1D_V4B16_TRAP Int64Regs:$s, Int32Regs:$x,
3003            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3004
3005 def : Pat<(int_nvvm_sust_b_1d_v4i32_trap
3006            Int64Regs:$s, Int32Regs:$x,
3007            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3008           (SUST_B_1D_V4B32_TRAP Int64Regs:$s, Int32Regs:$x,
3009            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3010
3011
3012
3013 def : Pat<(int_nvvm_sust_b_1d_array_i8_trap
3014            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r),
3015           (SUST_B_1D_ARRAY_B8_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3016            Int16Regs:$r)>;
3017
3018 def : Pat<(int_nvvm_sust_b_1d_array_i16_trap
3019            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r),
3020           (SUST_B_1D_ARRAY_B16_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3021            Int16Regs:$r)>;
3022
3023 def : Pat<(int_nvvm_sust_b_1d_array_i32_trap
3024            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$r),
3025           (SUST_B_1D_ARRAY_B32_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3026            Int32Regs:$r)>;
3027
3028 def : Pat<(int_nvvm_sust_b_1d_array_v2i8_trap
3029           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
3030           (SUST_B_1D_ARRAY_V2B8_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3031            Int16Regs:$r, Int16Regs:$g)>;
3032
3033 def : Pat<(int_nvvm_sust_b_1d_array_v2i16_trap
3034           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
3035           (SUST_B_1D_ARRAY_V2B16_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3036            Int16Regs:$r, Int16Regs:$g)>;
3037
3038 def : Pat<(int_nvvm_sust_b_1d_array_v2i32_trap
3039           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g),
3040           (SUST_B_1D_ARRAY_V2B32_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3041            Int32Regs:$r, Int32Regs:$g)>;
3042
3043 def : Pat<(int_nvvm_sust_b_1d_array_v4i8_trap
3044            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3045            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3046           (SUST_B_1D_ARRAY_V4B8_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3047            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3048
3049 def : Pat<(int_nvvm_sust_b_1d_array_v4i16_trap
3050            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3051            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3052           (SUST_B_1D_ARRAY_V4B16_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3053            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3054
3055 def : Pat<(int_nvvm_sust_b_1d_array_v4i32_trap
3056            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3057            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3058           (SUST_B_1D_ARRAY_V4B32_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3059            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3060
3061
3062
3063 def : Pat<(int_nvvm_sust_b_2d_i8_trap
3064            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3065           (SUST_B_2D_B8_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3066            Int16Regs:$r)>;
3067
3068 def : Pat<(int_nvvm_sust_b_2d_i16_trap
3069            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3070           (SUST_B_2D_B16_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3071            Int16Regs:$r)>;
3072
3073 def : Pat<(int_nvvm_sust_b_2d_i32_trap
3074            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r),
3075           (SUST_B_2D_B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3076            Int32Regs:$r)>;
3077
3078 def : Pat<(int_nvvm_sust_b_2d_v2i8_trap
3079           Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r, Int16Regs:$g),
3080           (SUST_B_2D_V2B8_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3081            Int16Regs:$r, Int16Regs:$g)>;
3082
3083 def : Pat<(int_nvvm_sust_b_2d_v2i16_trap
3084           Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r, Int16Regs:$g),
3085           (SUST_B_2D_V2B16_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3086            Int16Regs:$r, Int16Regs:$g)>;
3087
3088 def : Pat<(int_nvvm_sust_b_2d_v2i32_trap
3089           Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r, Int32Regs:$g),
3090           (SUST_B_2D_V2B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3091            Int32Regs:$r, Int32Regs:$g)>;
3092
3093 def : Pat<(int_nvvm_sust_b_2d_v4i8_trap
3094            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3095            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3096           (SUST_B_2D_V4B8_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3097            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3098
3099 def : Pat<(int_nvvm_sust_b_2d_v4i16_trap
3100            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3101            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3102           (SUST_B_2D_V4B16_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3103            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3104
3105 def : Pat<(int_nvvm_sust_b_2d_v4i32_trap
3106            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3107            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3108           (SUST_B_2D_V4B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3109            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3110
3111
3112
3113 def : Pat<(int_nvvm_sust_b_2d_array_i8_trap
3114           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3115           (SUST_B_2D_ARRAY_B8_TRAP Int64Regs:$s,
3116            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3117            Int16Regs:$r)>;
3118
3119 def : Pat<(int_nvvm_sust_b_2d_array_i16_trap
3120           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3121           (SUST_B_2D_ARRAY_B16_TRAP Int64Regs:$s,
3122            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3123            Int16Regs:$r)>;
3124
3125 def : Pat<(int_nvvm_sust_b_2d_array_i32_trap
3126           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r),
3127           (SUST_B_2D_ARRAY_B32_TRAP Int64Regs:$s,
3128            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3129            Int32Regs:$r)>;
3130
3131 def : Pat<(int_nvvm_sust_b_2d_array_v2i8_trap
3132            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3133            Int16Regs:$r, Int16Regs:$g),
3134           (SUST_B_2D_ARRAY_V2B8_TRAP Int64Regs:$s, Int32Regs:$l,
3135            Int32Regs:$x, Int32Regs:$y,
3136            Int16Regs:$r, Int16Regs:$g)>;
3137
3138 def : Pat<(int_nvvm_sust_b_2d_array_v2i16_trap
3139            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3140            Int16Regs:$r, Int16Regs:$g),
3141           (SUST_B_2D_ARRAY_V2B16_TRAP Int64Regs:$s, Int32Regs:$l,
3142            Int32Regs:$x, Int32Regs:$y,
3143            Int16Regs:$r, Int16Regs:$g)>;
3144
3145 def : Pat<(int_nvvm_sust_b_2d_array_v2i32_trap
3146            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r,
3147            Int32Regs:$g),
3148           (SUST_B_2D_ARRAY_V2B32_TRAP Int64Regs:$s, Int32Regs:$l,
3149            Int32Regs:$x, Int32Regs:$y, Int32Regs:$r, Int32Regs:$g)>;
3150
3151 def : Pat<(int_nvvm_sust_b_2d_array_v4i8_trap
3152            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3153            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3154           (SUST_B_2D_ARRAY_V4B8_TRAP Int64Regs:$s,
3155            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3156            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3157
3158 def : Pat<(int_nvvm_sust_b_2d_array_v4i16_trap
3159            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3160            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3161           (SUST_B_2D_ARRAY_V4B16_TRAP Int64Regs:$s,
3162            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3163            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3164
3165 def : Pat<(int_nvvm_sust_b_2d_array_v4i32_trap
3166            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3167            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3168           (SUST_B_2D_ARRAY_V4B32_TRAP Int64Regs:$s, Int32Regs:$l,
3169            Int32Regs:$x, Int32Regs:$y,
3170            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3171
3172
3173
3174 def : Pat<(int_nvvm_sust_b_3d_i8_trap
3175            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3176            Int16Regs:$r),
3177           (SUST_B_3D_B8_TRAP Int64Regs:$s,
3178            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3179            Int16Regs:$r)>;
3180
3181 def : Pat<(int_nvvm_sust_b_3d_i16_trap
3182            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3183            Int16Regs:$r),
3184           (SUST_B_3D_B16_TRAP Int64Regs:$s,
3185            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3186            Int16Regs:$r)>;
3187
3188 def : Pat<(int_nvvm_sust_b_3d_i32_trap
3189            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3190            Int32Regs:$r),
3191           (SUST_B_3D_B32_TRAP Int64Regs:$s,
3192            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3193            Int32Regs:$r)>;
3194
3195 def : Pat<(int_nvvm_sust_b_3d_v2i8_trap
3196            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3197            Int16Regs:$r, Int16Regs:$g),
3198           (SUST_B_3D_V2B8_TRAP Int64Regs:$s,
3199            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3200            Int16Regs:$r, Int16Regs:$g)>;
3201
3202 def : Pat<(int_nvvm_sust_b_3d_v2i16_trap
3203            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3204            Int16Regs:$r, Int16Regs:$g),
3205           (SUST_B_3D_V2B16_TRAP Int64Regs:$s,
3206            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3207            Int16Regs:$r, Int16Regs:$g)>;
3208
3209 def : Pat<(int_nvvm_sust_b_3d_v2i32_trap
3210            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3211            Int32Regs:$r, Int32Regs:$g),
3212           (SUST_B_3D_V2B32_TRAP Int64Regs:$s,
3213            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3214            Int32Regs:$r, Int32Regs:$g)>;
3215
3216 def : Pat<(int_nvvm_sust_b_3d_v4i8_trap
3217            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3218            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3219           (SUST_B_3D_V4B8_TRAP Int64Regs:$s,
3220            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3221            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3222
3223 def : Pat<(int_nvvm_sust_b_3d_v4i16_trap
3224            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3225            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3226           (SUST_B_3D_V4B16_TRAP Int64Regs:$s,
3227            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3228            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3229
3230 def : Pat<(int_nvvm_sust_b_3d_v4i32_trap
3231            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3232            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3233           (SUST_B_3D_V4B32_TRAP Int64Regs:$s,
3234            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3235            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3236
3237
3238
3239
3240 def : Pat<(int_nvvm_sust_p_1d_i8_trap
3241            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
3242           (SUST_P_1D_B8_TRAP Int64Regs:$s, Int32Regs:$x, Int16Regs:$r)>;
3243
3244 def : Pat<(int_nvvm_sust_p_1d_i16_trap
3245            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r),
3246           (SUST_P_1D_B16_TRAP Int64Regs:$s, Int32Regs:$x, Int16Regs:$r)>;
3247
3248 def : Pat<(int_nvvm_sust_p_1d_i32_trap
3249            Int64Regs:$s, Int32Regs:$x, Int32Regs:$r),
3250           (SUST_P_1D_B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$r)>;
3251
3252 def : Pat<(int_nvvm_sust_p_1d_v2i8_trap
3253            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
3254           (SUST_P_1D_V2B8_TRAP Int64Regs:$s, Int32Regs:$x,
3255            Int16Regs:$r, Int16Regs:$g)>;
3256
3257 def : Pat<(int_nvvm_sust_p_1d_v2i16_trap
3258            Int64Regs:$s, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
3259           (SUST_P_1D_V2B16_TRAP Int64Regs:$s, Int32Regs:$x,
3260            Int16Regs:$r, Int16Regs:$g)>;
3261
3262 def : Pat<(int_nvvm_sust_p_1d_v2i32_trap
3263            Int64Regs:$s, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g),
3264           (SUST_P_1D_V2B32_TRAP Int64Regs:$s, Int32Regs:$x,
3265            Int32Regs:$r, Int32Regs:$g)>;
3266
3267 def : Pat<(int_nvvm_sust_p_1d_v4i8_trap
3268            Int64Regs:$s, Int32Regs:$x,
3269            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3270           (SUST_P_1D_V4B8_TRAP Int64Regs:$s, Int32Regs:$x,
3271            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3272
3273 def : Pat<(int_nvvm_sust_p_1d_v4i16_trap
3274            Int64Regs:$s, Int32Regs:$x,
3275            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3276           (SUST_P_1D_V4B16_TRAP Int64Regs:$s, Int32Regs:$x,
3277            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3278
3279 def : Pat<(int_nvvm_sust_p_1d_v4i32_trap
3280            Int64Regs:$s, Int32Regs:$x,
3281            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3282           (SUST_P_1D_V4B32_TRAP Int64Regs:$s, Int32Regs:$x,
3283            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3284
3285
3286
3287 def : Pat<(int_nvvm_sust_p_1d_array_i8_trap
3288            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r),
3289           (SUST_P_1D_ARRAY_B8_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3290            Int16Regs:$r)>;
3291
3292 def : Pat<(int_nvvm_sust_p_1d_array_i16_trap
3293            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r),
3294           (SUST_P_1D_ARRAY_B16_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3295            Int16Regs:$r)>;
3296
3297 def : Pat<(int_nvvm_sust_p_1d_array_i32_trap
3298            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$r),
3299           (SUST_P_1D_ARRAY_B32_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3300            Int32Regs:$r)>;
3301
3302 def : Pat<(int_nvvm_sust_p_1d_array_v2i8_trap
3303           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
3304           (SUST_P_1D_ARRAY_V2B8_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3305            Int16Regs:$r, Int16Regs:$g)>;
3306
3307 def : Pat<(int_nvvm_sust_p_1d_array_v2i16_trap
3308           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int16Regs:$r, Int16Regs:$g),
3309           (SUST_P_1D_ARRAY_V2B16_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3310            Int16Regs:$r, Int16Regs:$g)>;
3311
3312 def : Pat<(int_nvvm_sust_p_1d_array_v2i32_trap
3313           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$r, Int32Regs:$g),
3314           (SUST_P_1D_ARRAY_V2B32_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3315            Int32Regs:$r, Int32Regs:$g)>;
3316
3317 def : Pat<(int_nvvm_sust_p_1d_array_v4i8_trap
3318            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3319            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3320           (SUST_P_1D_ARRAY_V4B8_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3321            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3322
3323 def : Pat<(int_nvvm_sust_p_1d_array_v4i16_trap
3324            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3325            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3326           (SUST_P_1D_ARRAY_V4B16_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3327            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3328
3329 def : Pat<(int_nvvm_sust_p_1d_array_v4i32_trap
3330            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3331            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3332           (SUST_P_1D_ARRAY_V4B32_TRAP Int64Regs:$s, Int32Regs:$l, Int32Regs:$x,
3333            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3334
3335
3336
3337 def : Pat<(int_nvvm_sust_p_2d_i8_trap
3338            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3339           (SUST_P_2D_B8_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3340            Int16Regs:$r)>;
3341
3342 def : Pat<(int_nvvm_sust_p_2d_i16_trap
3343            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3344           (SUST_P_2D_B16_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3345            Int16Regs:$r)>;
3346
3347 def : Pat<(int_nvvm_sust_p_2d_i32_trap
3348            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r),
3349           (SUST_P_2D_B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3350            Int32Regs:$r)>;
3351
3352 def : Pat<(int_nvvm_sust_p_2d_v2i8_trap
3353           Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r, Int16Regs:$g),
3354           (SUST_P_2D_V2B8_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3355            Int16Regs:$r, Int16Regs:$g)>;
3356
3357 def : Pat<(int_nvvm_sust_p_2d_v2i16_trap
3358           Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r, Int16Regs:$g),
3359           (SUST_P_2D_V2B16_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3360            Int16Regs:$r, Int16Regs:$g)>;
3361
3362 def : Pat<(int_nvvm_sust_p_2d_v2i32_trap
3363           Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r, Int32Regs:$g),
3364           (SUST_P_2D_V2B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3365            Int32Regs:$r, Int32Regs:$g)>;
3366
3367 def : Pat<(int_nvvm_sust_p_2d_v4i8_trap
3368            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3369            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3370           (SUST_P_2D_V4B8_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3371            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3372
3373 def : Pat<(int_nvvm_sust_p_2d_v4i16_trap
3374            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3375            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3376           (SUST_P_2D_V4B16_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3377            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3378
3379 def : Pat<(int_nvvm_sust_p_2d_v4i32_trap
3380            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3381            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3382           (SUST_P_2D_V4B32_TRAP Int64Regs:$s, Int32Regs:$x, Int32Regs:$y,
3383            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3384
3385
3386
3387 def : Pat<(int_nvvm_sust_p_2d_array_i8_trap
3388           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3389           (SUST_P_2D_ARRAY_B8_TRAP Int64Regs:$s,
3390            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3391            Int16Regs:$r)>;
3392
3393 def : Pat<(int_nvvm_sust_p_2d_array_i16_trap
3394           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int16Regs:$r),
3395           (SUST_P_2D_ARRAY_B16_TRAP Int64Regs:$s,
3396            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3397            Int16Regs:$r)>;
3398
3399 def : Pat<(int_nvvm_sust_p_2d_array_i32_trap
3400           Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r),
3401           (SUST_P_2D_ARRAY_B32_TRAP Int64Regs:$s,
3402            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3403            Int32Regs:$r)>;
3404
3405 def : Pat<(int_nvvm_sust_p_2d_array_v2i8_trap
3406            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3407            Int16Regs:$r, Int16Regs:$g),
3408           (SUST_P_2D_ARRAY_V2B8_TRAP Int64Regs:$s, Int32Regs:$l,
3409            Int32Regs:$x, Int32Regs:$y,
3410            Int16Regs:$r, Int16Regs:$g)>;
3411
3412 def : Pat<(int_nvvm_sust_p_2d_array_v2i16_trap
3413            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3414            Int16Regs:$r, Int16Regs:$g),
3415           (SUST_P_2D_ARRAY_V2B16_TRAP Int64Regs:$s, Int32Regs:$l,
3416            Int32Regs:$x, Int32Regs:$y,
3417            Int16Regs:$r, Int16Regs:$g)>;
3418
3419 def : Pat<(int_nvvm_sust_p_2d_array_v2i32_trap
3420            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y, Int32Regs:$r,
3421            Int32Regs:$g),
3422           (SUST_P_2D_ARRAY_V2B32_TRAP Int64Regs:$s, Int32Regs:$l,
3423            Int32Regs:$x, Int32Regs:$y, Int32Regs:$r, Int32Regs:$g)>;
3424
3425 def : Pat<(int_nvvm_sust_p_2d_array_v4i8_trap
3426            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3427            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3428           (SUST_P_2D_ARRAY_V4B8_TRAP Int64Regs:$s,
3429            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3430            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3431
3432 def : Pat<(int_nvvm_sust_p_2d_array_v4i16_trap
3433            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3434            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3435           (SUST_P_2D_ARRAY_V4B16_TRAP Int64Regs:$s,
3436            Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3437            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3438
3439 def : Pat<(int_nvvm_sust_p_2d_array_v4i32_trap
3440            Int64Regs:$s, Int32Regs:$l, Int32Regs:$x, Int32Regs:$y,
3441            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3442           (SUST_P_2D_ARRAY_V4B32_TRAP Int64Regs:$s, Int32Regs:$l,
3443            Int32Regs:$x, Int32Regs:$y,
3444            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3445
3446
3447
3448 def : Pat<(int_nvvm_sust_p_3d_i8_trap
3449            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3450            Int16Regs:$r),
3451           (SUST_P_3D_B8_TRAP Int64Regs:$s,
3452            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3453            Int16Regs:$r)>;
3454
3455 def : Pat<(int_nvvm_sust_p_3d_i16_trap
3456            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3457            Int16Regs:$r),
3458           (SUST_P_3D_B16_TRAP Int64Regs:$s,
3459            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3460            Int16Regs:$r)>;
3461
3462 def : Pat<(int_nvvm_sust_p_3d_i32_trap
3463            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3464            Int32Regs:$r),
3465           (SUST_P_3D_B32_TRAP Int64Regs:$s,
3466            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3467            Int32Regs:$r)>;
3468
3469 def : Pat<(int_nvvm_sust_p_3d_v2i8_trap
3470            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3471            Int16Regs:$r, Int16Regs:$g),
3472           (SUST_P_3D_V2B8_TRAP Int64Regs:$s,
3473            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3474            Int16Regs:$r, Int16Regs:$g)>;
3475
3476 def : Pat<(int_nvvm_sust_p_3d_v2i16_trap
3477            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3478            Int16Regs:$r, Int16Regs:$g),
3479           (SUST_P_3D_V2B16_TRAP Int64Regs:$s,
3480            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3481            Int16Regs:$r, Int16Regs:$g)>;
3482
3483 def : Pat<(int_nvvm_sust_p_3d_v2i32_trap
3484            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3485            Int32Regs:$r, Int32Regs:$g),
3486           (SUST_P_3D_V2B32_TRAP Int64Regs:$s,
3487            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3488            Int32Regs:$r, Int32Regs:$g)>;
3489
3490 def : Pat<(int_nvvm_sust_p_3d_v4i8_trap
3491            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3492            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3493           (SUST_P_3D_V4B8_TRAP Int64Regs:$s,
3494            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3495            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3496
3497 def : Pat<(int_nvvm_sust_p_3d_v4i16_trap
3498            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3499            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a),
3500           (SUST_P_3D_V4B16_TRAP Int64Regs:$s,
3501            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3502            Int16Regs:$r, Int16Regs:$g, Int16Regs:$b, Int16Regs:$a)>;
3503
3504 def : Pat<(int_nvvm_sust_p_3d_v4i32_trap
3505            Int64Regs:$s, Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3506            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a),
3507           (SUST_P_3D_V4B32_TRAP Int64Regs:$s,
3508            Int32Regs:$x, Int32Regs:$y, Int32Regs:$z,
3509            Int32Regs:$r, Int32Regs:$g, Int32Regs:$b, Int32Regs:$a)>;
3510
3511
3512
3513 //===-- Old PTX Back-end Intrinsics ---------------------------------------===//
3514
3515 // These intrinsics are handled to retain compatibility with the old backend.
3516
3517 // PTX Special Purpose Register Accessor Intrinsics
3518
3519 class PTX_READ_SPECIAL_REGISTER_R64<string regname, Intrinsic intop>
3520   : NVPTXInst<(outs Int64Regs:$d), (ins),
3521               !strconcat(!strconcat("mov.u64\t$d, %", regname), ";"),
3522               [(set Int64Regs:$d, (intop))]>;
3523
3524 class PTX_READ_SPECIAL_REGISTER_R32<string regname, Intrinsic intop>
3525   : NVPTXInst<(outs Int32Regs:$d), (ins),
3526               !strconcat(!strconcat("mov.u32\t$d, %", regname), ";"),
3527               [(set Int32Regs:$d, (intop))]>;
3528
3529 // TODO Add read vector-version of special registers
3530
3531 def PTX_READ_TID_X   : PTX_READ_SPECIAL_REGISTER_R32<"tid.x",
3532                                                      int_ptx_read_tid_x>;
3533 def PTX_READ_TID_Y   : PTX_READ_SPECIAL_REGISTER_R32<"tid.y",
3534                                                      int_ptx_read_tid_y>;
3535 def PTX_READ_TID_Z   : PTX_READ_SPECIAL_REGISTER_R32<"tid.z",
3536                                                      int_ptx_read_tid_z>;
3537 def PTX_READ_TID_W   : PTX_READ_SPECIAL_REGISTER_R32<"tid.w",
3538                                                      int_ptx_read_tid_w>;
3539
3540 def PTX_READ_NTID_X   : PTX_READ_SPECIAL_REGISTER_R32<"ntid.x",
3541                                                       int_ptx_read_ntid_x>;
3542 def PTX_READ_NTID_Y   : PTX_READ_SPECIAL_REGISTER_R32<"ntid.y",
3543                                                       int_ptx_read_ntid_y>;
3544 def PTX_READ_NTID_Z   : PTX_READ_SPECIAL_REGISTER_R32<"ntid.z",
3545                                                       int_ptx_read_ntid_z>;
3546 def PTX_READ_NTID_W   : PTX_READ_SPECIAL_REGISTER_R32<"ntid.w",
3547                                                       int_ptx_read_ntid_w>;
3548
3549 def PTX_READ_LANEID  : PTX_READ_SPECIAL_REGISTER_R32<"laneid",
3550                                                      int_ptx_read_laneid>;
3551 def PTX_READ_WARPID  : PTX_READ_SPECIAL_REGISTER_R32<"warpid",
3552                                                      int_ptx_read_warpid>;
3553 def PTX_READ_NWARPID : PTX_READ_SPECIAL_REGISTER_R32<"nwarpid",
3554                                                      int_ptx_read_nwarpid>;
3555
3556 def PTX_READ_CTAID_X   : PTX_READ_SPECIAL_REGISTER_R32<"ctaid.x",
3557                                                        int_ptx_read_ctaid_x>;
3558 def PTX_READ_CTAID_Y   : PTX_READ_SPECIAL_REGISTER_R32<"ctaid.y",
3559                                                        int_ptx_read_ctaid_y>;
3560 def PTX_READ_CTAID_Z   : PTX_READ_SPECIAL_REGISTER_R32<"ctaid.z",
3561                                                        int_ptx_read_ctaid_z>;
3562 def PTX_READ_CTAID_W   : PTX_READ_SPECIAL_REGISTER_R32<"ctaid.w",
3563                                                        int_ptx_read_ctaid_w>;
3564
3565 def PTX_READ_NCTAID_X   : PTX_READ_SPECIAL_REGISTER_R32<"nctaid.x",
3566                                                         int_ptx_read_nctaid_x>;
3567 def PTX_READ_NCTAID_Y   : PTX_READ_SPECIAL_REGISTER_R32<"nctaid.y",
3568                                                         int_ptx_read_nctaid_y>;
3569 def PTX_READ_NCTAID_Z   : PTX_READ_SPECIAL_REGISTER_R32<"nctaid.z",
3570                                                         int_ptx_read_nctaid_z>;
3571 def PTX_READ_NCTAID_W   : PTX_READ_SPECIAL_REGISTER_R32<"nctaid.w",
3572                                                         int_ptx_read_nctaid_w>;
3573
3574 def PTX_READ_SMID  : PTX_READ_SPECIAL_REGISTER_R32<"smid",
3575                                                    int_ptx_read_smid>;
3576 def PTX_READ_NSMID  : PTX_READ_SPECIAL_REGISTER_R32<"nsmid",
3577                                                     int_ptx_read_nsmid>;
3578 def PTX_READ_GRIDID  : PTX_READ_SPECIAL_REGISTER_R32<"gridid",
3579                                                      int_ptx_read_gridid>;
3580
3581 def PTX_READ_LANEMASK_EQ
3582   : PTX_READ_SPECIAL_REGISTER_R32<"lanemask_eq", int_ptx_read_lanemask_eq>;
3583 def PTX_READ_LANEMASK_LE
3584   : PTX_READ_SPECIAL_REGISTER_R32<"lanemask_le", int_ptx_read_lanemask_le>;
3585 def PTX_READ_LANEMASK_LT
3586   : PTX_READ_SPECIAL_REGISTER_R32<"lanemask_lt", int_ptx_read_lanemask_lt>;
3587 def PTX_READ_LANEMASK_GE
3588   : PTX_READ_SPECIAL_REGISTER_R32<"lanemask_ge", int_ptx_read_lanemask_ge>;
3589 def PTX_READ_LANEMASK_GT
3590   : PTX_READ_SPECIAL_REGISTER_R32<"lanemask_gt", int_ptx_read_lanemask_gt>;
3591
3592 def PTX_READ_CLOCK
3593   : PTX_READ_SPECIAL_REGISTER_R32<"clock", int_ptx_read_clock>;
3594 def PTX_READ_CLOCK64
3595   : PTX_READ_SPECIAL_REGISTER_R64<"clock64", int_ptx_read_clock64>;
3596
3597 def PTX_READ_PM0 : PTX_READ_SPECIAL_REGISTER_R32<"pm0", int_ptx_read_pm0>;
3598 def PTX_READ_PM1 : PTX_READ_SPECIAL_REGISTER_R32<"pm1", int_ptx_read_pm1>;
3599 def PTX_READ_PM2 : PTX_READ_SPECIAL_REGISTER_R32<"pm2", int_ptx_read_pm2>;
3600 def PTX_READ_PM3 : PTX_READ_SPECIAL_REGISTER_R32<"pm3", int_ptx_read_pm3>;
3601
3602 // PTX Parallel Synchronization and Communication Intrinsics
3603
3604 def PTX_BAR_SYNC : NVPTXInst<(outs), (ins i32imm:$i), "bar.sync\t$i;",
3605                              [(int_ptx_bar_sync imm:$i)]>;