1 //===- NVPTXRegisterInfo.cpp - NVPTX Register Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the NVPTX implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "nvptx-reg-info"
17 #include "NVPTXRegisterInfo.h"
18 #include "NVPTXSubtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/MC/MachineLocation.h"
24 #include "llvm/Target/TargetInstrInfo.h"
31 std::string getNVPTXRegClassName (TargetRegisterClass const *RC) {
32 if (RC == &NVPTX::Float32RegsRegClass) {
35 if (RC == &NVPTX::Float64RegsRegClass) {
38 else if (RC == &NVPTX::Int64RegsRegClass) {
41 else if (RC == &NVPTX::Int32RegsRegClass) {
44 else if (RC == &NVPTX::Int16RegsRegClass) {
47 // Int8Regs become 16-bit registers in PTX
48 else if (RC == &NVPTX::Int8RegsRegClass) {
51 else if (RC == &NVPTX::Int1RegsRegClass) {
54 else if (RC == &NVPTX::SpecialRegsRegClass) {
57 else if (RC == &NVPTX::V2F32RegsRegClass) {
60 else if (RC == &NVPTX::V4F32RegsRegClass) {
63 else if (RC == &NVPTX::V2I32RegsRegClass) {
66 else if (RC == &NVPTX::V4I32RegsRegClass) {
69 else if (RC == &NVPTX::V2F64RegsRegClass) {
72 else if (RC == &NVPTX::V2I64RegsRegClass) {
75 else if (RC == &NVPTX::V2I16RegsRegClass) {
78 else if (RC == &NVPTX::V4I16RegsRegClass) {
81 else if (RC == &NVPTX::V2I8RegsRegClass) {
84 else if (RC == &NVPTX::V4I8RegsRegClass) {
93 std::string getNVPTXRegClassStr (TargetRegisterClass const *RC) {
94 if (RC == &NVPTX::Float32RegsRegClass) {
97 if (RC == &NVPTX::Float64RegsRegClass) {
100 else if (RC == &NVPTX::Int64RegsRegClass) {
103 else if (RC == &NVPTX::Int32RegsRegClass) {
106 else if (RC == &NVPTX::Int16RegsRegClass) {
109 else if (RC == &NVPTX::Int8RegsRegClass) {
112 else if (RC == &NVPTX::Int1RegsRegClass) {
115 else if (RC == &NVPTX::SpecialRegsRegClass) {
118 else if (RC == &NVPTX::V2F32RegsRegClass) {
121 else if (RC == &NVPTX::V4F32RegsRegClass) {
124 else if (RC == &NVPTX::V2I32RegsRegClass) {
127 else if (RC == &NVPTX::V4I32RegsRegClass) {
130 else if (RC == &NVPTX::V2F64RegsRegClass) {
133 else if (RC == &NVPTX::V2I64RegsRegClass) {
136 else if (RC == &NVPTX::V2I16RegsRegClass) {
139 else if (RC == &NVPTX::V4I16RegsRegClass) {
142 else if (RC == &NVPTX::V2I8RegsRegClass) {
145 else if (RC == &NVPTX::V4I8RegsRegClass) {
154 bool isNVPTXVectorRegClass(TargetRegisterClass const *RC) {
155 if (RC->getID() == NVPTX::V2F32RegsRegClassID)
157 if (RC->getID() == NVPTX::V2F64RegsRegClassID)
159 if (RC->getID() == NVPTX::V2I16RegsRegClassID)
161 if (RC->getID() == NVPTX::V2I32RegsRegClassID)
163 if (RC->getID() == NVPTX::V2I64RegsRegClassID)
165 if (RC->getID() == NVPTX::V2I8RegsRegClassID)
167 if (RC->getID() == NVPTX::V4F32RegsRegClassID)
169 if (RC->getID() == NVPTX::V4I16RegsRegClassID)
171 if (RC->getID() == NVPTX::V4I32RegsRegClassID)
173 if (RC->getID() == NVPTX::V4I8RegsRegClassID)
178 std::string getNVPTXElemClassName(TargetRegisterClass const *RC) {
179 if (RC->getID() == NVPTX::V2F32RegsRegClassID)
180 return getNVPTXRegClassName(&NVPTX::Float32RegsRegClass);
181 if (RC->getID() == NVPTX::V2F64RegsRegClassID)
182 return getNVPTXRegClassName(&NVPTX::Float64RegsRegClass);
183 if (RC->getID() == NVPTX::V2I16RegsRegClassID)
184 return getNVPTXRegClassName(&NVPTX::Int16RegsRegClass);
185 if (RC->getID() == NVPTX::V2I32RegsRegClassID)
186 return getNVPTXRegClassName(&NVPTX::Int32RegsRegClass);
187 if (RC->getID() == NVPTX::V2I64RegsRegClassID)
188 return getNVPTXRegClassName(&NVPTX::Int64RegsRegClass);
189 if (RC->getID() == NVPTX::V2I8RegsRegClassID)
190 return getNVPTXRegClassName(&NVPTX::Int8RegsRegClass);
191 if (RC->getID() == NVPTX::V4F32RegsRegClassID)
192 return getNVPTXRegClassName(&NVPTX::Float32RegsRegClass);
193 if (RC->getID() == NVPTX::V4I16RegsRegClassID)
194 return getNVPTXRegClassName(&NVPTX::Int16RegsRegClass);
195 if (RC->getID() == NVPTX::V4I32RegsRegClassID)
196 return getNVPTXRegClassName(&NVPTX::Int32RegsRegClass);
197 if (RC->getID() == NVPTX::V4I8RegsRegClassID)
198 return getNVPTXRegClassName(&NVPTX::Int8RegsRegClass);
199 assert(0 && "Not a vector register class");
200 return "Unsupported";
203 const TargetRegisterClass *getNVPTXElemClass(TargetRegisterClass const *RC) {
204 if (RC->getID() == NVPTX::V2F32RegsRegClassID)
205 return (&NVPTX::Float32RegsRegClass);
206 if (RC->getID() == NVPTX::V2F64RegsRegClassID)
207 return (&NVPTX::Float64RegsRegClass);
208 if (RC->getID() == NVPTX::V2I16RegsRegClassID)
209 return (&NVPTX::Int16RegsRegClass);
210 if (RC->getID() == NVPTX::V2I32RegsRegClassID)
211 return (&NVPTX::Int32RegsRegClass);
212 if (RC->getID() == NVPTX::V2I64RegsRegClassID)
213 return (&NVPTX::Int64RegsRegClass);
214 if (RC->getID() == NVPTX::V2I8RegsRegClassID)
215 return (&NVPTX::Int8RegsRegClass);
216 if (RC->getID() == NVPTX::V4F32RegsRegClassID)
217 return (&NVPTX::Float32RegsRegClass);
218 if (RC->getID() == NVPTX::V4I16RegsRegClassID)
219 return (&NVPTX::Int16RegsRegClass);
220 if (RC->getID() == NVPTX::V4I32RegsRegClassID)
221 return (&NVPTX::Int32RegsRegClass);
222 if (RC->getID() == NVPTX::V4I8RegsRegClassID)
223 return (&NVPTX::Int8RegsRegClass);
224 assert(0 && "Not a vector register class");
228 int getNVPTXVectorSize(TargetRegisterClass const *RC) {
229 if (RC->getID() == NVPTX::V2F32RegsRegClassID)
231 if (RC->getID() == NVPTX::V2F64RegsRegClassID)
233 if (RC->getID() == NVPTX::V2I16RegsRegClassID)
235 if (RC->getID() == NVPTX::V2I32RegsRegClassID)
237 if (RC->getID() == NVPTX::V2I64RegsRegClassID)
239 if (RC->getID() == NVPTX::V2I8RegsRegClassID)
241 if (RC->getID() == NVPTX::V4F32RegsRegClassID)
243 if (RC->getID() == NVPTX::V4I16RegsRegClassID)
245 if (RC->getID() == NVPTX::V4I32RegsRegClassID)
247 if (RC->getID() == NVPTX::V4I8RegsRegClassID)
249 assert(0 && "Not a vector register class");
254 NVPTXRegisterInfo::NVPTXRegisterInfo(const TargetInstrInfo &tii,
255 const NVPTXSubtarget &st)
256 : NVPTXGenRegisterInfo(0),
259 Is64Bit = st.is64Bit();
263 #define GET_REGINFO_TARGET_DESC
264 #include "NVPTXGenRegisterInfo.inc"
266 /// NVPTX Callee Saved Registers
267 const uint16_t* NVPTXRegisterInfo::
268 getCalleeSavedRegs(const MachineFunction *MF) const {
269 static const uint16_t CalleeSavedRegs[] = { 0 };
270 return CalleeSavedRegs;
273 // NVPTX Callee Saved Reg Classes
274 const TargetRegisterClass* const*
275 NVPTXRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
276 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
277 return CalleeSavedRegClasses;
280 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
281 BitVector Reserved(getNumRegs());
285 void NVPTXRegisterInfo::
286 eliminateFrameIndex(MachineBasicBlock::iterator II,
288 RegScavenger *RS) const {
289 assert(SPAdj == 0 && "Unexpected");
292 MachineInstr &MI = *II;
293 while (!MI.getOperand(i).isFI()) {
295 assert(i < MI.getNumOperands() &&
296 "Instr doesn't have FrameIndex operand!");
299 int FrameIndex = MI.getOperand(i).getIndex();
301 MachineFunction &MF = *MI.getParent()->getParent();
302 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
303 MI.getOperand(i+1).getImm();
305 // Using I0 as the frame pointer
306 MI.getOperand(i).ChangeToRegister(NVPTX::VRFrame, false);
307 MI.getOperand(i+1).ChangeToImmediate(Offset);
311 int NVPTXRegisterInfo::
312 getDwarfRegNum(unsigned RegNum, bool isEH) const {
316 unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
317 return NVPTX::VRFrame;
320 unsigned NVPTXRegisterInfo::getRARegister() const {
324 // This function eliminates ADJCALLSTACKDOWN,
325 // ADJCALLSTACKUP pseudo instructions
326 void NVPTXRegisterInfo::
327 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
328 MachineBasicBlock::iterator I) const {
329 // Simply discard ADJCALLSTACKDOWN,
330 // ADJCALLSTACKUP instructions.