1 //===- NVPTXRegisterInfo.cpp - NVPTX Register Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the NVPTX implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "nvptx-reg-info"
16 #include "NVPTXRegisterInfo.h"
18 #include "NVPTXSubtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/MC/MachineLocation.h"
24 #include "llvm/Target/TargetInstrInfo.h"
31 std::string getNVPTXRegClassName (TargetRegisterClass const *RC) {
32 if (RC == &NVPTX::Float32RegsRegClass) {
35 if (RC == &NVPTX::Float64RegsRegClass) {
38 else if (RC == &NVPTX::Int64RegsRegClass) {
41 else if (RC == &NVPTX::Int32RegsRegClass) {
44 else if (RC == &NVPTX::Int16RegsRegClass) {
47 // Int8Regs become 16-bit registers in PTX
48 else if (RC == &NVPTX::Int8RegsRegClass) {
51 else if (RC == &NVPTX::Int1RegsRegClass) {
54 else if (RC == &NVPTX::SpecialRegsRegClass) {
63 std::string getNVPTXRegClassStr (TargetRegisterClass const *RC) {
64 if (RC == &NVPTX::Float32RegsRegClass) {
67 if (RC == &NVPTX::Float64RegsRegClass) {
70 else if (RC == &NVPTX::Int64RegsRegClass) {
73 else if (RC == &NVPTX::Int32RegsRegClass) {
76 else if (RC == &NVPTX::Int16RegsRegClass) {
79 else if (RC == &NVPTX::Int8RegsRegClass) {
82 else if (RC == &NVPTX::Int1RegsRegClass) {
85 else if (RC == &NVPTX::SpecialRegsRegClass) {
95 NVPTXRegisterInfo::NVPTXRegisterInfo(const TargetInstrInfo &tii,
96 const NVPTXSubtarget &st)
97 : NVPTXGenRegisterInfo(0),
98 Is64Bit(st.is64Bit()) {}
100 #define GET_REGINFO_TARGET_DESC
101 #include "NVPTXGenRegisterInfo.inc"
103 /// NVPTX Callee Saved Registers
104 const uint16_t* NVPTXRegisterInfo::
105 getCalleeSavedRegs(const MachineFunction *MF) const {
106 static const uint16_t CalleeSavedRegs[] = { 0 };
107 return CalleeSavedRegs;
110 // NVPTX Callee Saved Reg Classes
111 const TargetRegisterClass* const*
112 NVPTXRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
113 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
114 return CalleeSavedRegClasses;
117 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
118 BitVector Reserved(getNumRegs());
122 void NVPTXRegisterInfo::
123 eliminateFrameIndex(MachineBasicBlock::iterator II,
124 int SPAdj, unsigned FIOperandNum,
125 RegScavenger *RS) const {
126 assert(SPAdj == 0 && "Unexpected");
128 MachineInstr &MI = *II;
129 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
131 MachineFunction &MF = *MI.getParent()->getParent();
132 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
133 MI.getOperand(FIOperandNum+1).getImm();
135 // Using I0 as the frame pointer
136 MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
137 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
140 int NVPTXRegisterInfo::
141 getDwarfRegNum(unsigned RegNum, bool isEH) const {
145 unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
146 return NVPTX::VRFrame;
149 unsigned NVPTXRegisterInfo::getRARegister() const {