1 //===- NVPTXRegisterInfo.cpp - NVPTX Register Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the NVPTX implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXRegisterInfo.h"
16 #include "NVPTXSubtarget.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/MC/MachineLocation.h"
22 #include "llvm/Target/TargetInstrInfo.h"
26 #define DEBUG_TYPE "nvptx-reg-info"
29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) {
30 if (RC == &NVPTX::Float32RegsRegClass) {
33 if (RC == &NVPTX::Float64RegsRegClass) {
35 } else if (RC == &NVPTX::Int64RegsRegClass) {
37 } else if (RC == &NVPTX::Int32RegsRegClass) {
39 } else if (RC == &NVPTX::Int16RegsRegClass) {
41 } else if (RC == &NVPTX::Int1RegsRegClass) {
43 } else if (RC == &NVPTX::SpecialRegsRegClass) {
51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) {
52 if (RC == &NVPTX::Float32RegsRegClass) {
55 if (RC == &NVPTX::Float64RegsRegClass) {
57 } else if (RC == &NVPTX::Int64RegsRegClass) {
59 } else if (RC == &NVPTX::Int32RegsRegClass) {
61 } else if (RC == &NVPTX::Int16RegsRegClass) {
63 } else if (RC == &NVPTX::Int1RegsRegClass) {
65 } else if (RC == &NVPTX::SpecialRegsRegClass) {
74 NVPTXRegisterInfo::NVPTXRegisterInfo(const NVPTXSubtarget &st)
75 : NVPTXGenRegisterInfo(0), Is64Bit(st.is64Bit()) {}
77 #define GET_REGINFO_TARGET_DESC
78 #include "NVPTXGenRegisterInfo.inc"
80 /// NVPTX Callee Saved Registers
82 NVPTXRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
83 static const MCPhysReg CalleeSavedRegs[] = { 0 };
84 return CalleeSavedRegs;
87 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
88 BitVector Reserved(getNumRegs());
92 void NVPTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
93 int SPAdj, unsigned FIOperandNum,
94 RegScavenger *RS) const {
95 assert(SPAdj == 0 && "Unexpected");
97 MachineInstr &MI = *II;
98 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
100 MachineFunction &MF = *MI.getParent()->getParent();
101 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
102 MI.getOperand(FIOperandNum + 1).getImm();
104 // Using I0 as the frame pointer
105 MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
106 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
109 unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
110 return NVPTX::VRFrame;