1 //===-- NVPTXRegisterInfo.td - NVPTX Register defs ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the PTX register file
12 //===----------------------------------------------------------------------===//
14 class NVPTXReg<string n> : Register<n> {
15 let Namespace = "NVPTX";
18 class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList>
19 : RegisterClass <"NVPTX", regTypes, alignment, regList>;
21 //===----------------------------------------------------------------------===//
23 //===----------------------------------------------------------------------===//
25 // Special Registers used as stack pointer
26 def VRFrame : NVPTXReg<"%SP">;
27 def VRFrameLocal : NVPTXReg<"%SPL">;
29 // Special Registers used as the stack
30 def VRDepot : NVPTXReg<"%Depot">;
32 foreach i = 0-395 in {
33 def P#i : NVPTXReg<"%p"#i>; // Predicate
34 def RC#i : NVPTXReg<"%rc"#i>; // 8-bit
35 def RS#i : NVPTXReg<"%rs"#i>; // 16-bit
36 def R#i : NVPTXReg<"%r"#i>; // 32-bit
37 def RL#i : NVPTXReg<"%rl"#i>; // 64-bit
38 def F#i : NVPTXReg<"%f"#i>; // 32-bit float
39 def FL#i : NVPTXReg<"%fl"#i>; // 64-bit float
42 def ia#i : NVPTXReg<"%ia"#i>;
43 def la#i : NVPTXReg<"%la"#i>;
44 def fa#i : NVPTXReg<"%fa"#i>;
45 def da#i : NVPTXReg<"%da"#i>;
48 //===----------------------------------------------------------------------===//
50 //===----------------------------------------------------------------------===//
51 def Int1Regs : NVPTXRegClass<[i1], 8, (add (sequence "P%u", 0, 395))>;
52 def Int8Regs : NVPTXRegClass<[i8], 8, (add (sequence "RC%u", 0, 395))>;
53 def Int16Regs : NVPTXRegClass<[i16], 16, (add (sequence "RS%u", 0, 395))>;
54 def Int32Regs : NVPTXRegClass<[i32], 32, (add (sequence "R%u", 0, 395))>;
55 def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%u", 0, 395))>;
56 def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%u", 0, 395))>;
57 def Float64Regs : NVPTXRegClass<[f64], 64, (add (sequence "FL%u", 0, 395))>;
58 def Int32ArgRegs : NVPTXRegClass<[i32], 32, (add (sequence "ia%u", 0, 395))>;
59 def Int64ArgRegs : NVPTXRegClass<[i64], 64, (add (sequence "la%u", 0, 395))>;
60 def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%u", 0, 395))>;
61 def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%u", 0, 395))>;
63 // Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used.
64 def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame, VRDepot)>;