1 //===-- NVPTXRegisterInfo.td - NVPTX Register defs ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the PTX register file
12 //===----------------------------------------------------------------------===//
14 class NVPTXReg<string n> : Register<n> {
15 let Namespace = "NVPTX";
18 class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList>
19 : RegisterClass <"NVPTX", regTypes, alignment, regList>;
21 //===----------------------------------------------------------------------===//
23 //===----------------------------------------------------------------------===//
25 // Special Registers used as stack pointer
26 def VRFrame : NVPTXReg<"%SP">;
27 def VRFrameLocal : NVPTXReg<"%SPL">;
29 // Special Registers used as the stack
30 def VRDepot : NVPTXReg<"%Depot">;
32 foreach i = 0-395 in {
33 def P#i : NVPTXReg<"%p"#i>; // Predicate
34 def RC#i : NVPTXReg<"%rc"#i>; // 8-bit
35 def RS#i : NVPTXReg<"%rs"#i>; // 16-bit
36 def R#i : NVPTXReg<"%r"#i>; // 32-bit
37 def RL#i : NVPTXReg<"%rl"#i>; // 64-bit
38 def F#i : NVPTXReg<"%f"#i>; // 32-bit float
39 def FL#i : NVPTXReg<"%fl"#i>; // 64-bit float
41 foreach s = [ "2b8", "2b16", "2b32", "2b64", "4b8", "4b16", "4b32" ] in
42 def v#s#_#i : NVPTXReg<"%v"#s#"_"#i>;
45 def ia#i : NVPTXReg<"%ia"#i>;
46 def la#i : NVPTXReg<"%la"#i>;
47 def fa#i : NVPTXReg<"%fa"#i>;
48 def da#i : NVPTXReg<"%da"#i>;
51 //===----------------------------------------------------------------------===//
53 //===----------------------------------------------------------------------===//
54 def Int1Regs : NVPTXRegClass<[i1], 8, (add (sequence "P%u", 0, 395))>;
55 def Int8Regs : NVPTXRegClass<[i8], 8, (add (sequence "RC%u", 0, 395))>;
56 def Int16Regs : NVPTXRegClass<[i16], 16, (add (sequence "RS%u", 0, 395))>;
57 def Int32Regs : NVPTXRegClass<[i32], 32, (add (sequence "R%u", 0, 395))>;
58 def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%u", 0, 395))>;
59 def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%u", 0, 395))>;
60 def Float64Regs : NVPTXRegClass<[f64], 64, (add (sequence "FL%u", 0, 395))>;
61 def Int32ArgRegs : NVPTXRegClass<[i32], 32, (add (sequence "ia%u", 0, 395))>;
62 def Int64ArgRegs : NVPTXRegClass<[i64], 64, (add (sequence "la%u", 0, 395))>;
63 def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%u", 0, 395))>;
64 def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%u", 0, 395))>;
66 // Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used.
67 def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame, VRDepot)>;
69 class NVPTXVecRegClass<list<ValueType> regTypes, int alignment, dag regList,
73 : NVPTXRegClass<regTypes, alignment, regList>
75 NVPTXRegClass scalarClass=sClass;
80 : NVPTXVecRegClass<[v2f32], 64, (add (sequence "v2b32_%u", 0, 395)),
81 Float32Regs, 2, ".v2.f32">;
83 : NVPTXVecRegClass<[v4f32], 128, (add (sequence "v4b32_%u", 0, 395)),
84 Float32Regs, 4, ".v4.f32">;
86 : NVPTXVecRegClass<[v2i32], 64, (add (sequence "v2b32_%u", 0, 395)),
87 Int32Regs, 2, ".v2.u32">;
89 : NVPTXVecRegClass<[v4i32], 128, (add (sequence "v4b32_%u", 0, 395)),
90 Int32Regs, 4, ".v4.u32">;
92 : NVPTXVecRegClass<[v2f64], 128, (add (sequence "v2b64_%u", 0, 395)),
93 Float64Regs, 2, ".v2.f64">;
95 : NVPTXVecRegClass<[v2i64], 128, (add (sequence "v2b64_%u", 0, 395)),
96 Int64Regs, 2, ".v2.u64">;
98 : NVPTXVecRegClass<[v2i16], 32, (add (sequence "v2b16_%u", 0, 395)),
99 Int16Regs, 2, ".v2.u16">;
101 : NVPTXVecRegClass<[v4i16], 64, (add (sequence "v4b16_%u", 0, 395)),
102 Int16Regs, 4, ".v4.u16">;
104 : NVPTXVecRegClass<[v2i8], 16, (add (sequence "v2b8_%u", 0, 395)),
105 Int8Regs, 2, ".v2.u8">;
107 : NVPTXVecRegClass<[v4i8], 32, (add (sequence "v4b8_%u", 0, 395)),
108 Int8Regs, 4, ".v4.u8">;