1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "llvm/ADT/OwningPtr.h"
20 #include "llvm/Analysis/Passes.h"
21 #include "llvm/CodeGen/AsmPrinter.h"
22 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/IRPrintingPasses.h"
27 #include "llvm/IR/Verifier.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCStreamer.h"
31 #include "llvm/MC/MCSubtargetInfo.h"
32 #include "llvm/PassManager.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/FormattedStream.h"
36 #include "llvm/Support/TargetRegistry.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetLowering.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
44 #include "llvm/Target/TargetSubtargetInfo.h"
45 #include "llvm/Transforms/Scalar.h"
50 void initializeNVVMReflectPass(PassRegistry&);
51 void initializeGenericToNVVMPass(PassRegistry&);
52 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
53 void initializeNVPTXFavorNonGenericAddrSpacesPass(PassRegistry &);
56 extern "C" void LLVMInitializeNVPTXTarget() {
57 // Register the target.
58 RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
59 RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
61 // FIXME: This pass is really intended to be invoked during IR optimization,
62 // but it's very NVPTX-specific.
63 initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
64 initializeGenericToNVVMPass(*PassRegistry::getPassRegistry());
65 initializeNVPTXAssignValidGlobalNamesPass(*PassRegistry::getPassRegistry());
66 initializeNVPTXFavorNonGenericAddrSpacesPass(
67 *PassRegistry::getPassRegistry());
70 static std::string computeDataLayout(const NVPTXSubtarget &ST) {
71 std::string Ret = "e";
76 Ret += "-i64:64-v16:16-v32:32-n16:32:64";
81 NVPTXTargetMachine::NVPTXTargetMachine(
82 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
83 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
84 CodeGenOpt::Level OL, bool is64bit)
85 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
86 Subtarget(TT, CPU, FS, is64bit), DL(computeDataLayout(Subtarget)),
87 InstrInfo(*this), TLInfo(*this), TSInfo(*this),
89 *this, is64bit) /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ {
93 void NVPTXTargetMachine32::anchor() {}
95 NVPTXTargetMachine32::NVPTXTargetMachine32(
96 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
97 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
99 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
101 void NVPTXTargetMachine64::anchor() {}
103 NVPTXTargetMachine64::NVPTXTargetMachine64(
104 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
105 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
106 CodeGenOpt::Level OL)
107 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
110 class NVPTXPassConfig : public TargetPassConfig {
112 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
113 : TargetPassConfig(TM, PM) {}
115 NVPTXTargetMachine &getNVPTXTargetMachine() const {
116 return getTM<NVPTXTargetMachine>();
119 virtual void addIRPasses();
120 virtual bool addInstSelector();
121 virtual bool addPreRegAlloc();
122 virtual bool addPostRegAlloc();
124 virtual FunctionPass *createTargetRegisterAllocator(bool) override;
125 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
126 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
128 } // end anonymous namespace
130 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
131 NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
135 void NVPTXPassConfig::addIRPasses() {
136 // The following passes are known to not play well with virtual regs hanging
137 // around after register allocation (which in our case, is *all* registers).
138 // We explicitly disable them here. We do, however, need some functionality
139 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
140 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
141 disablePass(&PrologEpilogCodeInserterID);
142 disablePass(&MachineCopyPropagationID);
143 disablePass(&BranchFolderPassID);
144 disablePass(&TailDuplicateID);
146 addPass(createNVPTXImageOptimizerPass());
147 TargetPassConfig::addIRPasses();
148 addPass(createNVPTXAssignValidGlobalNamesPass());
149 addPass(createGenericToNVVMPass());
150 addPass(createNVPTXFavorNonGenericAddrSpacesPass());
151 // The FavorNonGenericAddrSpaces pass may remove instructions and leave some
152 // values unused. Therefore, we run a DCE pass right afterwards. We could
153 // remove unused values in an ad-hoc manner, but it requires manual work and
154 // might be error-prone.
155 addPass(createDeadCodeEliminationPass());
158 bool NVPTXPassConfig::addInstSelector() {
159 const NVPTXSubtarget &ST =
160 getTM<NVPTXTargetMachine>().getSubtarget<NVPTXSubtarget>();
162 addPass(createLowerAggrCopies());
163 addPass(createAllocaHoisting());
164 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
166 if (!ST.hasImageHandles())
167 addPass(createNVPTXReplaceImageHandlesPass());
172 bool NVPTXPassConfig::addPreRegAlloc() { return false; }
173 bool NVPTXPassConfig::addPostRegAlloc() {
174 addPass(createNVPTXPrologEpilogPass());
178 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
179 return 0; // No reg alloc
182 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
183 assert(!RegAllocPass && "NVPTX uses no regalloc!");
184 addPass(&PHIEliminationID);
185 addPass(&TwoAddressInstructionPassID);
188 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
189 assert(!RegAllocPass && "NVPTX uses no regalloc!");
191 addPass(&ProcessImplicitDefsID);
192 addPass(&LiveVariablesID);
193 addPass(&MachineLoopInfoID);
194 addPass(&PHIEliminationID);
196 addPass(&TwoAddressInstructionPassID);
197 addPass(&RegisterCoalescerID);
199 // PreRA instruction scheduling.
200 if (addPass(&MachineSchedulerID))
201 printAndVerify("After Machine Scheduling");
204 addPass(&StackSlotColoringID);
206 // FIXME: Needs physical registers
207 //addPass(&PostRAMachineLICMID);
209 printAndVerify("After StackSlotColoring");