1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "llvm/Analysis/Passes.h"
20 #include "llvm/CodeGen/AsmPrinter.h"
21 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/IRPrintingPasses.h"
26 #include "llvm/IR/Verifier.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCStreamer.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/PassManager.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/FormattedStream.h"
35 #include "llvm/Support/TargetRegistry.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetLowering.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetSubtargetInfo.h"
44 #include "llvm/Transforms/Scalar.h"
49 void initializeNVVMReflectPass(PassRegistry&);
50 void initializeGenericToNVVMPass(PassRegistry&);
51 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
52 void initializeNVPTXFavorNonGenericAddrSpacesPass(PassRegistry &);
53 void initializeNVPTXLowerStructArgsPass(PassRegistry &);
56 extern "C" void LLVMInitializeNVPTXTarget() {
57 // Register the target.
58 RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
59 RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
61 // FIXME: This pass is really intended to be invoked during IR optimization,
62 // but it's very NVPTX-specific.
63 initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
64 initializeGenericToNVVMPass(*PassRegistry::getPassRegistry());
65 initializeNVPTXAssignValidGlobalNamesPass(*PassRegistry::getPassRegistry());
66 initializeNVPTXFavorNonGenericAddrSpacesPass(
67 *PassRegistry::getPassRegistry());
68 initializeNVPTXLowerStructArgsPass(*PassRegistry::getPassRegistry());
71 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
72 StringRef CPU, StringRef FS,
73 const TargetOptions &Options,
74 Reloc::Model RM, CodeModel::Model CM,
75 CodeGenOpt::Level OL, bool is64bit)
76 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
77 Subtarget(TT, CPU, FS, *this, is64bit) {
81 void NVPTXTargetMachine32::anchor() {}
83 NVPTXTargetMachine32::NVPTXTargetMachine32(
84 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
85 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
87 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
89 void NVPTXTargetMachine64::anchor() {}
91 NVPTXTargetMachine64::NVPTXTargetMachine64(
92 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
93 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
95 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
98 class NVPTXPassConfig : public TargetPassConfig {
100 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
101 : TargetPassConfig(TM, PM) {}
103 NVPTXTargetMachine &getNVPTXTargetMachine() const {
104 return getTM<NVPTXTargetMachine>();
107 void addIRPasses() override;
108 bool addInstSelector() override;
109 bool addPreRegAlloc() override;
110 bool addPostRegAlloc() override;
111 void addMachineSSAOptimization() override;
113 FunctionPass *createTargetRegisterAllocator(bool) override;
114 void addFastRegAlloc(FunctionPass *RegAllocPass) override;
115 void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
117 } // end anonymous namespace
119 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
120 NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
124 void NVPTXPassConfig::addIRPasses() {
125 // The following passes are known to not play well with virtual regs hanging
126 // around after register allocation (which in our case, is *all* registers).
127 // We explicitly disable them here. We do, however, need some functionality
128 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
129 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
130 disablePass(&PrologEpilogCodeInserterID);
131 disablePass(&MachineCopyPropagationID);
132 disablePass(&BranchFolderPassID);
133 disablePass(&TailDuplicateID);
135 addPass(createNVPTXImageOptimizerPass());
136 TargetPassConfig::addIRPasses();
137 addPass(createNVPTXAssignValidGlobalNamesPass());
138 addPass(createGenericToNVVMPass());
139 addPass(createNVPTXFavorNonGenericAddrSpacesPass());
140 addPass(createSeparateConstOffsetFromGEPPass());
141 // The SeparateConstOffsetFromGEP pass creates variadic bases that can be used
142 // by multiple GEPs. Run GVN or EarlyCSE to really reuse them. GVN generates
143 // significantly better code than EarlyCSE for some of our benchmarks.
144 if (getOptLevel() == CodeGenOpt::Aggressive)
145 addPass(createGVNPass());
147 addPass(createEarlyCSEPass());
148 // Both FavorNonGenericAddrSpaces and SeparateConstOffsetFromGEP may leave
149 // some dead code. We could remove dead code in an ad-hoc manner, but that
150 // requires manual work and might be error-prone.
152 // The FavorNonGenericAddrSpaces pass shortcuts unnecessary addrspacecasts,
153 // and leave them unused.
155 // SeparateConstOffsetFromGEP rebuilds a new index from the old index, and the
156 // old index and some of its intermediate results may become unused.
157 addPass(createDeadCodeEliminationPass());
160 bool NVPTXPassConfig::addInstSelector() {
161 const NVPTXSubtarget &ST =
162 getTM<NVPTXTargetMachine>().getSubtarget<NVPTXSubtarget>();
164 addPass(createLowerAggrCopies());
165 addPass(createAllocaHoisting());
166 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
168 if (!ST.hasImageHandles())
169 addPass(createNVPTXReplaceImageHandlesPass());
174 bool NVPTXPassConfig::addPreRegAlloc() { return false; }
175 bool NVPTXPassConfig::addPostRegAlloc() {
176 addPass(createNVPTXPrologEpilogPass());
180 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
181 return nullptr; // No reg alloc
184 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
185 assert(!RegAllocPass && "NVPTX uses no regalloc!");
186 addPass(&PHIEliminationID);
187 addPass(&TwoAddressInstructionPassID);
190 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
191 assert(!RegAllocPass && "NVPTX uses no regalloc!");
193 addPass(&ProcessImplicitDefsID);
194 addPass(&LiveVariablesID);
195 addPass(&MachineLoopInfoID);
196 addPass(&PHIEliminationID);
198 addPass(&TwoAddressInstructionPassID);
199 addPass(&RegisterCoalescerID);
201 // PreRA instruction scheduling.
202 if (addPass(&MachineSchedulerID))
203 printAndVerify("After Machine Scheduling");
206 addPass(&StackSlotColoringID);
208 // FIXME: Needs physical registers
209 //addPass(&PostRAMachineLICMID);
211 printAndVerify("After StackSlotColoring");
214 void NVPTXPassConfig::addMachineSSAOptimization() {
215 // Pre-ra tail duplication.
216 if (addPass(&EarlyTailDuplicateID))
217 printAndVerify("After Pre-RegAlloc TailDuplicate");
219 // Optimize PHIs before DCE: removing dead PHI cycles may make more
220 // instructions dead.
221 addPass(&OptimizePHIsID);
223 // This pass merges large allocas. StackSlotColoring is a different pass
224 // which merges spill slots.
225 addPass(&StackColoringID);
227 // If the target requests it, assign local variables to stack slots relative
228 // to one another and simplify frame index references where possible.
229 addPass(&LocalStackSlotAllocationID);
231 // With optimization, dead code should already be eliminated. However
232 // there is one known exception: lowered code for arguments that are only
233 // used by tail calls, where the tail calls reuse the incoming stack
234 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
235 addPass(&DeadMachineInstructionElimID);
236 printAndVerify("After codegen DCE pass");
238 // Allow targets to insert passes that improve instruction level parallelism,
239 // like if-conversion. Such passes will typically need dominator trees and
240 // loop info, just like LICM and CSE below.
242 printAndVerify("After ILP optimizations");
244 addPass(&MachineLICMID);
245 addPass(&MachineCSEID);
247 addPass(&MachineSinkingID);
248 printAndVerify("After Machine LICM, CSE and Sinking passes");
250 addPass(&PeepholeOptimizerID);
251 printAndVerify("After codegen peephole optimization pass");