1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "NVPTXTargetObjectFile.h"
20 #include "llvm/Analysis/Passes.h"
21 #include "llvm/CodeGen/AsmPrinter.h"
22 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/IRPrintingPasses.h"
27 #include "llvm/IR/Verifier.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCStreamer.h"
31 #include "llvm/MC/MCSubtargetInfo.h"
32 #include "llvm/PassManager.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/FormattedStream.h"
36 #include "llvm/Support/TargetRegistry.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetLowering.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
44 #include "llvm/Target/TargetSubtargetInfo.h"
45 #include "llvm/Transforms/Scalar.h"
50 void initializeNVVMReflectPass(PassRegistry&);
51 void initializeGenericToNVVMPass(PassRegistry&);
52 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
53 void initializeNVPTXFavorNonGenericAddrSpacesPass(PassRegistry &);
54 void initializeNVPTXLowerStructArgsPass(PassRegistry &);
57 extern "C" void LLVMInitializeNVPTXTarget() {
58 // Register the target.
59 RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
60 RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
62 // FIXME: This pass is really intended to be invoked during IR optimization,
63 // but it's very NVPTX-specific.
64 initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
65 initializeGenericToNVVMPass(*PassRegistry::getPassRegistry());
66 initializeNVPTXAssignValidGlobalNamesPass(*PassRegistry::getPassRegistry());
67 initializeNVPTXFavorNonGenericAddrSpacesPass(
68 *PassRegistry::getPassRegistry());
69 initializeNVPTXLowerStructArgsPass(*PassRegistry::getPassRegistry());
72 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
73 StringRef CPU, StringRef FS,
74 const TargetOptions &Options,
75 Reloc::Model RM, CodeModel::Model CM,
76 CodeGenOpt::Level OL, bool is64bit)
77 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
78 TLOF(make_unique<NVPTXTargetObjectFile>()),
79 Subtarget(TT, CPU, FS, *this, is64bit) {
83 void NVPTXTargetMachine32::anchor() {}
85 NVPTXTargetMachine32::NVPTXTargetMachine32(
86 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
87 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
89 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
91 void NVPTXTargetMachine64::anchor() {}
93 NVPTXTargetMachine64::NVPTXTargetMachine64(
94 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
95 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
97 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
100 class NVPTXPassConfig : public TargetPassConfig {
102 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
103 : TargetPassConfig(TM, PM) {}
105 NVPTXTargetMachine &getNVPTXTargetMachine() const {
106 return getTM<NVPTXTargetMachine>();
109 void addIRPasses() override;
110 bool addInstSelector() override;
111 bool addPreRegAlloc() override;
112 bool addPostRegAlloc() override;
113 void addMachineSSAOptimization() override;
115 FunctionPass *createTargetRegisterAllocator(bool) override;
116 void addFastRegAlloc(FunctionPass *RegAllocPass) override;
117 void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
119 } // end anonymous namespace
121 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
122 NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
126 void NVPTXTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
127 // Add first the target-independent BasicTTI pass, then our NVPTX pass. This
128 // allows the NVPTX pass to delegate to the target independent layer when
130 PM.add(createBasicTargetTransformInfoPass(this));
131 PM.add(createNVPTXTargetTransformInfoPass(this));
134 void NVPTXPassConfig::addIRPasses() {
135 // The following passes are known to not play well with virtual regs hanging
136 // around after register allocation (which in our case, is *all* registers).
137 // We explicitly disable them here. We do, however, need some functionality
138 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
139 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
140 disablePass(&PrologEpilogCodeInserterID);
141 disablePass(&MachineCopyPropagationID);
142 disablePass(&BranchFolderPassID);
143 disablePass(&TailDuplicateID);
145 addPass(createNVPTXImageOptimizerPass());
146 TargetPassConfig::addIRPasses();
147 addPass(createNVPTXAssignValidGlobalNamesPass());
148 addPass(createGenericToNVVMPass());
149 addPass(createNVPTXFavorNonGenericAddrSpacesPass());
150 addPass(createSeparateConstOffsetFromGEPPass());
151 // The SeparateConstOffsetFromGEP pass creates variadic bases that can be used
152 // by multiple GEPs. Run GVN or EarlyCSE to really reuse them. GVN generates
153 // significantly better code than EarlyCSE for some of our benchmarks.
154 if (getOptLevel() == CodeGenOpt::Aggressive)
155 addPass(createGVNPass());
157 addPass(createEarlyCSEPass());
158 // Both FavorNonGenericAddrSpaces and SeparateConstOffsetFromGEP may leave
159 // some dead code. We could remove dead code in an ad-hoc manner, but that
160 // requires manual work and might be error-prone.
162 // The FavorNonGenericAddrSpaces pass shortcuts unnecessary addrspacecasts,
163 // and leave them unused.
165 // SeparateConstOffsetFromGEP rebuilds a new index from the old index, and the
166 // old index and some of its intermediate results may become unused.
167 addPass(createDeadCodeEliminationPass());
170 bool NVPTXPassConfig::addInstSelector() {
171 const NVPTXSubtarget &ST =
172 getTM<NVPTXTargetMachine>().getSubtarget<NVPTXSubtarget>();
174 addPass(createLowerAggrCopies());
175 addPass(createAllocaHoisting());
176 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
178 if (!ST.hasImageHandles())
179 addPass(createNVPTXReplaceImageHandlesPass());
184 bool NVPTXPassConfig::addPreRegAlloc() { return false; }
185 bool NVPTXPassConfig::addPostRegAlloc() {
186 addPass(createNVPTXPrologEpilogPass());
190 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
191 return nullptr; // No reg alloc
194 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
195 assert(!RegAllocPass && "NVPTX uses no regalloc!");
196 addPass(&PHIEliminationID);
197 addPass(&TwoAddressInstructionPassID);
200 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
201 assert(!RegAllocPass && "NVPTX uses no regalloc!");
203 addPass(&ProcessImplicitDefsID);
204 addPass(&LiveVariablesID);
205 addPass(&MachineLoopInfoID);
206 addPass(&PHIEliminationID);
208 addPass(&TwoAddressInstructionPassID);
209 addPass(&RegisterCoalescerID);
211 // PreRA instruction scheduling.
212 if (addPass(&MachineSchedulerID))
213 printAndVerify("After Machine Scheduling");
216 addPass(&StackSlotColoringID);
218 // FIXME: Needs physical registers
219 //addPass(&PostRAMachineLICMID);
221 printAndVerify("After StackSlotColoring");
224 void NVPTXPassConfig::addMachineSSAOptimization() {
225 // Pre-ra tail duplication.
226 if (addPass(&EarlyTailDuplicateID))
227 printAndVerify("After Pre-RegAlloc TailDuplicate");
229 // Optimize PHIs before DCE: removing dead PHI cycles may make more
230 // instructions dead.
231 addPass(&OptimizePHIsID);
233 // This pass merges large allocas. StackSlotColoring is a different pass
234 // which merges spill slots.
235 addPass(&StackColoringID);
237 // If the target requests it, assign local variables to stack slots relative
238 // to one another and simplify frame index references where possible.
239 addPass(&LocalStackSlotAllocationID);
241 // With optimization, dead code should already be eliminated. However
242 // there is one known exception: lowered code for arguments that are only
243 // used by tail calls, where the tail calls reuse the incoming stack
244 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
245 addPass(&DeadMachineInstructionElimID);
246 printAndVerify("After codegen DCE pass");
248 // Allow targets to insert passes that improve instruction level parallelism,
249 // like if-conversion. Such passes will typically need dominator trees and
250 // loop info, just like LICM and CSE below.
252 printAndVerify("After ILP optimizations");
254 addPass(&MachineLICMID);
255 addPass(&MachineCSEID);
257 addPass(&MachineSinkingID);
258 printAndVerify("After Machine LICM, CSE and Sinking passes");
260 addPass(&PeepholeOptimizerID);
261 printAndVerify("After codegen peephole optimization pass");