1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "NVPTXTargetObjectFile.h"
20 #include "llvm/Analysis/Passes.h"
21 #include "llvm/CodeGen/AsmPrinter.h"
22 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/IRPrintingPasses.h"
27 #include "llvm/IR/Verifier.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCStreamer.h"
31 #include "llvm/MC/MCSubtargetInfo.h"
32 #include "llvm/PassManager.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/FormattedStream.h"
36 #include "llvm/Support/TargetRegistry.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetLowering.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
44 #include "llvm/Target/TargetSubtargetInfo.h"
45 #include "llvm/Transforms/Scalar.h"
50 void initializeNVVMReflectPass(PassRegistry&);
51 void initializeGenericToNVVMPass(PassRegistry&);
52 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
53 void initializeNVPTXFavorNonGenericAddrSpacesPass(PassRegistry &);
54 void initializeNVPTXLowerStructArgsPass(PassRegistry &);
57 extern "C" void LLVMInitializeNVPTXTarget() {
58 // Register the target.
59 RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
60 RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
62 // FIXME: This pass is really intended to be invoked during IR optimization,
63 // but it's very NVPTX-specific.
64 initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
65 initializeGenericToNVVMPass(*PassRegistry::getPassRegistry());
66 initializeNVPTXAssignValidGlobalNamesPass(*PassRegistry::getPassRegistry());
67 initializeNVPTXFavorNonGenericAddrSpacesPass(
68 *PassRegistry::getPassRegistry());
69 initializeNVPTXLowerStructArgsPass(*PassRegistry::getPassRegistry());
72 static std::string computeDataLayout(bool is64Bit) {
73 std::string Ret = "e";
78 Ret += "-i64:64-v16:16-v32:32-n16:32:64";
83 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
84 StringRef CPU, StringRef FS,
85 const TargetOptions &Options,
86 Reloc::Model RM, CodeModel::Model CM,
87 CodeGenOpt::Level OL, bool is64bit)
88 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
89 TLOF(make_unique<NVPTXTargetObjectFile>()),
90 DL(computeDataLayout(is64bit)),
91 Subtarget(TT, CPU, FS, *this, is64bit) {
95 NVPTXTargetMachine::~NVPTXTargetMachine() {}
97 void NVPTXTargetMachine32::anchor() {}
99 NVPTXTargetMachine32::NVPTXTargetMachine32(
100 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
101 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
102 CodeGenOpt::Level OL)
103 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
105 void NVPTXTargetMachine64::anchor() {}
107 NVPTXTargetMachine64::NVPTXTargetMachine64(
108 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
109 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
110 CodeGenOpt::Level OL)
111 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
114 class NVPTXPassConfig : public TargetPassConfig {
116 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
117 : TargetPassConfig(TM, PM) {}
119 NVPTXTargetMachine &getNVPTXTargetMachine() const {
120 return getTM<NVPTXTargetMachine>();
123 void addIRPasses() override;
124 bool addInstSelector() override;
125 void addPostRegAlloc() override;
126 void addMachineSSAOptimization() override;
128 FunctionPass *createTargetRegisterAllocator(bool) override;
129 void addFastRegAlloc(FunctionPass *RegAllocPass) override;
130 void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
132 } // end anonymous namespace
134 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
135 NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
139 void NVPTXTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
140 // Add first the target-independent BasicTTI pass, then our NVPTX pass. This
141 // allows the NVPTX pass to delegate to the target independent layer when
143 PM.add(createBasicTargetTransformInfoPass(this));
144 PM.add(createNVPTXTargetTransformInfoPass(this));
147 void NVPTXPassConfig::addIRPasses() {
148 // The following passes are known to not play well with virtual regs hanging
149 // around after register allocation (which in our case, is *all* registers).
150 // We explicitly disable them here. We do, however, need some functionality
151 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
152 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
153 disablePass(&PrologEpilogCodeInserterID);
154 disablePass(&MachineCopyPropagationID);
155 disablePass(&BranchFolderPassID);
156 disablePass(&TailDuplicateID);
158 addPass(createNVPTXImageOptimizerPass());
159 TargetPassConfig::addIRPasses();
160 addPass(createNVPTXAssignValidGlobalNamesPass());
161 addPass(createGenericToNVVMPass());
162 addPass(createNVPTXFavorNonGenericAddrSpacesPass());
163 addPass(createSeparateConstOffsetFromGEPPass());
164 // The SeparateConstOffsetFromGEP pass creates variadic bases that can be used
165 // by multiple GEPs. Run GVN or EarlyCSE to really reuse them. GVN generates
166 // significantly better code than EarlyCSE for some of our benchmarks.
167 if (getOptLevel() == CodeGenOpt::Aggressive)
168 addPass(createGVNPass());
170 addPass(createEarlyCSEPass());
171 // Both FavorNonGenericAddrSpaces and SeparateConstOffsetFromGEP may leave
172 // some dead code. We could remove dead code in an ad-hoc manner, but that
173 // requires manual work and might be error-prone.
175 // The FavorNonGenericAddrSpaces pass shortcuts unnecessary addrspacecasts,
176 // and leave them unused.
178 // SeparateConstOffsetFromGEP rebuilds a new index from the old index, and the
179 // old index and some of its intermediate results may become unused.
180 addPass(createDeadCodeEliminationPass());
183 bool NVPTXPassConfig::addInstSelector() {
184 const NVPTXSubtarget &ST =
185 getTM<NVPTXTargetMachine>().getSubtarget<NVPTXSubtarget>();
187 addPass(createLowerAggrCopies());
188 addPass(createAllocaHoisting());
189 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
191 if (!ST.hasImageHandles())
192 addPass(createNVPTXReplaceImageHandlesPass());
197 void NVPTXPassConfig::addPostRegAlloc() {
198 addPass(createNVPTXPrologEpilogPass(), false);
201 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
202 return nullptr; // No reg alloc
205 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
206 assert(!RegAllocPass && "NVPTX uses no regalloc!");
207 addPass(&PHIEliminationID);
208 addPass(&TwoAddressInstructionPassID);
211 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
212 assert(!RegAllocPass && "NVPTX uses no regalloc!");
214 addPass(&ProcessImplicitDefsID);
215 addPass(&LiveVariablesID);
216 addPass(&MachineLoopInfoID);
217 addPass(&PHIEliminationID);
219 addPass(&TwoAddressInstructionPassID);
220 addPass(&RegisterCoalescerID);
222 // PreRA instruction scheduling.
223 if (addPass(&MachineSchedulerID))
224 printAndVerify("After Machine Scheduling");
227 addPass(&StackSlotColoringID);
229 // FIXME: Needs physical registers
230 //addPass(&PostRAMachineLICMID);
232 printAndVerify("After StackSlotColoring");
235 void NVPTXPassConfig::addMachineSSAOptimization() {
236 // Pre-ra tail duplication.
237 if (addPass(&EarlyTailDuplicateID))
238 printAndVerify("After Pre-RegAlloc TailDuplicate");
240 // Optimize PHIs before DCE: removing dead PHI cycles may make more
241 // instructions dead.
242 addPass(&OptimizePHIsID);
244 // This pass merges large allocas. StackSlotColoring is a different pass
245 // which merges spill slots.
246 addPass(&StackColoringID);
248 // If the target requests it, assign local variables to stack slots relative
249 // to one another and simplify frame index references where possible.
250 addPass(&LocalStackSlotAllocationID);
252 // With optimization, dead code should already be eliminated. However
253 // there is one known exception: lowered code for arguments that are only
254 // used by tail calls, where the tail calls reuse the incoming stack
255 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
256 addPass(&DeadMachineInstructionElimID);
257 printAndVerify("After codegen DCE pass");
259 // Allow targets to insert passes that improve instruction level parallelism,
260 // like if-conversion. Such passes will typically need dominator trees and
261 // loop info, just like LICM and CSE below.
263 printAndVerify("After ILP optimizations");
265 addPass(&MachineLICMID);
266 addPass(&MachineCSEID);
268 addPass(&MachineSinkingID);
269 printAndVerify("After Machine LICM, CSE and Sinking passes");
271 addPass(&PeepholeOptimizerID);
272 printAndVerify("After codegen peephole optimization pass");