1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Top-level implementation for the NVPTX target.
12 //===----------------------------------------------------------------------===//
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "NVPTXTargetObjectFile.h"
20 #include "NVPTXTargetTransformInfo.h"
21 #include "llvm/Analysis/Passes.h"
22 #include "llvm/CodeGen/AsmPrinter.h"
23 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/LegacyPassManager.h"
29 #include "llvm/IR/Verifier.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCInstrInfo.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/MC/MCSubtargetInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/FormattedStream.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 #include "llvm/Target/TargetSubtargetInfo.h"
46 #include "llvm/Transforms/Scalar.h"
51 void initializeNVVMReflectPass(PassRegistry&);
52 void initializeGenericToNVVMPass(PassRegistry&);
53 void initializeNVPTXAllocaHoistingPass(PassRegistry &);
54 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
55 void initializeNVPTXFavorNonGenericAddrSpacesPass(PassRegistry &);
56 void initializeNVPTXLowerStructArgsPass(PassRegistry &);
59 extern "C" void LLVMInitializeNVPTXTarget() {
60 // Register the target.
61 RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
62 RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
64 // FIXME: This pass is really intended to be invoked during IR optimization,
65 // but it's very NVPTX-specific.
66 initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
67 initializeGenericToNVVMPass(*PassRegistry::getPassRegistry());
68 initializeNVPTXAllocaHoistingPass(*PassRegistry::getPassRegistry());
69 initializeNVPTXAssignValidGlobalNamesPass(*PassRegistry::getPassRegistry());
70 initializeNVPTXFavorNonGenericAddrSpacesPass(
71 *PassRegistry::getPassRegistry());
72 initializeNVPTXLowerStructArgsPass(*PassRegistry::getPassRegistry());
75 static std::string computeDataLayout(bool is64Bit) {
76 std::string Ret = "e";
81 Ret += "-i64:64-v16:16-v32:32-n16:32:64";
86 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
87 StringRef CPU, StringRef FS,
88 const TargetOptions &Options,
89 Reloc::Model RM, CodeModel::Model CM,
90 CodeGenOpt::Level OL, bool is64bit)
91 : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM,
93 is64bit(is64bit), TLOF(make_unique<NVPTXTargetObjectFile>()),
94 Subtarget(TT, CPU, FS, *this) {
95 if (Triple(TT).getOS() == Triple::NVCL)
96 drvInterface = NVPTX::NVCL;
98 drvInterface = NVPTX::CUDA;
102 NVPTXTargetMachine::~NVPTXTargetMachine() {}
104 void NVPTXTargetMachine32::anchor() {}
106 NVPTXTargetMachine32::NVPTXTargetMachine32(
107 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
108 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
109 CodeGenOpt::Level OL)
110 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
112 void NVPTXTargetMachine64::anchor() {}
114 NVPTXTargetMachine64::NVPTXTargetMachine64(
115 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
116 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
117 CodeGenOpt::Level OL)
118 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
121 class NVPTXPassConfig : public TargetPassConfig {
123 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
124 : TargetPassConfig(TM, PM) {}
126 NVPTXTargetMachine &getNVPTXTargetMachine() const {
127 return getTM<NVPTXTargetMachine>();
130 void addIRPasses() override;
131 bool addInstSelector() override;
132 void addPostRegAlloc() override;
133 void addMachineSSAOptimization() override;
135 FunctionPass *createTargetRegisterAllocator(bool) override;
136 void addFastRegAlloc(FunctionPass *RegAllocPass) override;
137 void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
139 } // end anonymous namespace
141 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
142 NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
146 TargetIRAnalysis NVPTXTargetMachine::getTargetIRAnalysis() {
147 return TargetIRAnalysis(
148 [this](Function &) { return TargetTransformInfo(NVPTXTTIImpl(this)); });
151 void NVPTXPassConfig::addIRPasses() {
152 // The following passes are known to not play well with virtual regs hanging
153 // around after register allocation (which in our case, is *all* registers).
154 // We explicitly disable them here. We do, however, need some functionality
155 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
156 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
157 disablePass(&PrologEpilogCodeInserterID);
158 disablePass(&MachineCopyPropagationID);
159 disablePass(&BranchFolderPassID);
160 disablePass(&TailDuplicateID);
162 addPass(createNVPTXImageOptimizerPass());
163 TargetPassConfig::addIRPasses();
164 addPass(createNVPTXAssignValidGlobalNamesPass());
165 addPass(createGenericToNVVMPass());
166 addPass(createNVPTXFavorNonGenericAddrSpacesPass());
167 // FavorNonGenericAddrSpaces shortcuts unnecessary addrspacecasts, and leave
168 // them unused. We could remove dead code in an ad-hoc manner, but that
169 // requires manual work and might be error-prone.
170 addPass(createDeadCodeEliminationPass());
171 addPass(createSeparateConstOffsetFromGEPPass());
172 // ReassociateGEPs exposes more opportunites for SLSR. See
173 // the example in reassociate-geps-and-slsr.ll.
174 addPass(createStraightLineStrengthReducePass());
175 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
176 // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
177 // for some of our benchmarks.
178 if (getOptLevel() == CodeGenOpt::Aggressive)
179 addPass(createGVNPass());
181 addPass(createEarlyCSEPass());
184 bool NVPTXPassConfig::addInstSelector() {
185 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
187 addPass(createLowerAggrCopies());
188 addPass(createAllocaHoisting());
189 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
191 if (!ST.hasImageHandles())
192 addPass(createNVPTXReplaceImageHandlesPass());
197 void NVPTXPassConfig::addPostRegAlloc() {
198 addPass(createNVPTXPrologEpilogPass(), false);
201 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
202 return nullptr; // No reg alloc
205 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
206 assert(!RegAllocPass && "NVPTX uses no regalloc!");
207 addPass(&PHIEliminationID);
208 addPass(&TwoAddressInstructionPassID);
211 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
212 assert(!RegAllocPass && "NVPTX uses no regalloc!");
214 addPass(&ProcessImplicitDefsID);
215 addPass(&LiveVariablesID);
216 addPass(&MachineLoopInfoID);
217 addPass(&PHIEliminationID);
219 addPass(&TwoAddressInstructionPassID);
220 addPass(&RegisterCoalescerID);
222 // PreRA instruction scheduling.
223 if (addPass(&MachineSchedulerID))
224 printAndVerify("After Machine Scheduling");
227 addPass(&StackSlotColoringID);
229 // FIXME: Needs physical registers
230 //addPass(&PostRAMachineLICMID);
232 printAndVerify("After StackSlotColoring");
235 void NVPTXPassConfig::addMachineSSAOptimization() {
236 // Pre-ra tail duplication.
237 if (addPass(&EarlyTailDuplicateID))
238 printAndVerify("After Pre-RegAlloc TailDuplicate");
240 // Optimize PHIs before DCE: removing dead PHI cycles may make more
241 // instructions dead.
242 addPass(&OptimizePHIsID);
244 // This pass merges large allocas. StackSlotColoring is a different pass
245 // which merges spill slots.
246 addPass(&StackColoringID);
248 // If the target requests it, assign local variables to stack slots relative
249 // to one another and simplify frame index references where possible.
250 addPass(&LocalStackSlotAllocationID);
252 // With optimization, dead code should already be eliminated. However
253 // there is one known exception: lowered code for arguments that are only
254 // used by tail calls, where the tail calls reuse the incoming stack
255 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
256 addPass(&DeadMachineInstructionElimID);
257 printAndVerify("After codegen DCE pass");
259 // Allow targets to insert passes that improve instruction level parallelism,
260 // like if-conversion. Such passes will typically need dominator trees and
261 // loop info, just like LICM and CSE below.
263 printAndVerify("After ILP optimizations");
265 addPass(&MachineLICMID);
266 addPass(&MachineCSEID);
268 addPass(&MachineSinkingID);
269 printAndVerify("After Machine LICM, CSE and Sinking passes");
271 addPass(&PeepholeOptimizerID);
272 printAndVerify("After codegen peephole optimization pass");